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Searched +full:conf +full:- +full:clk (Results 1 – 25 of 162) sorted by relevance

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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
[all …]
/openbmc/linux/drivers/memory/
H A Datmel-ebi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
9 #include <linux/clk.h>
12 #include <linux/mfd/syscon/atmel-matrix.h>
13 #include <linux/mfd/syscon/atmel-smc.h>
17 #include <soc/at91/atmel-sfr.h>
41 struct atmel_ebi_dev_config *conf);
44 struct atmel_ebi_dev_config *conf);
46 struct atmel_ebi_dev_config *conf);
50 struct clk *clk; member
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
63 u32 conf; member
85 * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
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/openbmc/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
17 #include <linux/clk.h>
30 #include <linux/platform_data/dma-ep93xx.h>
31 #include <linux/platform_data/spi-ep93xx.h>
69 * struct ep93xx_spi - EP93xx SPI controller structure
70 * @clk: clock for the controller
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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/openbmc/linux/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
20 void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf) in atmel_smc_cs_conf_init() argument
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
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/openbmc/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_lvds_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
21 struct msm_drm_private *priv = lvds_pll->dev->dev_private; in get_kms()
22 return to_mdp4_kms(to_mdp_kms(priv->kms)); in get_kms()
30 } conf[32]; member
53 return &freqtbl[i-1]; in find_rate()
54 return &freqtbl[i-1]; in find_rate()
61 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); in mpd4_lvds_pll_enable()
64 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); in mpd4_lvds_pll_enable()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-lochnagar.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
11 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/lochnagar.h>
49 LN_PARENT("ln-none"),
50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
53 LN_PARENT("ln-cdc-clkout"),
54 LN_PARENT("ln-dsp-clkout"),
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H A Dclk-sparx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/microchip,sparx5.h>
59 const struct s5_pll_conf *conf) in s5_calc_freq() argument
61 unsigned long rate = parent_rate / conf->div; in s5_calc_freq()
63 if (conf->rot_ena) { in s5_calc_freq()
64 int sign = conf->rot_dir ? -1 : 1; in s5_calc_freq()
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
78 struct s5_pll_conf *conf) in s5_search_fractional() argument
84 memset(conf, 0, sizeof(*conf)); in s5_search_fractional()
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/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
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H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623n-bananapi-bpi-r2.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
12 model = "Bananapi BPI-R2";
13 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
16 stdout-path = &uart2;
17 tick-timer = &timer0;
20 reg_1p8v: regulator-1p8v {
21 compatible = "regulator-fixed";
22 regulator-name = "fixed-1.8V";
23 regulator-min-microvolt = <1800000>;
[all …]
/openbmc/linux/drivers/pinctrl/cirrus/
H A Dpinctrl-madera-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2018 Cirrus Logic
17 #include <linux/pinctrl/pinconf-generic.h>
25 #include "../pinctrl-utils.h"
27 #include "pinctrl-madera.h"
31 * NOTE: IDs are zero-indexed for coding convenience
77 * All single-pin functions can be mapped to any GPIO, however pinmux applies
81 * Since these do not correspond to anything in the actual hardware - they are
82 * merely an adaptation to pinctrl's view of the world - we use the same name
94 /* set of pin numbers for single-pin groups, zero-indexed */
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
11 #include <linux/clk.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
109 * @clk: clock of the controller.
131 struct clk *clk; member
157 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
[all …]
H A Dpinctrl-lantiq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/drivers/pinctrl/pinctrl-lantiq.h
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
28 #define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16) argument
29 #define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff) argument
100 struct clk *clk[5]; member
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
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/openbmc/linux/drivers/tty/serial/
H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
25 #include <linux/clk.h>
174 struct clk *clk; member
175 struct clk *pclk;
192 writel_relaxed(val, port->membase + off); in msm_write()
198 return readl_relaxed(port->membase + off); in msm_read()
210 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
222 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
230 * These registers don't exist so we change the clk input rate in msm_serial_set_mnd_regs()
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/openbmc/linux/drivers/pci/controller/
H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <linux/clk.h>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
111 struct clk *clk; member
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-ebaz4205.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 /include/ "zynq-7000.dtsi"
10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
28 ps-clk-frequency = <33333333>;
29 fclk-enable = <8>;
34 phy-mode = "mii";
35 phy-handle = <&phy>;
38 assigned-clocks = <&clkc 18>;
[all …]
H A Dzynq-microzed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
29 compatible = "usb-nop-xceiv";
30 #phy-cells = <0>;
35 ps-clk-frequency = <33333333>;
40 phy-mode = "rgmii-id";
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
13 #include <linux/clk.h>
33 #include <sound/hdmi-codec.h>
34 #include <media/cec-notifier.h>
44 #include "regs-hdmi.h"
82 u8 conf[32]; member
105 * required parents of clock when HDMI-PHY is respectively off or on.
135 struct clk **clk_gates;
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/openbmc/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzn1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
11 #include <linux/clk.h>
19 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
75 u32 conf[170]; member
83 * struct rzn1_pmx_func - describes rzn1 pinmux functions
95 * struct rzn1_pin_group - describes an rzn1 pin group
113 struct clk *clk; member
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/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
11 #include <linux/media-bus-format.h>
16 #include <linux/soc/mediatek/mtk-mmsys.h>
71 struct clk *engine_clk;
72 struct clk *pixel_clk;
73 struct clk *tvd_clk;
76 const struct mtk_dpi_conf *conf; member
120 * struct mtk_dpi_conf - Configuration of mediatek dpi.
163 u32 tmp = readl(dpi->regs + offset) & ~mask; in mtk_dpi_mask()
[all …]

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