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/openbmc/u-boot/arch/mips/lib/
H A Dasm-offsets.c1 // SPDX-License-Identifier: GPL-2.0+
3 * offset.c: Calculate pt_regs and task_struct offsets.
9 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
20 OFFSET(PT_R0, pt_regs, regs[0]); in output_ptreg_defines()
21 OFFSET(PT_R1, pt_regs, regs[1]); in output_ptreg_defines()
22 OFFSET(PT_R2, pt_regs, regs[2]); in output_ptreg_defines()
23 OFFSET(PT_R3, pt_regs, regs[3]); in output_ptreg_defines()
24 OFFSET(PT_R4, pt_regs, regs[4]); in output_ptreg_defines()
25 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
26 OFFSET(PT_R6, pt_regs, regs[6]); in output_ptreg_defines()
[all …]
/openbmc/openbmc/poky/meta/recipes-kernel/lttng/lttng-tools/
H A D0001-compat-Define-off64_t-as-off_t-on-linux.patch2 From: =?UTF-8?q?J=C3=A9r=C3=A9mie=20Galarneau?=
3 <jeremie.galarneau@efficios.com>
4 Date: Tue, 17 Jan 2023 16:57:35 -0500
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
15 "arrange for 64-bit file offsets, known as large-file support."
17 As such, it is safe to assume off_t is 64-bit wide. This is checked by a
18 static_assert to catch any platform where autoconf would let a 32-bit
21 Submitted [https://review.lttng.org/c/lttng-tools/+/9268]
[all …]
/openbmc/qemu/block/
H A Dreqlist.c8 * Dietmar Maurer (dietmar@proxmox.com)
9 * Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
12 * See the COPYING file in the top-level directory.
20 void reqlist_init_req(BlockReqList *reqs, BlockReq *req, int64_t offset, in reqlist_init_req() argument
24 .offset = offset, in reqlist_init_req()
27 qemu_co_queue_init(&req->wait_queue); in reqlist_init_req()
31 BlockReq *reqlist_find_conflict(BlockReqList *reqs, int64_t offset, in reqlist_find_conflict() argument
37 if (ranges_overlap(offset, bytes, r->offset, r->bytes)) { in reqlist_find_conflict()
45 bool coroutine_fn reqlist_wait_one(BlockReqList *reqs, int64_t offset, in reqlist_wait_one() argument
48 BlockReq *r = reqlist_find_conflict(reqs, offset, bytes); in reqlist_wait_one()
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Tom Cubie <tangliang@allwinnertech.com>
15 u32 offset = GPIO_CFG_OFFSET(bank_offset); in sunxi_gpio_set_cfgbank() local
17 clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); in sunxi_gpio_set_cfgbank()
31 u32 offset = GPIO_CFG_OFFSET(bank_offset); in sunxi_gpio_get_cfgbank() local
34 cfg = readl(&pio->cfg[0] + index); in sunxi_gpio_get_cfgbank()
35 cfg >>= offset; in sunxi_gpio_get_cfgbank()
52 u32 offset = GPIO_DRV_OFFSET(pin); in sunxi_gpio_set_drv() local
[all …]
/openbmc/qemu/hw/display/
H A Ddpcd.c5 * http://www.greensocs.com/ , email: info@greensocs.com
8 * Frederic Konrad <fred.konrad@greensocs.com>
45 * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
52 static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size) in dpcd_read() argument
57 if (offset < DPCD_READABLE_AREA) { in dpcd_read()
58 ret = e->dpcd_info[offset]; in dpcd_read()
60 qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", in dpcd_read()
61 offset); in dpcd_read()
64 trace_dpcd_read(offset, ret); in dpcd_read()
69 static void dpcd_write(void *opaque, hwaddr offset, uint64_t value, in dpcd_write() argument
[all …]
/openbmc/openbmc/meta-google/dynamic-layers/nuvoton-layer/recipes-bsp/images/npcm7xx-igps/
H A D0001-Set-FIU0_DRD_CFG-and-FIU_Clk_divider-for-gbmc-hoth.patch2 From: Benjamin Fair <benjaminfair@google.com>
3 Date: Wed, 20 Nov 2019 14:20:38 -0800
8 Signed-off-by: Benjamin Fair <benjaminfair@google.com>
9 Signed-off-by: Brandon Kim <brandonkim@google.com>
11 ---
12 ImageGeneration/references/BootBlockAndHeader_EB.xml | 4 ++--
13 ImageGeneration/references/UbootHeader_EB.xml | 2 +-
14 2 files changed, 3 insertions(+), 3 deletions(-)
16 diff --git a/ImageGeneration/references/BootBlockAndHeader_EB.xml b/ImageGeneration/references/Boot…
18 --- a/ImageGeneration/references/BootBlockAndHeader_EB.xml
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
7 * Kamil Lulko, <kamil.lulko@gmail.com>
29 uint32_t vtor; /* Vector Table Offset Register */
31 uint32_t scr; /* offset 0x10: System Control Register */
32 uint32_t ccr; /* offset 0x14: Config and Control Register */
33 uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
34 uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
35 uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
36 uint32_t shcrs; /* offset 0x24: System Handler Control State */
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/libx86-1/libx86-1.1/
H A D0001-Fix-type-of-the-void-pointer-assignment.patch2 From: Khem Raj <raj.khem@gmail.com>
3 Date: Fri, 2 Sep 2022 00:28:05 -0700
8 x86-common.c:216:9: error: incompatible integer to pointer conversion assigning to 'void *' from 'l…
9 offset = mem_info.offset - REAL_MEM_BASE;
12 Upstream-Status: Pending
13 Signed-off-by: Khem Raj <raj.khem@gmail.com>
14 ---
15 x86-common.c | 2 +-
16 1 file changed, 1 insertion(+), 1 deletion(-)
18 diff --git a/x86-common.c b/x86-common.c
[all …]
/openbmc/openbmc/poky/meta/recipes-graphics/piglit/piglit/
H A D0001-tests-Fix-narrowing-errors-seen-with-clang.patch2 From: Khem Raj <raj.khem@gmail.com>
3 Date: Wed, 3 May 2023 21:59:43 -0700
7 piglit-test-pattern.cpp:656:26: error: type 'float' cannot be narrowed to 'int' in initiali
8 zer list [-Wc++11-narrowing]
10 Upstream-Status: Submitted [https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/807]
11 Signed-off-by: Khem Raj <raj.khem@gmail.com>
12 ---
13 .../spec/ext_framebuffer_multisample/draw-buffers-common.cpp | 4 ++--
14 tests/util/piglit-test-pattern.cpp | 4 ++--
15 2 files changed, 4 insertions(+), 4 deletions(-)
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/strace/strace/
H A D0002-tests-Replace-off64_t-with-off_t.patch2 From: Khem Raj <raj.khem@gmail.com>
3 Date: Thu, 15 Dec 2022 15:56:13 -0800
9 Upstream-Status: Submitted [https://github.com/strace/strace/pull/230]
10 Signed-off-by: Khem Raj <raj.khem@gmail.com>
11 ---
12 tests/readahead.c | 2 +-
13 tests/sync_file_range.c | 4 ++--
14 tests/sync_file_range2.c | 4 ++--
15 3 files changed, 5 insertions(+), 5 deletions(-)
17 diff --git a/tests/readahead.c b/tests/readahead.c
[all …]
/openbmc/qemu/hw/misc/
H A Darm_integrator_debug.c9 …* https://developer.arm.com/documentation/dui0159/b/peripherals-and-interfaces/debug-leds-and-dip…
11 * Copyright (c) 2013 Alex Bennée <alex@bennee.com>
14 * See the COPYING file in the top-level directory.
32 static uint64_t intdbg_control_read(void *opaque, hwaddr offset, in intdbg_control_read() argument
35 switch (offset >> 2) { in intdbg_control_read()
41 __func__, offset, size); in intdbg_control_read()
45 "%s: Bad offset %" HWADDR_PRIx, in intdbg_control_read()
46 __func__, offset); in intdbg_control_read()
51 static void intdbg_control_write(void *opaque, hwaddr offset, in intdbg_control_write() argument
54 switch (offset >> 2) { in intdbg_control_write()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dmc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * NVIDIA Corporation <www.nvidia.com>
14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dmc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * NVIDIA Corporation <www.nvidia.com>
14 u32 reserved0[3]; /* offset 0x00 - 0x08 */
15 u32 mc_emem_cfg; /* offset 0x0C */
16 u32 mc_emem_adr_cfg; /* offset 0x10 */
17 u32 mc_emem_arb_cfg0; /* offset 0x14 */
18 u32 mc_emem_arb_cfg1; /* offset 0x18 */
19 u32 mc_emem_arb_cfg2; /* offset 0x1C */
20 u32 reserved1; /* offset 0x20 */
21 u32 mc_gart_cfg; /* offset 0x24 */
[all …]
/openbmc/openbmc/meta-openembedded/meta-filesystems/recipes-utils/f2fs-tools/f2fs-tools/
H A D0002-f2fs_io-Define-_FILE_OFFSET_BITS-64.patch2 From: Khem Raj <raj.khem@gmail.com>
3 Date: Wed, 21 Dec 2022 18:23:03 -0800
11 Upstream-Status: Submitted [https://lore.kernel.org/linux-f2fs-devel/20221222022830.976309-2-raj.kh…
12 Signed-off-by: Khem Raj <raj.khem@gmail.com>
13 ---
14 lib/libf2fs_io.c | 4 +++-
15 tools/f2fs_io/f2fs_io.c | 4 ++--
16 2 files changed, 5 insertions(+), 3 deletions(-)
18 --- a/lib/libf2fs_io.c
20 @@ -11,7 +11,9 @@
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dmc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * NVIDIA Corporation <www.nvidia.com>
14 u32 reserved0[4]; /* offset 0x00 - 0x0C */
15 u32 mc_smmu_config; /* offset 0x10 */
16 u32 mc_smmu_tlb_config; /* offset 0x14 */
17 u32 mc_smmu_ptc_config; /* offset 0x18 */
18 u32 mc_smmu_ptb_asid; /* offset 0x1C */
19 u32 mc_smmu_ptb_data; /* offset 0x20 */
20 u32 reserved1[3]; /* offset 0x24 - 0x2C */
21 u32 mc_smmu_tlb_flush; /* offset 0x30 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Duart.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * NVIDIA Corporation <www.nvidia.com>
12 uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
13 uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
14 uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
15 uint uart_lcr; /* UART_LCR_0, offset 0C */
16 uint uart_mcr; /* UART_MCR_0, offset 10 */
17 uint uart_lsr; /* UART_LSR_0, offset 14 */
18 uint uart_msr; /* UART_MSR_0, offset 18 */
19 uint uart_spr; /* UART_SPR_0, offset 1C */
[all …]
H A Dscu.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * NVIDIA Corporation <www.nvidia.com>
12 uint scu_ctrl; /* SCU Control Register, offset 00 */
13 uint scu_cfg; /* SCU Config Register, offset 04 */
14 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
15 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
16 uint scu_reserved0[12]; /* reserved, offset 10-3C */
17 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
18 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
19 uint scu_reserved1[2]; /* reserved, offset 48-4C */
[all …]
/openbmc/u-boot/drivers/dfu/
H A Ddfu_ram.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Afzal Mohammed <afzal.mohd.ma@gmail.com>
8 * author: Lukasz Majewski <l.majewski@samsung.com>
17 u64 offset, void *buf, long *len) in dfu_transfer_medium_ram() argument
19 if (dfu->layout != DFU_RAM_ADDR) { in dfu_transfer_medium_ram()
20 pr_err("unsupported layout: %s\n", dfu_get_layout(dfu->layout)); in dfu_transfer_medium_ram()
21 return -EINVAL; in dfu_transfer_medium_ram()
24 if (offset > dfu->data.ram.size) { in dfu_transfer_medium_ram()
26 return -EINVAL; in dfu_transfer_medium_ram()
30 memcpy(dfu->data.ram.start + offset, buf, *len); in dfu_transfer_medium_ram()
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/python/python3-cffi/
H A D0001-Cast-offset-to-size_t-to-avoid-c-11-narrowing-warnin.patch2 From: triallax <triallax@tutanota.com>
4 Subject: [PATCH] Cast offset to size_t to avoid c++11-narrowing warning (#92)
8 …3:10: error: non-constant-expression cannot be narrowed from type 'long' to 'size_t' (aka 'unsigne…
9 583 | { "a", ((char *)&((foo_t)4096)->a) - (char *)4096,
12 583 | { "a", ((char *)&((foo_t)4096)->a) - (char *)4096,
16 Upstream-Status: Backport [https://github.com/python-cffi/cffi/pull/92]
17 Signed-off-by: Khem Raj <raj.khem@gmail.com>
18 ---
19 src/cffi/recompiler.py | 2 +-
20 1 file changed, 1 insertion(+), 1 deletion(-)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dflow.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
11 u32 halt_cpu_events; /* offset 0x00 */
12 u32 halt_cop_events; /* offset 0x04 */
13 u32 cpu_csr; /* offset 0x08 */
14 u32 cop_csr; /* offset 0x0c */
15 u32 xrq_events; /* offset 0x10 */
16 u32 halt_cpu1_events; /* offset 0x14 */
17 u32 cpu1_csr; /* offset 0x18 */
[all …]
/openbmc/openbmc/meta-phosphor/recipes-phosphor/ipmi/ipmitool/
H A D0001-Fru-Fix-edit-field-not-checking-area-existence.patch2 From: Alex Schendel <alex.schendel@intel.com>
3 Date: Fri, 9 Jun 2023 16:35:24 -0700
9 1. If the FRU is shrinking and a FRU area does not exist (offset 0),
10 ipmitool may attempt to shift it forwards (decrementing the offset).
11 This results in a wraparound to 0xFF, leaving an erroneous field offset.
20 1. Confirming that a area's does not have an offset of 0x00 before
22 2. Ensuring that the area's offset is after the area that was modified
31 Note that the Multi Record area now has an offset of 0xFF.
36 Note that the Multi Record area retains its offset of 0x00.
41 Offset: 0
[all …]
/openbmc/qemu/util/
H A Dbitops.c3 * Written by David Howells (dhowells@redhat.com)
5 * Written by Rusty Russell <rusty@rustcorp.com.au>
21 unsigned long offset) in find_next_bit() argument
23 const unsigned long *p = addr + BIT_WORD(offset); in find_next_bit()
24 unsigned long result = offset & ~(BITS_PER_LONG-1); in find_next_bit()
27 if (offset >= size) { in find_next_bit()
30 size -= result; in find_next_bit()
31 offset %= BITS_PER_LONG; in find_next_bit()
32 if (offset) { in find_next_bit()
34 tmp &= (~0UL << offset); in find_next_bit()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dflow.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2013
4 * NVIDIA Corporation <www.nvidia.com>
11 u32 halt_cpu_events; /* offset 0x00 */
12 u32 halt_cop_events; /* offset 0x04 */
13 u32 cpu_csr; /* offset 0x08 */
14 u32 cop_csr; /* offset 0x0c */
15 u32 xrq_events; /* offset 0x10 */
16 u32 halt_cpu1_events; /* offset 0x14 */
17 u32 cpu1_csr; /* offset 0x18 */
[all …]
/openbmc/u-boot/drivers/video/sunxi/
H A Dsimplefb_common.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
6 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
14 int offset, ret; in sunxi_simplefb_fdt_match() local
17 offset = fdt_node_offset_by_compatible(blob, -1, in sunxi_simplefb_fdt_match()
18 "allwinner,simple-framebuffer"); in sunxi_simplefb_fdt_match()
19 while (offset >= 0) { in sunxi_simplefb_fdt_match()
20 ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline", in sunxi_simplefb_fdt_match()
24 offset = fdt_node_offset_by_compatible(blob, offset, in sunxi_simplefb_fdt_match()
25 "allwinner,simple-framebuffer"); in sunxi_simplefb_fdt_match()
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dsimplefb_common.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
6 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
14 int offset, ret; in meson_simplefb_fdt_match() local
17 offset = fdt_node_offset_by_compatible(blob, -1, in meson_simplefb_fdt_match()
18 "amlogic,simple-framebuffer"); in meson_simplefb_fdt_match()
19 while (offset >= 0) { in meson_simplefb_fdt_match()
20 ret = fdt_stringlist_search(blob, offset, "amlogic,pipeline", in meson_simplefb_fdt_match()
24 offset = fdt_node_offset_by_compatible(blob, offset, in meson_simplefb_fdt_match()
25 "amlogic,simple-framebuffer"); in meson_simplefb_fdt_match()
[all …]

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