Home
last modified time | relevance | path

Searched +full:clocks +full:- +full:timing (Results 1 – 25 of 400) sorted by relevance

12345678910>>...16

/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
[all …]
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
28 clocks:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
28 compatible = "xlnx,v-tc-6.1";
31 clocks = <&clkc 15>;
H A Dxlnx,v-tpg.txt2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
11 TPG versions backward-compatible with previous versions should list all
14 - reg: Physical base address and length of the registers set for the device.
16 - clocks: Reference to the video core clock.
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
21 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
13 #include <dm/device-internal.h>
14 #include <dm/uclass-internal.h>
56 enum hdmi_compatible compat = dev_get_driver_data(priv->dev); in meson_hdmi_is_compatible()
66 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
67 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
70 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
71 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
80 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dimx-weim.txt5 wireless and mobile applications that use low-power technology.
11 - compatible: Should contain one of the following:
12 "fsl,imx1-weim"
13 "fsl,imx27-weim"
14 "fsl,imx51-weim"
15 "fsl,imx50-weim"
16 "fsl,imx6q-weim"
17 - reg: A resource specifier for the register space
19 - clocks: the clock, see the example below.
20 - #address-cells: Must be set to 2 to allow memory address translation
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt3 - compatible : "st,stm32-fmc"
4 - reg : fmc controller base address
5 - clocks : fmc controller clock
6 u-boot,dm-pre-reloc: flag to initialize memory before relocation.
8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
32 compatible = "st,stm32-fmc";
34 clocks = <&rcc 0 64>;
[all …]
H A Dst,stm32mp1-ddr.txt3 --------------------
5 --------------------
6 - compatible : Should be "st,stm32mp1-ddr"
7 - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
8 - clocks : controller clocks handle
9 - clock-names : associated controller clock names
11 at phy level according the expected value in "mem-speed" field
17 ----------------
18 - st,mem-name : name for DDR configuration, simple string for information
19 - st,mem-speed : DDR expected speed for the setting in MHz
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
17 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
18 clock-names = "emc-parent";
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
13 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
13 clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Ddwmmc.txt4 . Embedded Multimedia Cards (EMMC-version 4.5)
5 . Secure Digital memory (SD mem-version 2.0)
6 . Secure Digital I/O (SDIO-version 3.0)
7 . Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
14 - compatible: should be
15 - samsung,exynos-dwmmc: for exynos platforms
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
24 - #address-cells: should be 1.
25 - #size-cells: should be 0.
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-eukrea-cpuimx27.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
18 clk14745600: clk-uart {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <14745600>;
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_fec>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
14 special extensions to add functionality, is a high-performance dual-port
21 const: ceva,ahci-1v84
26 clocks:
29 dma-coherent: true
37 power-domains:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
27 clocks:
30 clock-names:
[all …]
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
44 clocks:
47 clock-names:
[all …]
H A Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c1 // SPDX-License-Identifier: MIT
184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu()
194 if (dc->config.use_default_clock_table == false) { in dcn314_update_bw_bounding_box_fpu()
195 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn314_update_bw_bounding_box_fpu()
196 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
198 if (bw_params->dram_channel_width_bytes > 0) in dcn314_update_bw_bounding_box_fpu()
199 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn314_update_bw_bounding_box_fpu()
201 if (bw_params->num_channels > 0) in dcn314_update_bw_bounding_box_fpu()
202 dcn3_14_soc.num_chans = bw_params->num_channels; in dcn314_update_bw_bounding_box_fpu()
205 ASSERT(clk_table->num_entries); in dcn314_update_bw_bounding_box_fpu()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dvf610-nfc.txt7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
27 - compatible: Should be set to "fsl,vf610-nfc-cs".
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
H A Drockchip-dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
31 - nvidia,tegra124-car
32 - nvidia,tegra132-car
37 '#clock-cells':
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
8 compatible = "ti,am654-ddrss";
12 reg-names = "ss", "ctl", "phy";
13 clocks = <&k3_clks 20 0>;
14 power-domains = <&k3_pds 20>,
16 assigned-clocks = <&k3_clks 20 1>;
17 assigned-clock-rates = <DDR_PLL_FREQUENCY>;
18 u-boot,dm-spl;
20 ti,ctl-reg = <
[all …]

12345678910>>...16