Lines Matching +full:clocks +full:- +full:timing
3 --------------------
5 --------------------
6 - compatible : Should be "st,stm32mp1-ddr"
7 - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
8 - clocks : controller clocks handle
9 - clock-names : associated controller clock names
11 at phy level according the expected value in "mem-speed" field
17 ----------------
18 - st,mem-name : name for DDR configuration, simple string for information
19 - st,mem-speed : DDR expected speed for the setting in MHz
20 - st,mem-size : DDR mem size in byte
24 -----------------------
25 - st,ctl-reg : controleur values depending of the DDR type
54 - st,ctl-timing : controleur values depending of frequency and timing parameter
70 - st,ctl-map : controleur values depending of address mapping
82 - st,ctl-perf : controleur values depending of performance and scheduling
103 ----------------
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
118 - st,phy-timing : phy values depending of frequency and timing parameter of DDR
131 - st,phy-cal : phy cal depending of calibration or tuning of DDR
150 u-boot,dm-spl;
153 u-boot,dm-spl;
154 u-boot,dm-pre-reloc;
156 compatible = "st,stm32mp1-ddr";
161 clocks = <&rcc_clk AXIDCG>,
168 clock-names = "axidcg",
175 st,mem-name = "DDR3 2x4Gb 533MHz";
176 st,mem-speed = <533>;
177 st,mem-size = <0x40000000>;
179 st,ctl-reg = <
207 st,ctl-timing = <
222 st,ctl-map = <
234 st,ctl-perf = <
254 st,phy-reg = <
268 st,phy-timing = <
281 st,phy-cal = <