/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | brcm,kona-ccu.txt | 4 clock control units (CCUs). A CCU is a clock provider that manages 5 a set of clock signals. Each CCU is represented by a node in the 8 This binding uses the common clock binding: 9 Documentation/devicetree/bindings/clock/clock-bindings.txt 12 - compatible 13 Shall have a value of the form "brcm,<model>-<which>-ccu", 16 "brcm,bcm11351-root-ccu" 19 - reg 21 containing clock control registers 22 - #clock-cells [all …]
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H A D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. 5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf 7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output 8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only 9 3 output clocks are accessible. The internal structure of the clock 15 - compatible: shall be one of the following: 16 "silabs,si5351a" - Si5351a, QFN20 package 17 "silabs,si5351a-msop" - Si5351a, MSOP10 package 18 "silabs,si5351b" - Si5351b, QFN20 package 19 "silabs,si5351c" - Si5351c, QFN20 package [all …]
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/openbmc/linux/sound/soc/sh/ |
H A D | fsi.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // Fifo-attached Serial Interface (FSI) support for SH7724 12 #include <linux/dma-mapping.h> 42 /* master register */ 102 #define SE (1 << 0) /* Fix the master clock */ 166 * |<-------------------- period--------------------->| 169 * ||<----- frame ----->|<------ frame ----->| ... | 170 * |+--------------------+--------------------+- ... | 172 * |+--------------------+--------------------+- ... | 185 * --> go to codecs [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 20 - enum: 21 - qcom,pcie-apq8064 22 - qcom,pcie-apq8084 23 - qcom,pcie-ipq4019 24 - qcom,pcie-ipq6018 [all …]
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/openbmc/linux/Documentation/sound/soc/ |
H A D | clocking.rst | 9 Master Clock 10 ------------ 12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK 13 or SYSCLK). This audio master clock can be derived from a number of sources 14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct 17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that 19 power). Other master clocks are fixed at a set frequency (i.e. crystals). 23 ---------- 24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to 25 as BCLK). This clock is used to drive the digital audio data across the link [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/sound/simple-card.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 14 frame-master: 15 description: Indicates dai-link frame master. 18 bitclock-master: 19 description: Indicates dai-link bit clock master 22 frame-inversion: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/i3c/ |
H A D | silvaco,i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Silvaco I3C master 10 - Conor Culhane <conor.culhane@silvaco.com> 13 - $ref: i3c.yaml# 17 const: silvaco,i3c-master-v1 27 - description: system clock 28 - description: bus clock [all …]
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H A D | cdns,i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/i3c/cdns,i3c-master.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Cadence I3C master block 10 - Boris Brezillon <bbrezillon@kernel.org> 13 - $ref: i3c.yaml# 17 const: cdns,i3c-master 25 clock-names: 27 - const: pclk [all …]
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/openbmc/linux/Documentation/devicetree/bindings/ata/ |
H A D | cortina,gemini-sata-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that 19 const: cortina,gemini-sata-bridge 28 reset-names: 30 - const: sata0 31 - const: sata1 [all …]
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/openbmc/linux/Documentation/spi/ |
H A D | spi-summary.rst | 5 02-Feb-2012 8 ------------ 12 standardization body. SPI uses a master/slave configuration. 14 The three signal wires hold a clock (SCK, often on the order of 10 MHz), 15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, 17 clocking modes through which data is exchanged; mode-0 and mode-3 are most 18 commonly used. Each clock cycle shifts data out and data in; the clock 26 other signals, often including an interrupt to the master. 32 - SPI may be used for request/response style device protocols, as with 35 - It may also be used to stream data in either direction (half duplex), [all …]
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/openbmc/linux/sound/soc/mxs/ |
H A D | mxs-saif.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 #include <linux/dma-mapping.h> 14 #include <linux/clk-provider.h> 23 #include "mxs-saif.h" 31 * SAIF is a little different with other normal SOC DAIs on clock using. 33 * For MXS, two SAIF modules are instantiated on-chip. 34 * Each SAIF has a set of clock pins and can be operating in master 35 * mode simultaneously if they are connected to different off-chip codecs. 36 * Also, one of the two SAIFs can master or drive the clock pins while the 37 * other SAIF, in slave mode, receives clocking from the master SAIF. [all …]
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/openbmc/linux/Documentation/driver-api/soundwire/ |
H A D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It 15 commands over a single two-pin interface. 17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR 20 (3) Clock scaling and optional multiple data lanes to give wide flexibility 23 (4) Device status monitoring, including interrupt-style alerts to the Master. 26 interfaces share the common Bus containing data and clock line. Each of the 35 Below figure shows an example of connectivity between a SoundWire Master and 38 +---------------+ +---------------+ 39 | | Clock Signal | | 40 | Master |-------+-------------------------------| Slave | [all …]
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/openbmc/linux/sound/soc/atmel/ |
H A D | atmel-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only 29 * ---- I2S Controller Register map ---- 44 * ---- Control Register (Write-only) ---- 48 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ 49 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ 55 * ---- Mode Register (Read/Write) ---- 101 /* Audio Clock to I2SC Master Clock ratio */ 106 /* Master Clock to fs ratio */ 111 /* Master Clock mode */ 113 /* 0: No master clock generated (selected clock drives I2SCK pin) */ [all …]
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/openbmc/linux/include/linux/soundwire/ |
H A D | sdw.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 29 /* SDW Master Device Number, not supported yet */ 75 * enum sdw_slave_status - Slave status 89 * enum sdw_clk_stop_type: clock stop operations 91 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare 92 * @SDW_CLK_POST_PREPARE: post clock stop prepare 93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare 94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare 104 * enum sdw_command_response - Command response as defined by SDW spec [all …]
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/openbmc/linux/Documentation/devicetree/bindings/iommu/ |
H A D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB. 9 - compatible: Must contain "qcom,apq8064-iommu". 10 - reg: Base address and size of the IOMMU registers. 11 - interrupts: Specifiers for the MMU fault interrupts. For instances that 12 support secure mode two interrupts must be specified, for non-secure and 15 - #iommu-cells: The number of cells needed to specify the stream id. This 17 - qcom,ncb: The total number of context banks in the IOMMU. 18 - clocks : List of clocks to be used during SMMU register access. See 19 Documentation/devicetree/bindings/clock/clock-bindings.txt 20 for information about the format. For each clock specified [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0 2 // spi-uniphier.c - Socionext UniPhier SPI controller driver 4 // Copyright 2016-2018 Socionext Inc. 29 struct spi_master *master; member 113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable() 115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable() 123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable() 125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable() 130 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); in uniphier_spi_set_mode() 134 * clock setting in uniphier_spi_set_mode() [all …]
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H A D | spi-sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright (C) 2012 - 2014 Allwinner Tech 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 78 struct spi_master *master; member 92 return readl(sspi->base_addr + reg); in sun4i_spi_read() 97 writel(value, sspi->base_addr + reg); in sun4i_spi_write() 138 while (len--) { in sun4i_spi_drain_fifo() 139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo() 140 if (sspi->rx_buf) in sun4i_spi_drain_fifo() 141 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo() [all …]
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/openbmc/linux/include/linux/clk/ |
H A D | at91_pmc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 8 * Power Management Controller (PMC) - System peripherals registers. 20 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ 21 #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ 23 #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ 24 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 25 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp… 27 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 28 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ [all …]
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/openbmc/linux/Documentation/i2c/ |
H A D | gpio-fault-injection.rst | 5 The GPIO based I2C bus master driver can be configured to provide fault 7 which is driven by the I2C bus master driver under test. The GPIO fault 9 master driver should handle gracefully. 12 'i2c-fault-injector' subdirectory in the Kernel debugfs filesystem, usually 15 injection. They will be described now along with their intended use-cases. 21 ----- 26 because the bus master under test will not be able to clock. It should detect 31 ----- 36 master under test should detect this condition and trigger a bus recovery (see 52 in a bus master driver, make sure you checked your hardware setup for such [all …]
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-soundwire-master | 1 What: /sys/bus/soundwire/devices/sdw-master-<N>/revision 2 /sys/bus/soundwire/devices/sdw-master-<N>/clk_stop_modes 3 /sys/bus/soundwire/devices/sdw-master-<N>/clk_freq 4 /sys/bus/soundwire/devices/sdw-master-<N>/clk_gears 5 /sys/bus/soundwire/devices/sdw-master-<N>/default_col 6 /sys/bus/soundwire/devices/sdw-master-<N>/default_frame_rate 7 /sys/bus/soundwire/devices/sdw-master-<N>/default_row 8 /sys/bus/soundwire/devices/sdw-master-<N>/dynamic_shape 9 /sys/bus/soundwire/devices/sdw-master-<N>/err_threshold 10 /sys/bus/soundwire/devices/sdw-master-<N>/max_clk_freq [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | dp83640.c | 1 // SPDX-License-Identifier: GPL-2.0+ 107 struct dp83640_clock *clock; member 133 /* we create one clock instance per MII bus */ 147 /* reference to our PTP hardware clock */ 165 static int chosen_phy = -1; 174 "The address of the PHY to use for the ancillary clock features"); 194 index = gpio_tab[CALIBRATE_GPIO] - 1; in dp83640_gpio_defaults() 198 index = gpio_tab[PEROUT_GPIO] - 1; in dp83640_gpio_defaults() 203 index = gpio_tab[i] - 1; in dp83640_gpio_defaults() 205 pd[index].chan = i - EXTTS0_GPIO; in dp83640_gpio_defaults() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | max2175.txt | 2 ----------------------------------------- 4 The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with 5 RF to Bits® front-end designed for software-defined radio solutions. 8 -------------------- 9 - compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner. 10 - clocks: clock specifier. 11 - port: child port node corresponding to the I2S output, in accordance with 13 Documentation/devicetree/bindings/media/video-interfaces.txt. The port 17 -------------------- 18 - maxim,master : phandle to the master tuner if it is a slave. This [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls1012a-frdm.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 /dts-v1/; 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include "fsl-ls1012a.dtsi" 15 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; 17 sys_mclk: clock-mclk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <25000000>; 23 reg_1p8v: regulator-1p8v { [all …]
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/openbmc/linux/Documentation/devicetree/bindings/fsi/ |
H A D | fsi-master-gpio.txt | 1 Device-tree bindings for gpio-based FSI master driver 2 ----------------------------------------------------- 5 - compatible = "fsi-master-gpio"; 6 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock 7 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal 10 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal 11 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable 12 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other 14 - no-gpio-delays; : Don't add extra delays between GPIO 21 fsi-master { [all …]
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H A D | fsi-master-ast-cf.txt | 1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver 2 ------------------------------------------------------------------------ 5 - compatible = 6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system 8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system 10 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock 11 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal 12 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal 13 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable 14 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other [all …]
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