/openbmc/linux/sound/pci/lola/ |
H A D | lola_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Support for Digigram Lola PCI-e boards 17 unsigned int freq; in lola_sample_rate_convert() local 21 case 0: freq = 48000; break; in lola_sample_rate_convert() 22 case 1: freq = 44100; break; in lola_sample_rate_convert() 23 case 2: freq = 32000; break; in lola_sample_rate_convert() 31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert() 32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert() 33 case (5 << 2): freq /= 2; break; in lola_sample_rate_convert() 34 case (6 << 2): freq /= 4; break; in lola_sample_rate_convert() [all …]
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/openbmc/linux/sound/drivers/vx/ |
H A D | vx_uer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 17 * vx_modify_board_clock - tell the board that its clock has been modified 32 * vx_modify_board_inputs - resync audio inputs 44 * vx_read_one_cbit - read one bit from UER config 52 mutex_lock(&chip->lock); in vx_read_one_cbit() 53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit() 62 mutex_unlock(&chip->lock); in vx_read_one_cbit() 67 * vx_write_one_cbit - write one bit to UER config 74 mutex_lock(&chip->lock); in vx_write_one_cbit() 82 mutex_unlock(&chip->lock); in vx_write_one_cbit() [all …]
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/openbmc/qemu/hw/misc/ |
H A D | imx25_ccm.c | 2 * IMX25 Clock Control Module 5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * See the COPYING file in the top-level directory. 112 uint32_t freq; in imx25_ccm_get_mpll_clk() local 115 if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], MPLL_BYPASS)) { in imx25_ccm_get_mpll_clk() 116 freq = CKIH_FREQ; in imx25_ccm_get_mpll_clk() 118 freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ); in imx25_ccm_get_mpll_clk() 121 DPRINTF("freq = %u\n", freq); in imx25_ccm_get_mpll_clk() 123 return freq; in imx25_ccm_get_mpll_clk() 128 uint32_t freq; in imx25_ccm_get_mcu_clk() local [all …]
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H A D | imx31_ccm.c | 2 * IMX31 Clock Control Module 5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * See the COPYING file in the top-level directory. 109 uint32_t freq = 0; in imx31_ccm_get_pll_ref_clk() local 112 if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) { in imx31_ccm_get_pll_ref_clk() 113 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) { in imx31_ccm_get_pll_ref_clk() 114 freq = CKIL_FREQ; in imx31_ccm_get_pll_ref_clk() 115 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) { in imx31_ccm_get_pll_ref_clk() 116 freq *= 1024; in imx31_ccm_get_pll_ref_clk() 120 freq = CKIH_FREQ; in imx31_ccm_get_pll_ref_clk() [all …]
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H A D | imx_ccm.c | 2 * IMX31 Clock Control Module 5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 8 * See the COPYING file in the top-level directory. 31 uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) in imx_ccm_get_clock_frequency() argument 33 uint32_t freq = 0; in imx_ccm_get_clock_frequency() local 36 if (klass->get_clock_frequency) { in imx_ccm_get_clock_frequency() 37 freq = klass->get_clock_frequency(dev, clock); in imx_ccm_get_clock_frequency() 40 DPRINTF("(clock = %d) = %u\n", clock, freq); in imx_ccm_get_clock_frequency() 42 return freq; in imx_ccm_get_clock_frequency() 50 int32_t freq; in imx_ccm_calc_pll() local [all …]
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/openbmc/u-boot/arch/arm/mach-imx/mx5/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) 77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk() 80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk() 91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk() 107 return -EINVAL; in enable_i2c_clk() 111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk() 113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk() [all …]
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/openbmc/u-boot/doc/device-tree-bindings/clock/ |
H A D | rockchip,rk3288-dmc.txt | 3 - compatible: "rockchip,rk3288-dmc", "syscon" 4 - rockchip,cru: this driver should access cru regs, so need get cru here 5 - rockchip,grf: this driver should access grf regs, so need get grf here 6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here 7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here 8 - rockchip,noc: this driver should access noc regs, so need get noc here 9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address 10 - clock: must include clock specifiers corresponding to entries in the clock-names property. 11 - clock-output-names: from common clock binding to override the default output clock name 13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0 [all …]
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/openbmc/u-boot/arch/arm/mach-imx/mx7/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/clock.h> 30 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in get_clocks() 32 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in get_clocks() 34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in get_clocks() 81 /* disable the clock gate first */ in enable_usboh3_clk() 91 /* enable the clock gate */ in enable_usboh3_clk() 115 reg = readl(&ccm_anatop->pll_arm); in decode_pll() 129 reg = readl(&ccm_anatop->pll_480); in decode_pll() [all …]
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/openbmc/u-boot/arch/arm/mach-imx/mx6/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 10 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/clock.h> 31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk() 36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk() 44 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk() 52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk() 54 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk() 60 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Brian Norris <briannorris@chromium.org> 15 - rockchip,rk3399-dmc 17 devfreq-events: 21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. 26 clock-names: 28 - const: dmc_clk [all …]
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/openbmc/linux/drivers/net/can/mscan/ |
H A D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 38 { .compatible = "fsl,mpc5200-cdm", }, 48 unsigned int freq; in mpc52xx_can_get_clock() local 54 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock() 55 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock() 56 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock() 66 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock() 67 if (!freq) in mpc52xx_can_get_clock() [all …]
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/openbmc/u-boot/arch/arm/mach-at91/armv7/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] 7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 31 return gd->arch.main_clk_rate_hz; in at91_css_to_rate() 33 return gd->arch.plla_rate_hz; in at91_css_to_rate() 39 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument 46 freq /= div; in at91_pll_rate() 47 freq *= mul + 1; in at91_pll_rate() 49 freq = 0; in at91_pll_rate() 52 return freq; in at91_pll_rate() [all …]
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/openbmc/linux/drivers/gpu/drm/msm/ |
H A D | msm_gpu_trace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 22 __entry->pid = pid; 23 __entry->id = id; 24 __entry->ringid = ringid; 25 __entry->nr_bos = nr_bos; 26 __entry->nr_cmds = nr_cmds 29 __entry->id, __entry->pid, __entry->ringid, 30 __entry->nr_bos, __entry->nr_cmds) 44 __entry->pid = pid_nr(submit->pid); 45 __entry->id = submit->ident; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 21 - description: v1 of CPUFREQ HW 23 - enum: 24 - qcom,qcm2290-cpufreq-hw 25 - qcom,sc7180-cpufreq-hw 26 - qcom,sdm845-cpufreq-hw [all …]
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/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/ |
H A D | generic.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc. 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/clock.h> 20 u32 cpu = readl(&mscmir->cpxtype); in get_cpu_rev() 35 return -1; in get_pllfreq() 57 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq() 97 u32 freq = 0; in get_mcu_main_clk() local 109 freq = FIRC_CLK_FREQ; in get_mcu_main_clk() 112 freq = XOSC_CLK_FREQ; in get_mcu_main_clk() [all …]
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/openbmc/u-boot/arch/arm/cpu/armv7/vf610/ |
H A D | generic.c | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/clock.h> 11 #include <asm/mach-imx/sys_proto.h> 29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk() 34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk() 43 u32 freq = 0; in get_mcu_main_clk() local 45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk() 49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk() 56 freq = FASE_CLK_FREQ; in get_mcu_main_clk() [all …]
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/openbmc/qemu/hw/timer/ |
H A D | pxa2xx_timer.c | 12 #include "hw/qdev-properties.h" 45 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ 64 /* [5] is the "Externally supplied clock". Assign if necessary. */ 68 #define TYPE_PXA2XX_TIMER "pxa2xx-timer" 83 int32_t clock; member 85 uint32_t freq; member 95 int32_t clock; member 98 uint32_t freq; member 113 return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4); in pxa2xx_timer_has_tm4() 123 now_vm = s->clock + in pxa2xx_timer_update() [all …]
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/openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll() 28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll() 37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg); in decode_frac_pll() 98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll() 99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll() 100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll() 113 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); in decode_sscg_pll() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_afmt.c | 34 /* Clock N CTS N CTS N CTS */ 51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument 57 n = 128 * freq; in amdgpu_afmt_calc_cts() 58 cts = clock * 1000; in amdgpu_afmt_calc_cts() 67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts() 70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts() 76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts() 78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts() 85 *N, *CTS, freq); in amdgpu_afmt_calc_cts() 88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument [all …]
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/openbmc/linux/drivers/clocksource/ |
H A D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 34 if (priv->big_endian) in ftm_readl() 42 if (priv->big_endian) in ftm_writel() 52 /* select and enable counter clock source */ in ftm_counter_enable() 55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable() 63 /* disable counter clock source */ in ftm_counter_disable() 108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock() 119 * a, the counter source clock is disabled. in ftm_set_next_event() 121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event() 124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | atmel,sama5d2-pdmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 20 const: atmel,sama5d2-pdmic 30 - description: peripheral clock 31 - description: generated clock 33 clock-names: 35 - const: pclk [all …]
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/openbmc/linux/drivers/sh/clk/ |
H A D | core.c | 2 * SuperH clock framework 4 * Copyright (C) 2005 - 2010 Paul Mundt 6 * This clock framework is derived from the OMAP version by: 8 * Copyright (C) 2004 - 2008 Nokia Corporation 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 17 #define pr_fmt(fmt) "clock: " fmt 36 /* clock disable operations are not passed on to hardware during boot */ 46 unsigned long freq; in clk_rate_table_build() local 49 clk->nr_freqs = nr_freqs; in clk_rate_table_build() 55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build() [all …]
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/openbmc/linux/drivers/cpufreq/ |
H A D | armada-8k-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+ 25 { .compatible = "marvell,ap806-cpu-clock" }, 26 { .compatible = "marvell,ap807-cpu-clock" }, 41 unsigned int freq[ARRAY_SIZE(opps_div)]; member 44 /* If the CPUs share the same clock, then they are in the same cluster. */ 62 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus() 77 unsigned int freq; in armada_8k_add_opp() local 83 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp() 84 return -EINVAL; in armada_8k_add_opp() 90 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp() [all …]
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/openbmc/linux/drivers/clk/ti/ |
H A D | fapll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 #include <linux/clk-provider.h> 13 #include "clock.h" 43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 73 void __iomem *freq; member 81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass() 83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass() 91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass() 93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass() 97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass() [all …]
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca5s.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A5 MPCore (V2P-CA5s) 8 * HBI-0225B 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA5s"; 18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; [all …]
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