/openbmc/linux/drivers/watchdog/ |
H A D | shwdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org> 9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com> 12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com> 31 #include <linux/clk.h> 35 #define DRV_NAME "sh-wdt" 39 * values, consult the asm-sh/watchdog.h. Overload this at module load 43 * something quite higher than 100 (or we need a proper high-res timer 46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though 47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely [all …]
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/openbmc/linux/drivers/clk/ |
H A D | clk-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface 13 #include <linux/clk-provider.h> 31 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument 33 return readl_relaxed(csr); in xgene_clk_read() 36 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument 38 writel_relaxed(data, csr); in xgene_clk_write() 63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled() 81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate() 83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate() [all …]
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/openbmc/u-boot/drivers/serial/ |
H A D | atmel_usart.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2004-2006 Atmel Corporation 9 #include <clk.h> 21 #include <asm/arch/clk.h> 37 * Baud Rate = -------------- in atmel_serial_setbrg_internal() 42 writel(USART3_BF(CD, divisor), &usart->brgr); in atmel_serial_setbrg_internal() 51 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY))) in atmel_serial_init_internal() 54 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); in atmel_serial_init_internal() 64 &usart->mr); in atmel_serial_activate() 65 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); in atmel_serial_activate() [all …]
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/openbmc/u-boot/drivers/i2c/ |
H A D | ast_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 9 #include <clk.h> 29 struct clk clk; member 50 scl_low = (divider_ratio >> 1) - 1; in get_clk_reg_val() 51 scl_high = divider_ratio - scl_low - 2; in get_clk_reg_val() 64 writel(~0, &priv->regs->isr); in ast_i2c_clear_interrupts() 72 writel(0, &priv->regs->fcr); in ast_i2c_init_bus() 73 /* Enable Master Mode. Assuming single-master */ in ast_i2c_init_bus() 77 &priv->regs->fcr); in ast_i2c_init_bus() [all …]
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H A D | ast2600_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <clk.h> 108 struct clk clk; member 125 if ((len - 1) == rx_cnt) in ast2600_i2c_read_data() 128 if (send_stop && ((len - 1) == rx_cnt)) in ast2600_i2c_read_data() 131 writel(cmd, &priv->regs->cmd_sts); in ast2600_i2c_read_data() 133 ret = readl_poll_timeout(&priv->regs->isr, isr, in ast2600_i2c_read_data() 137 return -ETIMEDOUT; in ast2600_i2c_read_data() 140 AST2600_I2CC_GET_RX_BUFF(readl(&priv->regs->trx_buff)); in ast2600_i2c_read_data() 142 writel(AST2600_I2CM_PKT_DONE, &priv->regs->isr); in ast2600_i2c_read_data() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 14 Registers(CSR) module represents a set of miscellaneous registers of a 17 use-case is for some other nodes to acquire a reference to the syscon node 18 by phandle, and the other typical use-case is that the operating system 19 should consider all subnodes of the CSR module as separate child devices. 23 pattern: "^syscon@[0-9a-f]+$" [all …]
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/openbmc/qemu/tests/qtest/ |
H A D | npcm7xx_pwm-test.c | 34 #define CSR 0x04 macro 39 /* CLK module related */ 204 ptrdiff_t diff = module - pwm_module_list; in pwm_module_index() 214 ptrdiff_t diff = pwm - pwm_list; in pwm_index() 229 response = qtest_qmp(qts, "{ 'execute': 'qom-get'," in pwm_qom_get() 271 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in mft_qom_set() 319 static uint32_t pwm_selector(uint32_t csr) in pwm_selector() argument 321 switch (csr) { in pwm_selector() 337 static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, in pwm_compute_freq() argument 340 return read_pclk(qts, false) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1)); in pwm_compute_freq() [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/clk.h> 13 #include <linux/dma-mapping.h> 217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 226 readl_relaxed((port)->regs + SPI_##reg) 228 writel_relaxed((value), (port)->regs + SPI_##reg) 230 writew_relaxed((value), (port)->regs + SPI_##reg) 261 struct clk *clk; member [all …]
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/openbmc/linux/drivers/net/wireless/ralink/rt2x00/ |
H A D | rt2x00soc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2004 - 2009 Felix Fietkau <nbd@openwrt.org> 25 kfree(rt2x00dev->rf); in rt2x00soc_free_reg() 26 rt2x00dev->rf = NULL; in rt2x00soc_free_reg() 28 kfree(rt2x00dev->eeprom); in rt2x00soc_free_reg() 29 rt2x00dev->eeprom = NULL; in rt2x00soc_free_reg() 31 iounmap(rt2x00dev->csr.base); in rt2x00soc_free_reg() 36 struct platform_device *pdev = to_platform_device(rt2x00dev->dev); in rt2x00soc_alloc_reg() 41 return -ENODEV; in rt2x00soc_alloc_reg() [all …]
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/openbmc/linux/drivers/dma/ |
H A D | xgene-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Applied Micro X-Gene SoC DMA engine Driver 13 #include <linux/clk.h> 15 #include <linux/dma-mapping.h> 27 /* X-Gene DMA ring csr registers and bit definations */ 44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) 46 ((m) &= (~BIT(31 - (v)))) 77 /* X-Gene DMA device csr registers and bit definitions */ 106 /* X-Gene SoC EFUSE csr register and bit defination */ 110 /* X-Gene DMA Descriptor format */ [all …]
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H A D | fsl-edma-common.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc 6 #include <linux/clk.h> 10 #include <linux/dma-mapping.h> 14 #include "fsl-edma-common.h" 48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler() 50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler() 52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler() 56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler() 57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler() [all …]
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H A D | tegra20-apb-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 9 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 40 /* CSR register */ 103 * on-flight burst and update DMA status register. 132 u32 csr; member 144 * sub-transfer as per requester details and hw support. 201 /* Channel-slave specific configuration */ 213 struct clk *dma_clk; [all …]
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/openbmc/linux/drivers/iio/adc/ |
H A D | stm32-adc-core.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 8 * Inspired from: fsl-imx25-tsadc 13 #include <linux/clk.h> 29 #include "stm32-adc-core.h" 45 * struct stm32_adc_common_regs - stm32 common registers 46 * @csr: common status register offset 48 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n 49 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n 54 u32 csr; member [all …]
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/openbmc/linux/drivers/net/ethernet/qualcomm/emac/ |
H A D | emac.c | 1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 18 #include "emac-mac.h" 19 #include "emac-phy.h" 20 #include "emac-sgmii.h" 84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked() 90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked() 100 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx() 101 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx() 109 irq->mask |= rx_q->intr; in emac_napi_rtx() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 15 groups of four data lanes of LVDS data streams. A phase-locked 24 by Control and Status Registers(CSR) module in the SoC. The CSR 30 - fsl,imx8qm-lvds-phy 31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll 33 "#phy-cells": [all …]
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H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Guido Günther <agx@sigxcpu.org> 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 18 in either MIPI-DSI PHY mode or LVDS PHY mode. 23 - fsl,imx8mq-mipi-dphy 24 - fsl,imx8qxp-mipi-dphy [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module. 16 The CSR module, as a system controller, contains the LDB's configuration 41 - fsl,imx8qm-ldb 42 - fsl,imx8qxp-ldb 44 "#address-cells": [all …]
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/openbmc/linux/drivers/pci/controller/ |
H A D | pci-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * APM X-Gene PCIe Driver 9 #include <linux/clk.h> 19 #include <linux/pci-acpi.h> 20 #include <linux/pci-ecam.h> 64 struct clk *clk; member 74 return readl(port->csr_base + reg); in xgene_pcie_readl() 79 writel(val, port->csr_base + reg); in xgene_pcie_writel() 92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port() 94 cfg = bus->sysdata; in pcie_bus_to_port() [all …]
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-pllv4.c | 1 // SPDX-License-Identifier: GPL-2.0+ 11 #include <linux/clk-provider.h> 17 #include "clk.h" 62 u32 csr; in clk_pllv4_wait_lock() local 64 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock() 65 csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US); in clk_pllv4_wait_lock() 72 if (readl_relaxed(pll->base) & PLL_EN) in clk_pllv4_is_prepared() 85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate() 89 mfn = readl_relaxed(pll->base + pll->num_offset); in clk_pllv4_recalc_rate() 90 mfd = readl_relaxed(pll->base + pll->denom_offset); in clk_pllv4_recalc_rate() [all …]
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/openbmc/u-boot/include/ |
H A D | stm32_rcc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 78 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ 79 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ 80 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ 82 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ 83 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ 86 u32 csr; /* RCC clock control & status */ member
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/openbmc/linux/Documentation/devicetree/bindings/bus/ |
H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, 26 Status Registers (CSR) module, are accessed through the bus. 35 - $ref: simple-pm-bus.yaml# 37 # We need a select here so we don't match all nodes with 'simple-pm-bus'. 43 - fsl,imx8qxp-display-pixel-link-msi-bus [all …]
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/openbmc/linux/drivers/i2c/busses/ |
H A D | i2c-octeon-core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 #include <linux/clk.h> 7 #include <linux/i2c-smbus.h> 40 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */ 41 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */ 97 #define SW_TWSI(x) (x->roff.sw_twsi) 98 #define TWSI_INT(x) (x->roff.twsi_int) 99 #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) 105 struct clk *clk; member 132 * octeon_i2c_reg_write - write an I2C core register [all …]
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/openbmc/linux/drivers/mmc/host/ |
H A D | wbsd.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * linux/drivers/mmc/host/wbsd.c - Winbond W83L51xD SD/MMC driver 5 * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved. 12 * - FIFO size field in FSR is always zero. 14 * - FIFO interrupts tend not to work as they should. Interrupts are 17 * - On APIC systems the FIFO empty interrupt is sometimes lost. 26 #include <linux/dma-mapping.h> 86 BUG_ON(host->config == 0); in wbsd_unlock_config() 88 outb(host->unlock_code, host->config); in wbsd_unlock_config() 89 outb(host->unlock_code, host->config); in wbsd_unlock_config() [all …]
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/openbmc/u-boot/drivers/spi/ |
H A D | atmel_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <clk.h> 15 #include <asm/arch/clk.h> 72 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; in spi_setup_slave() 90 as->regs = regs; in spi_setup_slave() 91 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS in spi_setup_slave() 94 as->mr |= ATMEL_SPI_MR_WDRBT; in spi_setup_slave() 96 spi_writel(as, CSR(cs), csrx); in spi_setup_slave() 98 return &as->slave; in spi_setup_slave() 119 spi_writel(as, MR, as->mr); in spi_claim_bus() [all …]
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/openbmc/linux/drivers/tty/serial/ |
H A D | sccnxp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 #include <linux/clk.h> 24 #include <linux/platform_data/serial-sccnxp.h> 27 #define SCCNXP_NAME "uart-sccnxp" 93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 225 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_read() 228 ret = readb(port->membase + (reg << port->regshift)); in sccnxp_read() 230 ndelay(s->chip->trwd); in sccnxp_read() 237 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_write() [all …]
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