1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2ad83665bSJan Glauber #include <linux/atomic.h>
3ad83665bSJan Glauber #include <linux/clk.h>
4ad83665bSJan Glauber #include <linux/delay.h>
5ad83665bSJan Glauber #include <linux/device.h>
6ad83665bSJan Glauber #include <linux/i2c.h>
71e586671SJan Glauber #include <linux/i2c-smbus.h>
8ad83665bSJan Glauber #include <linux/io.h>
9ad83665bSJan Glauber #include <linux/kernel.h>
10ad83665bSJan Glauber
11ad83665bSJan Glauber /* Controller command patterns */
12ad83665bSJan Glauber #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
13ad83665bSJan Glauber #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
14ad83665bSJan Glauber #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
15ad83665bSJan Glauber #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
16ad83665bSJan Glauber #define SW_TWSI_SIZE_SHIFT 52
17ad83665bSJan Glauber #define SW_TWSI_ADDR_SHIFT 40
18ad83665bSJan Glauber #define SW_TWSI_IA_SHIFT 32 /* Internal address */
19ad83665bSJan Glauber
20ad83665bSJan Glauber /* Controller opcode word (bits 60:57) */
21ad83665bSJan Glauber #define SW_TWSI_OP_SHIFT 57
22ad83665bSJan Glauber #define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
23ad83665bSJan Glauber #define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
24ad83665bSJan Glauber #define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
25ad83665bSJan Glauber #define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
26ad83665bSJan Glauber #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
27ad83665bSJan Glauber #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
28ad83665bSJan Glauber
29ad83665bSJan Glauber /* Controller extended opcode word (bits 34:32) */
30ad83665bSJan Glauber #define SW_TWSI_EOP_SHIFT 32
31ad83665bSJan Glauber #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
32ad83665bSJan Glauber #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
33ad83665bSJan Glauber #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
34ad83665bSJan Glauber #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
35ad83665bSJan Glauber #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
36ad83665bSJan Glauber
37ad83665bSJan Glauber /* Controller command and status bits */
38ad83665bSJan Glauber #define TWSI_CTL_CE 0x80 /* High level controller enable */
39ad83665bSJan Glauber #define TWSI_CTL_ENAB 0x40 /* Bus enable */
40ad83665bSJan Glauber #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
41ad83665bSJan Glauber #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
42ad83665bSJan Glauber #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
43ad83665bSJan Glauber #define TWSI_CTL_AAK 0x04 /* Assert ACK */
44ad83665bSJan Glauber
45ad83665bSJan Glauber /* Status values */
467c424679SJan Glauber #define STAT_BUS_ERROR 0x00
47ad83665bSJan Glauber #define STAT_START 0x08
48ad83665bSJan Glauber #define STAT_REP_START 0x10
49ad83665bSJan Glauber #define STAT_TXADDR_ACK 0x18
50ad83665bSJan Glauber #define STAT_TXADDR_NAK 0x20
51ad83665bSJan Glauber #define STAT_TXDATA_ACK 0x28
52ad83665bSJan Glauber #define STAT_TXDATA_NAK 0x30
53ad83665bSJan Glauber #define STAT_LOST_ARB_38 0x38
54ad83665bSJan Glauber #define STAT_RXADDR_ACK 0x40
55ad83665bSJan Glauber #define STAT_RXADDR_NAK 0x48
56ad83665bSJan Glauber #define STAT_RXDATA_ACK 0x50
57ad83665bSJan Glauber #define STAT_RXDATA_NAK 0x58
58ad83665bSJan Glauber #define STAT_SLAVE_60 0x60
59ad83665bSJan Glauber #define STAT_LOST_ARB_68 0x68
60ad83665bSJan Glauber #define STAT_SLAVE_70 0x70
61ad83665bSJan Glauber #define STAT_LOST_ARB_78 0x78
62ad83665bSJan Glauber #define STAT_SLAVE_80 0x80
63ad83665bSJan Glauber #define STAT_SLAVE_88 0x88
64ad83665bSJan Glauber #define STAT_GENDATA_ACK 0x90
65ad83665bSJan Glauber #define STAT_GENDATA_NAK 0x98
66ad83665bSJan Glauber #define STAT_SLAVE_A0 0xA0
67ad83665bSJan Glauber #define STAT_SLAVE_A8 0xA8
68ad83665bSJan Glauber #define STAT_LOST_ARB_B0 0xB0
69ad83665bSJan Glauber #define STAT_SLAVE_LOST 0xB8
70ad83665bSJan Glauber #define STAT_SLAVE_NAK 0xC0
71ad83665bSJan Glauber #define STAT_SLAVE_ACK 0xC8
72ad83665bSJan Glauber #define STAT_AD2W_ACK 0xD0
73ad83665bSJan Glauber #define STAT_AD2W_NAK 0xD8
74ad83665bSJan Glauber #define STAT_IDLE 0xF8
75ad83665bSJan Glauber
76ad83665bSJan Glauber /* TWSI_INT values */
77ad83665bSJan Glauber #define TWSI_INT_ST_INT BIT_ULL(0)
78ad83665bSJan Glauber #define TWSI_INT_TS_INT BIT_ULL(1)
79ad83665bSJan Glauber #define TWSI_INT_CORE_INT BIT_ULL(2)
80ad83665bSJan Glauber #define TWSI_INT_ST_EN BIT_ULL(4)
81ad83665bSJan Glauber #define TWSI_INT_TS_EN BIT_ULL(5)
82ad83665bSJan Glauber #define TWSI_INT_CORE_EN BIT_ULL(6)
83ad83665bSJan Glauber #define TWSI_INT_SDA_OVR BIT_ULL(8)
84ad83665bSJan Glauber #define TWSI_INT_SCL_OVR BIT_ULL(9)
85ad83665bSJan Glauber #define TWSI_INT_SDA BIT_ULL(10)
86ad83665bSJan Glauber #define TWSI_INT_SCL BIT_ULL(11)
87ad83665bSJan Glauber
88ad83665bSJan Glauber #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
89ad83665bSJan Glauber
9097d97004SJan Glauber /* Register offsets */
9197d97004SJan Glauber struct octeon_i2c_reg_offset {
9297d97004SJan Glauber unsigned int sw_twsi;
9397d97004SJan Glauber unsigned int twsi_int;
9497d97004SJan Glauber unsigned int sw_twsi_ext;
9597d97004SJan Glauber };
9697d97004SJan Glauber
9797d97004SJan Glauber #define SW_TWSI(x) (x->roff.sw_twsi)
9897d97004SJan Glauber #define TWSI_INT(x) (x->roff.twsi_int)
9997d97004SJan Glauber #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext)
10097d97004SJan Glauber
101ad83665bSJan Glauber struct octeon_i2c {
102ad83665bSJan Glauber wait_queue_head_t queue;
103ad83665bSJan Glauber struct i2c_adapter adap;
10497d97004SJan Glauber struct octeon_i2c_reg_offset roff;
10522d40209SJan Glauber struct clk *clk;
106ad83665bSJan Glauber int irq;
107ad83665bSJan Glauber int hlc_irq; /* For cn7890 only */
108ad83665bSJan Glauber u32 twsi_freq;
109ad83665bSJan Glauber int sys_freq;
110ad83665bSJan Glauber void __iomem *twsi_base;
111ad83665bSJan Glauber struct device *dev;
112ad83665bSJan Glauber bool hlc_enabled;
113ad83665bSJan Glauber bool broken_irq_mode;
114ad83665bSJan Glauber bool broken_irq_check;
115ad83665bSJan Glauber void (*int_enable)(struct octeon_i2c *);
116ad83665bSJan Glauber void (*int_disable)(struct octeon_i2c *);
117ad83665bSJan Glauber void (*hlc_int_enable)(struct octeon_i2c *);
118ad83665bSJan Glauber void (*hlc_int_disable)(struct octeon_i2c *);
119ad83665bSJan Glauber atomic_t int_enable_cnt;
120ad83665bSJan Glauber atomic_t hlc_int_enable_cnt;
1211e586671SJan Glauber struct i2c_smbus_alert_setup alert_data;
1221e586671SJan Glauber struct i2c_client *ara;
123ad83665bSJan Glauber };
124ad83665bSJan Glauber
octeon_i2c_writeq_flush(u64 val,void __iomem * addr)125ad83665bSJan Glauber static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
126ad83665bSJan Glauber {
127ad83665bSJan Glauber __raw_writeq(val, addr);
128ad83665bSJan Glauber __raw_readq(addr); /* wait for write to land */
129ad83665bSJan Glauber }
130ad83665bSJan Glauber
131ad83665bSJan Glauber /**
132ad83665bSJan Glauber * octeon_i2c_reg_write - write an I2C core register
133ad83665bSJan Glauber * @i2c: The struct octeon_i2c
134ad83665bSJan Glauber * @eop_reg: Register selector
135ad83665bSJan Glauber * @data: Value to be written
136ad83665bSJan Glauber *
137ad83665bSJan Glauber * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
138ad83665bSJan Glauber */
octeon_i2c_reg_write(struct octeon_i2c * i2c,u64 eop_reg,u8 data)139ad83665bSJan Glauber static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
140ad83665bSJan Glauber {
141493ff7e2SJan Glauber int tries = 1000;
142ad83665bSJan Glauber u64 tmp;
143ad83665bSJan Glauber
14497d97004SJan Glauber __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
145dfa2ccc3SJan Glauber do {
146dfa2ccc3SJan Glauber tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
147493ff7e2SJan Glauber if (--tries < 0)
148493ff7e2SJan Glauber return;
149dfa2ccc3SJan Glauber } while ((tmp & SW_TWSI_V) != 0);
150ad83665bSJan Glauber }
151ad83665bSJan Glauber
152ad83665bSJan Glauber #define octeon_i2c_ctl_write(i2c, val) \
153ad83665bSJan Glauber octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
154ad83665bSJan Glauber #define octeon_i2c_data_write(i2c, val) \
155ad83665bSJan Glauber octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
156ad83665bSJan Glauber
157ad83665bSJan Glauber /**
158ad83665bSJan Glauber * octeon_i2c_reg_read - read lower bits of an I2C core register
159ad83665bSJan Glauber * @i2c: The struct octeon_i2c
160ad83665bSJan Glauber * @eop_reg: Register selector
161ad83665bSJan Glauber *
162ad83665bSJan Glauber * Returns the data.
163ad83665bSJan Glauber *
164ad83665bSJan Glauber * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
165ad83665bSJan Glauber */
octeon_i2c_reg_read(struct octeon_i2c * i2c,u64 eop_reg,int * error)166493ff7e2SJan Glauber static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
167493ff7e2SJan Glauber int *error)
168ad83665bSJan Glauber {
169493ff7e2SJan Glauber int tries = 1000;
170ad83665bSJan Glauber u64 tmp;
171ad83665bSJan Glauber
17297d97004SJan Glauber __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
173dfa2ccc3SJan Glauber do {
174dfa2ccc3SJan Glauber tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
175493ff7e2SJan Glauber if (--tries < 0) {
176493ff7e2SJan Glauber /* signal that the returned data is invalid */
177493ff7e2SJan Glauber if (error)
178493ff7e2SJan Glauber *error = -EIO;
179493ff7e2SJan Glauber return 0;
180493ff7e2SJan Glauber }
181dfa2ccc3SJan Glauber } while ((tmp & SW_TWSI_V) != 0);
182ad83665bSJan Glauber
183ad83665bSJan Glauber return tmp & 0xFF;
184ad83665bSJan Glauber }
185ad83665bSJan Glauber
186ad83665bSJan Glauber #define octeon_i2c_ctl_read(i2c) \
187493ff7e2SJan Glauber octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
188493ff7e2SJan Glauber #define octeon_i2c_data_read(i2c, error) \
189493ff7e2SJan Glauber octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
190ad83665bSJan Glauber #define octeon_i2c_stat_read(i2c) \
191493ff7e2SJan Glauber octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
192ad83665bSJan Glauber
193ad83665bSJan Glauber /**
194ad83665bSJan Glauber * octeon_i2c_read_int - read the TWSI_INT register
195ad83665bSJan Glauber * @i2c: The struct octeon_i2c
196ad83665bSJan Glauber *
197ad83665bSJan Glauber * Returns the value of the register.
198ad83665bSJan Glauber */
octeon_i2c_read_int(struct octeon_i2c * i2c)199ad83665bSJan Glauber static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
200ad83665bSJan Glauber {
20197d97004SJan Glauber return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));
202ad83665bSJan Glauber }
203ad83665bSJan Glauber
204ad83665bSJan Glauber /**
205ad83665bSJan Glauber * octeon_i2c_write_int - write the TWSI_INT register
206ad83665bSJan Glauber * @i2c: The struct octeon_i2c
207ad83665bSJan Glauber * @data: Value to be written
208ad83665bSJan Glauber */
octeon_i2c_write_int(struct octeon_i2c * i2c,u64 data)209ad83665bSJan Glauber static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
210ad83665bSJan Glauber {
21197d97004SJan Glauber octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
212ad83665bSJan Glauber }
213ad83665bSJan Glauber
214ad83665bSJan Glauber /* Prototypes */
215ad83665bSJan Glauber irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
216ad83665bSJan Glauber int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
217ad83665bSJan Glauber int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
218ad83665bSJan Glauber void octeon_i2c_set_clock(struct octeon_i2c *i2c);
219ad83665bSJan Glauber extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;
220