| /openbmc/linux/drivers/ufs/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
15 This selects the PCI UFS Host Controller Interface. Select this if
23 tristate "DesignWare pci support using a G210 Test Chip"
26 Synopsys Test Chip is a PHY for prototyping purposes.
34 This selects the UFS host controller support. Select this if
45 This selects the Cadence-specific additions to UFSHCD platform driver.
50 tristate "DesignWare platform support using a G210 Test Chip"
53 Synopsys Test Chip is a PHY for prototyping purposes.
64 This selects the QCOM specific additions to UFSHCD platform driver.
[all …]
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
30 This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
41 This selects the Qualcomm Data Mover lite/local on SD Card controller.
52 This selects the STMicroelectronics STM32 SDMMC host controller.
61 This selects the Intel(R) PXA(R) Multimedia card Interface.
71 This selects the generic Secure Digital Host Controller Interface.
94 implements a hardware byte swapper using a 32-bit datum.
108 This selects the PCI Secure Digital Host Controller Interface.
123 disabled, it will steal the MMC cards away - rendering them
134 This selects support for ACPI enumerated SDHCI controllers,
[all …]
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | Kconfig | 8 This selects MultiMediaCard, Secure Digital and Secure
31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
53 This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card
161 you are reading this help text, you most likely have no idea :-)
175 This selects the TI DAVINCI Multimedia card Interface.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ebi2.txt | 4 external memory (such as NAND or other memory-mapped peripherals) whereas
10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
20 The chip selects have the following memory range assignments. This region of
21 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
23 Chip Select Physical address base
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
[all …]
|
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
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| H A D | nuvoton,npcm-fiu.txt | 6 FIU0 and FIUx supports two chip selects,
7 FIU3 support four chip select.
10 FIU0 and FIUx supports two chip selects,
11 FIU1 and FIU3 supports four chip selects.
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
16 - #address-cells : should be 1.
17 - #size-cells : should be 0.
18 - reg : the first contains the register location and length,
20 - reg-names: Should contain the reg names "control" and "memory"
[all …]
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| H A D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
30 GPIOs used as chip selects.
[all …]
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| H A D | renesas,rspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,rspi-sh7757 # SH7757
18 - const: renesas,rspi # Legacy SH
20 - items:
21 - enum:
[all …]
|
| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
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| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
[all …]
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| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-dbg-g-chip-info.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_CHIP_INFO - Identify the chips on a TV card
41 applications must not use it. When you found a chip specific bug, please
42 contact the linux-media mailing list
53 the driver stores information about the selected chip in the ``name``
57 selects the nth bridge 'chip' on the TV card. You can enumerate all
60 zero always selects the bridge chip itself, e. g. the chip connected to
61 the PCI or USB bus. Non-zero numbers identify specific parts of the
62 bridge chip such as an AC97 register block.
65 selects the nth sub-device. This allows you to enumerate over all
[all …]
|
| H A D | vidioc-dbg-g-register.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_DBG_G_REGISTER - VIDIOC_DBG_S_REGISTER - Read or write hardware registers
55 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip
66 selects the nth non-sub-device chip on the TV card. The number zero
67 always selects the host chip, e. g. the chip connected to the PCI or USB
72 selects the nth sub-device.
83 We recommended the v4l2-dbg utility over calling these ioctls directly.
84 It is available from the LinuxTV v4l-dvb repository; see
92 .. flat-table:: struct v4l2_dbg_match
93 :header-rows: 0
[all …]
|
| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | Kconfig | 69 Say "Y" if you want output formatted for use in non-SPL
70 (DCD-style) configuration files.
79 int "DDR chip selects"
83 Select the number of chip selects used in your board design
106 bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
110 bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
114 bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
118 bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
122 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
126 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
[all …]
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | pmbus-core.rst | 9 power-management protocol with a fully defined command language that facilitates
11 protocol is implemented over the industry-standard SMBus serial interface and
12 enables programming, control, and real-time monitoring of compliant power
18 promoted by the PMBus Implementers Forum (PMBus-IF), comprising 30+ adopters
22 commands, and manufacturers can add as many non-standard commands as they like.
23 Also, different PMBUs devices act differently if non-supported commands are
43 PMBus device capabilities auto-detection
46 For generic PMBus devices, code in pmbus.c attempts to auto-detect all supported
47 PMBus commands. Auto-detection is somewhat limited, since there are simply too
50 pages (see the PMBus specification for details on multi-page PMBus devices).
[all …]
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| /openbmc/u-boot/board/xes/xpedite517x/ |
| H A D | xpedite517x.c | 1 // SPDX-License-Identifier: GPL-2.0+
23 * swap flash chip selects to maintain consistent flash numbering/addresses.
30 * Print boot dev and swap flash flash chip selects if booted from 2nd in flash_cs_fixup()
31 * flash. Swapping chip selects presents user with a common memory in flash_cs_fixup()
69 gd->ram_size = dram_size; in dram_init()
|
| /openbmc/u-boot/arch/arm/include/asm/arch-mvebu/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
23 u32 dw_cfg; /* 0x10620 - Direct Write Configuration */
27 * each of the below #defines selects which mpp is
29 * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
30 * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
31 * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
40 #define KWSPI_CS_SHIFT 2 /* chip select shift */
41 #define KWSPI_CS_MASK 0x7 /* chip select mask */
|
| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | mcfqspi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
33 * @num_chipselects: number of chip selects supported by this qspi driver.
34 * @cs_control: platform dependent chip select control.
|
| /openbmc/linux/drivers/gpu/drm/rockchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
28 This selects support for the VOP driver. You should enable it
34 This selects support for the VOP2 driver. The VOP2 hardware is
43 This selects support for Rockchip SoC specific extensions
53 This selects support for Rockchip SoC specific extensions
61 This selects support for Rockchip SoC specific extensions
70 This selects support for Rockchip SoC specific extensions
78 This selects support for Rockchip SoC specific extensions
99 and serial RGB format to panel or connect to a conversion chip.
106 This selects support for Rockchip SoC specific extensions
|
| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-zynq.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
16 - num-cs : Number of chip selects used.
18 chip selects after the decoder.
[all …]
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
18 * more chip selects than the hardware peripherals support, or than are
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
29 * @current_cs: The current chip select set in the mux
35 * @mux: mux_control structure used to provide chip selects for
51 struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller); in spi_mux_select()
54 ret = mux_control_select(priv->mux, spi_get_chipselect(spi, 0)); in spi_mux_select()
58 if (priv->current_cs == spi_get_chipselect(spi, 0)) in spi_mux_select()
[all …]
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| /openbmc/u-boot/board/xes/xpedite537x/ |
| H A D | xpedite537x.c | 1 // SPDX-License-Identifier: GPL-2.0+
25 * Print boot dev and swap flash flash chip selects if booted from 2nd in flash_cs_fixup()
26 * flash. Swapping chip selects presents user with a common memory in flash_cs_fixup()
51 * Remap NOR flash region to caching-inhibited in board_early_init_r()
55 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
|
| /openbmc/u-boot/board/xes/xpedite550x/ |
| H A D | xpedite550x.c | 1 // SPDX-License-Identifier: GPL-2.0+
25 * Print boot dev and swap flash flash chip selects if booted from 2nd in flash_cs_fixup()
26 * flash. Swapping chip selects presents user with a common memory in flash_cs_fixup()
51 * Remap NOR flash region to caching-inhibited in board_early_init_r()
55 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
|
| /openbmc/u-boot/board/xes/xpedite520x/ |
| H A D | xpedite520x.c | 1 // SPDX-License-Identifier: GPL-2.0+
27 * Print boot dev and swap flash flash chip selects if booted from 2nd in flash_cs_fixup()
28 * flash. Swapping chip selects presents user with a common memory in flash_cs_fixup()
51 * Remap NOR flash region to caching-inhibited in board_early_init_r()
55 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
|
| /openbmc/linux/arch/alpha/include/asm/ |
| H A D | core_irongate.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
10 * which provides memory controller and PCI access for NAUTILUS-based
21 * The 21264 supports, and internally recognizes, a 44-bit physical
30 * through the routines given is 32-bit.
38 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
39 igcsr32 stat_cmd; /* 0x04 - status, command */
40 igcsr32 class; /* 0x08 - class code, rev ID */
41 igcsr32 latency; /* 0x0C - header type, PCI latency */
42 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
[all …]
|