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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-ingenic.c682 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
683 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
722 "ssi-ce0-b", "ssi-ce0-f",
933 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
934 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
935 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
936 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
961 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
962 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
963 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
[all …]
H A Dpinctrl-gemini.c612 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
634 /* Serial flash pins CE0, CE1, DI, DO, CK */
655 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
658 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
661 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
1561 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1583 /* Serial flash pins CE0, CE1, DI, DO, CK */
1601 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1607 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dcu1830-neo.dts78 reg = <0>; /* CE0 */
197 groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
H A Dcu1000-neo.dts79 reg = <0>; /* CE0 */
194 groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
/openbmc/linux/Documentation/devicetree/bindings/media/spi/
H A Dsony-cxd2880.txt16 reg = <0>; /* CE0 */
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath11k.yaml105 - description: interrupt event for ring CE0
159 - const: ce0
332 "ce0",
H A Dqcom,ath10k.yaml245 - description: CE0
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c275 debug("%s: CE0\n", __func__); in powerup_cpus()
276 power_partition(CE0); in powerup_cpus()
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-rut1xx.dts52 /* Conflict with NAND CE0 */
H A Dgemini-sl93512r.dts64 /* Conflict with NAND flash CE0 (no problem) */
/openbmc/qemu/hw/arm/
H A Dfby35.c179 "boot directly from CE0 flash device"); in fby35_class_init()
/openbmc/linux/drivers/net/wireless/ath/ath11k/
H A Dce.c12 /* CE0: host->target HTC control and raw streams */
118 /* CE0: host->target HTC control and raw streams */
198 /* CE0: host->target HTC control and raw streams */
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts230 "pin24 [gpio16/spi1-ce0]",
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/
H A Dqunit-1.18.0.css1 …nd-color:#FFF;border-left:10px solid #C6E746;}#qunit-tests .pass{color:#528CE0;background-color:#D…
/openbmc/u-boot/drivers/spi/
H A Daspeed_spi.c121 * CE0 0x20000000 - 0x2fffffff 128MB
126 * covered and CE0 start address and CE2 end addresses are read-only.
357 * Use some address/size under the first flash device CE0
371 * When doing calibration, the SPI clock rate in the CE0 in aspeed_spi_fmc_checksum()
391 * Use some address/size under the first flash device CE0
722 * The start address of the AHB window of CE0 is in aspeed_spi_controller_init()
/openbmc/u-boot/arch/arm/dts/
H A Dsun7i-a20-bananapi.dts250 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-bananapi.dts246 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/openbmc/linux/drivers/net/wireless/ath/ath12k/
H A Dce.c12 /* CE0: host->target HTC control and raw streams */
146 /* CE0: host->target HTC control and raw streams */
H A Dhw.c119 /* CE0: host->target HTC control and raw streams */
246 /* CE0: host->target HTC control and raw streams */
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c242 power_partition(CE0); in powerup_cpus()
/openbmc/linux/drivers/spi/
H A Dspi-aspeed-smc.c496 * Due to an HW issue on the AST2500 SPI controller, the CE0 in aspeed_spi_chip_adjust_window()
604 * CE0 Control Register in aspeed_spi_dirmap_create()
890 * The timing register is shared by all devices. Only update for CE0.
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk104.c494 { 0x15, "CE0", NULL, NVKM_ENGINE_CE, 0 },
527 { 0x01, "CE0" },
H A Dgv100.c324 { 0x01, "CE0" },
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpmc.h294 #define CE0 14 macro
/openbmc/qemu/docs/system/arm/
H A Daspeed.rst125 * ``execute-in-place`` which emulates the boot from the CE0 flash

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