| /openbmc/linux/arch/x86/include/asm/ |
| H A D | agp.h | 12 * mappings with different cacheability attributes for the same
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| H A D | set_memory.h | 15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic-v3.yaml | 112 and cacheability attributes but are connected to a non-coherent
205 cacheability attributes but is connected to a non-coherent
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh4.h | 65 #define PMB_C 3 /* Cacheability */
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| /openbmc/linux/drivers/iommu/ |
| H A D | msm_iommu.h | 16 /* Cacheability attributes of MSM IOMMU mappings */
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| /openbmc/linux/arch/sparc/include/asm/ |
| H A D | swift.h | 21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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| /openbmc/u-boot/arch/arm/mach-uniphier/arm32/ |
| H A D | lowlevel_init.S | 58 orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_ppc970.S | 41 li r3,0x1200 /* enable i-fetch cacheability */
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| /openbmc/linux/include/linux/ |
| H A D | io-pgtable.h | 86 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
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| /openbmc/qemu/target/arm/ |
| H A D | ptw.c | 1779 * Note that QEMU ignores shareability and cacheability attributes, in get_phys_addr_lpae()
3027 * Combine either inner or outer cacheability attributes for normal
3053 * Combine the memory type and cacheability attributes of
3073 /* Combine memory type and cacheability attributes */ in combined_attrs_nofwb()
3089 /* Outer/inner cacheability combine independently */ in combined_attrs_nofwb()
3099 * Given the 4 bits specifying the outer or inner cacheability in force_cacheattr_nibble_wb()
3117 * Combine the memory type and cacheability attributes of
3161 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
3194 /* Combine memory type and cacheability attributes */ in combine_cacheattrs()
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| /openbmc/qemu/target/sh4/ |
| H A D | cpu.h | 117 uint8_t c:1; /* cacheability */
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 180 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | io.h | 340 * Function Memory type Cacheability Cache hint
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| /openbmc/linux/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3.h | 94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gtt.h | 107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
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| H A D | intel_gtt.c | 574 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
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| H A D | intel_mocs.c | 146 * Thus it is expected to allow LLC cacheability to enable coherent
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig | 488 that indicate the cacheability, idempotency, and ordering
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | device-io.rst | 439 | API | Memory region type and cacheability |
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 173 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /openbmc/qemu/hw/intc/ |
| H A D | armv7m_nvic.c | 1947 * only affect cacheability, and we don't implement caching. in nvic_writel()
1959 * only affect cacheability, and we don't implement caching. in nvic_writel()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-gic-v3-its.c | 3131 * remove the cacheability attributes as in its_cpu_init_lpis()
3157 * cacheability attributes as well. in its_cpu_init_lpis()
5148 * remove the cacheability attributes as in its_probe_one()
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| /openbmc/linux/include/uapi/drm/ |
| H A D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /openbmc/linux/tools/include/uapi/drm/ |
| H A D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /openbmc/linux/arch/mips/ |
| H A D | Kconfig | 1066 # MIPS allows mixing "slightly different" Cacheability and Coherency
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