1c1737f2bSArnaldo Carvalho de Melo /* 2c1737f2bSArnaldo Carvalho de Melo * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3c1737f2bSArnaldo Carvalho de Melo * All Rights Reserved. 4c1737f2bSArnaldo Carvalho de Melo * 5c1737f2bSArnaldo Carvalho de Melo * Permission is hereby granted, free of charge, to any person obtaining a 6c1737f2bSArnaldo Carvalho de Melo * copy of this software and associated documentation files (the 7c1737f2bSArnaldo Carvalho de Melo * "Software"), to deal in the Software without restriction, including 8c1737f2bSArnaldo Carvalho de Melo * without limitation the rights to use, copy, modify, merge, publish, 9c1737f2bSArnaldo Carvalho de Melo * distribute, sub license, and/or sell copies of the Software, and to 10c1737f2bSArnaldo Carvalho de Melo * permit persons to whom the Software is furnished to do so, subject to 11c1737f2bSArnaldo Carvalho de Melo * the following conditions: 12c1737f2bSArnaldo Carvalho de Melo * 13c1737f2bSArnaldo Carvalho de Melo * The above copyright notice and this permission notice (including the 14c1737f2bSArnaldo Carvalho de Melo * next paragraph) shall be included in all copies or substantial portions 15c1737f2bSArnaldo Carvalho de Melo * of the Software. 16c1737f2bSArnaldo Carvalho de Melo * 17c1737f2bSArnaldo Carvalho de Melo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18c1737f2bSArnaldo Carvalho de Melo * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19c1737f2bSArnaldo Carvalho de Melo * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20c1737f2bSArnaldo Carvalho de Melo * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21c1737f2bSArnaldo Carvalho de Melo * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22c1737f2bSArnaldo Carvalho de Melo * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23c1737f2bSArnaldo Carvalho de Melo * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24c1737f2bSArnaldo Carvalho de Melo * 25c1737f2bSArnaldo Carvalho de Melo */ 26c1737f2bSArnaldo Carvalho de Melo 27c1737f2bSArnaldo Carvalho de Melo #ifndef _UAPI_I915_DRM_H_ 28c1737f2bSArnaldo Carvalho de Melo #define _UAPI_I915_DRM_H_ 29c1737f2bSArnaldo Carvalho de Melo 30c1737f2bSArnaldo Carvalho de Melo #include "drm.h" 31c1737f2bSArnaldo Carvalho de Melo 32c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 33c1737f2bSArnaldo Carvalho de Melo extern "C" { 34c1737f2bSArnaldo Carvalho de Melo #endif 35c1737f2bSArnaldo Carvalho de Melo 36c1737f2bSArnaldo Carvalho de Melo /* Please note that modifications to all structs defined here are 37c1737f2bSArnaldo Carvalho de Melo * subject to backwards-compatibility constraints. 38c1737f2bSArnaldo Carvalho de Melo */ 39c1737f2bSArnaldo Carvalho de Melo 40c1737f2bSArnaldo Carvalho de Melo /** 41c1737f2bSArnaldo Carvalho de Melo * DOC: uevents generated by i915 on it's device node 42c1737f2bSArnaldo Carvalho de Melo * 43c1737f2bSArnaldo Carvalho de Melo * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44c1737f2bSArnaldo Carvalho de Melo * event from the gpu l3 cache. Additional information supplied is ROW, 45c1737f2bSArnaldo Carvalho de Melo * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46c1737f2bSArnaldo Carvalho de Melo * track of these events and if a specific cache-line seems to have a 47c1737f2bSArnaldo Carvalho de Melo * persistent error remap it with the l3 remapping tool supplied in 48c1737f2bSArnaldo Carvalho de Melo * intel-gpu-tools. The value supplied with the event is always 1. 49c1737f2bSArnaldo Carvalho de Melo * 50c1737f2bSArnaldo Carvalho de Melo * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51c1737f2bSArnaldo Carvalho de Melo * hangcheck. The error detection event is a good indicator of when things 52c1737f2bSArnaldo Carvalho de Melo * began to go badly. The value supplied with the event is a 1 upon error 53c1737f2bSArnaldo Carvalho de Melo * detection, and a 0 upon reset completion, signifying no more error 54c1737f2bSArnaldo Carvalho de Melo * exists. NOTE: Disabling hangcheck or reset via module parameter will 55c1737f2bSArnaldo Carvalho de Melo * cause the related events to not be seen. 56c1737f2bSArnaldo Carvalho de Melo * 57c1737f2bSArnaldo Carvalho de Melo * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58d01541d0SArnaldo Carvalho de Melo * GPU. The value supplied with the event is always 1. NOTE: Disable 59c1737f2bSArnaldo Carvalho de Melo * reset via module parameter will cause this event to not be seen. 60c1737f2bSArnaldo Carvalho de Melo */ 61c1737f2bSArnaldo Carvalho de Melo #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62c1737f2bSArnaldo Carvalho de Melo #define I915_ERROR_UEVENT "ERROR" 63c1737f2bSArnaldo Carvalho de Melo #define I915_RESET_UEVENT "RESET" 64c1737f2bSArnaldo Carvalho de Melo 654a1cddeaSArnaldo Carvalho de Melo /** 664a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension - Base class for defining a chain of extensions 67e6aff9f8SArnaldo Carvalho de Melo * 68e6aff9f8SArnaldo Carvalho de Melo * Many interfaces need to grow over time. In most cases we can simply 69e6aff9f8SArnaldo Carvalho de Melo * extend the struct and have userspace pass in more data. Another option, 70e6aff9f8SArnaldo Carvalho de Melo * as demonstrated by Vulkan's approach to providing extensions for forward 71e6aff9f8SArnaldo Carvalho de Melo * and backward compatibility, is to use a list of optional structs to 72e6aff9f8SArnaldo Carvalho de Melo * provide those extra details. 73e6aff9f8SArnaldo Carvalho de Melo * 74e6aff9f8SArnaldo Carvalho de Melo * The key advantage to using an extension chain is that it allows us to 75e6aff9f8SArnaldo Carvalho de Melo * redefine the interface more easily than an ever growing struct of 76e6aff9f8SArnaldo Carvalho de Melo * increasing complexity, and for large parts of that interface to be 77e6aff9f8SArnaldo Carvalho de Melo * entirely optional. The downside is more pointer chasing; chasing across 78e6aff9f8SArnaldo Carvalho de Melo * the __user boundary with pointers encapsulated inside u64. 794a1cddeaSArnaldo Carvalho de Melo * 804a1cddeaSArnaldo Carvalho de Melo * Example chaining: 814a1cddeaSArnaldo Carvalho de Melo * 824a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 834a1cddeaSArnaldo Carvalho de Melo * 844a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext3 { 854a1cddeaSArnaldo Carvalho de Melo * .next_extension = 0, // end 864a1cddeaSArnaldo Carvalho de Melo * .name = ..., 874a1cddeaSArnaldo Carvalho de Melo * }; 884a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext2 { 894a1cddeaSArnaldo Carvalho de Melo * .next_extension = (uintptr_t)&ext3, 904a1cddeaSArnaldo Carvalho de Melo * .name = ..., 914a1cddeaSArnaldo Carvalho de Melo * }; 924a1cddeaSArnaldo Carvalho de Melo * struct i915_user_extension ext1 { 934a1cddeaSArnaldo Carvalho de Melo * .next_extension = (uintptr_t)&ext2, 944a1cddeaSArnaldo Carvalho de Melo * .name = ..., 954a1cddeaSArnaldo Carvalho de Melo * }; 964a1cddeaSArnaldo Carvalho de Melo * 974a1cddeaSArnaldo Carvalho de Melo * Typically the struct i915_user_extension would be embedded in some uAPI 984a1cddeaSArnaldo Carvalho de Melo * struct, and in this case we would feed it the head of the chain(i.e ext1), 994a1cddeaSArnaldo Carvalho de Melo * which would then apply all of the above extensions. 1004a1cddeaSArnaldo Carvalho de Melo * 101e6aff9f8SArnaldo Carvalho de Melo */ 102e6aff9f8SArnaldo Carvalho de Melo struct i915_user_extension { 1034a1cddeaSArnaldo Carvalho de Melo /** 1044a1cddeaSArnaldo Carvalho de Melo * @next_extension: 1054a1cddeaSArnaldo Carvalho de Melo * 1064a1cddeaSArnaldo Carvalho de Melo * Pointer to the next struct i915_user_extension, or zero if the end. 1074a1cddeaSArnaldo Carvalho de Melo */ 108e6aff9f8SArnaldo Carvalho de Melo __u64 next_extension; 1094a1cddeaSArnaldo Carvalho de Melo /** 1104a1cddeaSArnaldo Carvalho de Melo * @name: Name of the extension. 1114a1cddeaSArnaldo Carvalho de Melo * 1124a1cddeaSArnaldo Carvalho de Melo * Note that the name here is just some integer. 1134a1cddeaSArnaldo Carvalho de Melo * 1144a1cddeaSArnaldo Carvalho de Melo * Also note that the name space for this is not global for the whole 1154a1cddeaSArnaldo Carvalho de Melo * driver, but rather its scope/meaning is limited to the specific piece 1164a1cddeaSArnaldo Carvalho de Melo * of uAPI which has embedded the struct i915_user_extension. 1174a1cddeaSArnaldo Carvalho de Melo */ 118e6aff9f8SArnaldo Carvalho de Melo __u32 name; 1194a1cddeaSArnaldo Carvalho de Melo /** 1204a1cddeaSArnaldo Carvalho de Melo * @flags: MBZ 1214a1cddeaSArnaldo Carvalho de Melo * 1224a1cddeaSArnaldo Carvalho de Melo * All undefined bits must be zero. 1234a1cddeaSArnaldo Carvalho de Melo */ 1244a1cddeaSArnaldo Carvalho de Melo __u32 flags; 1254a1cddeaSArnaldo Carvalho de Melo /** 1264a1cddeaSArnaldo Carvalho de Melo * @rsvd: MBZ 1274a1cddeaSArnaldo Carvalho de Melo * 1284a1cddeaSArnaldo Carvalho de Melo * Reserved for future use; must be zero. 1294a1cddeaSArnaldo Carvalho de Melo */ 1304a1cddeaSArnaldo Carvalho de Melo __u32 rsvd[4]; 131e6aff9f8SArnaldo Carvalho de Melo }; 132e6aff9f8SArnaldo Carvalho de Melo 133e6aff9f8SArnaldo Carvalho de Melo /* 134c1737f2bSArnaldo Carvalho de Melo * MOCS indexes used for GPU surfaces, defining the cacheability of the 135c1737f2bSArnaldo Carvalho de Melo * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 136c1737f2bSArnaldo Carvalho de Melo */ 137c1737f2bSArnaldo Carvalho de Melo enum i915_mocs_table_index { 138c1737f2bSArnaldo Carvalho de Melo /* 139c1737f2bSArnaldo Carvalho de Melo * Not cached anywhere, coherency between CPU and GPU accesses is 140c1737f2bSArnaldo Carvalho de Melo * guaranteed. 141c1737f2bSArnaldo Carvalho de Melo */ 142c1737f2bSArnaldo Carvalho de Melo I915_MOCS_UNCACHED, 143c1737f2bSArnaldo Carvalho de Melo /* 144c1737f2bSArnaldo Carvalho de Melo * Cacheability and coherency controlled by the kernel automatically 145c1737f2bSArnaldo Carvalho de Melo * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 146c1737f2bSArnaldo Carvalho de Melo * usage of the surface (used for display scanout or not). 147c1737f2bSArnaldo Carvalho de Melo */ 148c1737f2bSArnaldo Carvalho de Melo I915_MOCS_PTE, 149c1737f2bSArnaldo Carvalho de Melo /* 150c1737f2bSArnaldo Carvalho de Melo * Cached in all GPU caches available on the platform. 151c1737f2bSArnaldo Carvalho de Melo * Coherency between CPU and GPU accesses to the surface is not 152c1737f2bSArnaldo Carvalho de Melo * guaranteed without extra synchronization. 153c1737f2bSArnaldo Carvalho de Melo */ 154c1737f2bSArnaldo Carvalho de Melo I915_MOCS_CACHED, 155c1737f2bSArnaldo Carvalho de Melo }; 156c1737f2bSArnaldo Carvalho de Melo 1570fdd435cSArnaldo Carvalho de Melo /** 1580fdd435cSArnaldo Carvalho de Melo * enum drm_i915_gem_engine_class - uapi engine type enumeration 1590fdd435cSArnaldo Carvalho de Melo * 160f091f1d6SIngo Molnar * Different engines serve different roles, and there may be more than one 1610fdd435cSArnaldo Carvalho de Melo * engine serving each role. This enum provides a classification of the role 1620fdd435cSArnaldo Carvalho de Melo * of the engine, which may be used when requesting operations to be performed 1630fdd435cSArnaldo Carvalho de Melo * on a certain subset of engines, or for providing information about that 1640fdd435cSArnaldo Carvalho de Melo * group. 165f091f1d6SIngo Molnar */ 166f091f1d6SIngo Molnar enum drm_i915_gem_engine_class { 1670fdd435cSArnaldo Carvalho de Melo /** 1680fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_RENDER: 1690fdd435cSArnaldo Carvalho de Melo * 1700fdd435cSArnaldo Carvalho de Melo * Render engines support instructions used for 3D, Compute (GPGPU), 1710fdd435cSArnaldo Carvalho de Melo * and programmable media workloads. These instructions fetch data and 1720fdd435cSArnaldo Carvalho de Melo * dispatch individual work items to threads that operate in parallel. 1730fdd435cSArnaldo Carvalho de Melo * The threads run small programs (called "kernels" or "shaders") on 1740fdd435cSArnaldo Carvalho de Melo * the GPU's execution units (EUs). 1750fdd435cSArnaldo Carvalho de Melo */ 176f091f1d6SIngo Molnar I915_ENGINE_CLASS_RENDER = 0, 1770fdd435cSArnaldo Carvalho de Melo 1780fdd435cSArnaldo Carvalho de Melo /** 1790fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_COPY: 1800fdd435cSArnaldo Carvalho de Melo * 1810fdd435cSArnaldo Carvalho de Melo * Copy engines (also referred to as "blitters") support instructions 1820fdd435cSArnaldo Carvalho de Melo * that move blocks of data from one location in memory to another, 1830fdd435cSArnaldo Carvalho de Melo * or that fill a specified location of memory with fixed data. 1840fdd435cSArnaldo Carvalho de Melo * Copy engines can perform pre-defined logical or bitwise operations 1850fdd435cSArnaldo Carvalho de Melo * on the source, destination, or pattern data. 1860fdd435cSArnaldo Carvalho de Melo */ 187f091f1d6SIngo Molnar I915_ENGINE_CLASS_COPY = 1, 1880fdd435cSArnaldo Carvalho de Melo 1890fdd435cSArnaldo Carvalho de Melo /** 1900fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_VIDEO: 1910fdd435cSArnaldo Carvalho de Melo * 1920fdd435cSArnaldo Carvalho de Melo * Video engines (also referred to as "bit stream decode" (BSD) or 1930fdd435cSArnaldo Carvalho de Melo * "vdbox") support instructions that perform fixed-function media 1940fdd435cSArnaldo Carvalho de Melo * decode and encode. 1950fdd435cSArnaldo Carvalho de Melo */ 196f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO = 2, 1970fdd435cSArnaldo Carvalho de Melo 1980fdd435cSArnaldo Carvalho de Melo /** 1990fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_VIDEO_ENHANCE: 2000fdd435cSArnaldo Carvalho de Melo * 2010fdd435cSArnaldo Carvalho de Melo * Video enhancement engines (also referred to as "vebox") support 2020fdd435cSArnaldo Carvalho de Melo * instructions related to image enhancement. 2030fdd435cSArnaldo Carvalho de Melo */ 204f091f1d6SIngo Molnar I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 205f091f1d6SIngo Molnar 2060fdd435cSArnaldo Carvalho de Melo /** 2070fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_COMPUTE: 2080fdd435cSArnaldo Carvalho de Melo * 2090fdd435cSArnaldo Carvalho de Melo * Compute engines support a subset of the instructions available 2100fdd435cSArnaldo Carvalho de Melo * on render engines: compute engines support Compute (GPGPU) and 2110fdd435cSArnaldo Carvalho de Melo * programmable media workloads, but do not support the 3D pipeline. 2120fdd435cSArnaldo Carvalho de Melo */ 2130fdd435cSArnaldo Carvalho de Melo I915_ENGINE_CLASS_COMPUTE = 4, 214e6aff9f8SArnaldo Carvalho de Melo 2150fdd435cSArnaldo Carvalho de Melo /* Values in this enum should be kept compact. */ 2160fdd435cSArnaldo Carvalho de Melo 2170fdd435cSArnaldo Carvalho de Melo /** 2180fdd435cSArnaldo Carvalho de Melo * @I915_ENGINE_CLASS_INVALID: 2190fdd435cSArnaldo Carvalho de Melo * 2200fdd435cSArnaldo Carvalho de Melo * Placeholder value to represent an invalid engine class assignment. 2210fdd435cSArnaldo Carvalho de Melo */ 222f091f1d6SIngo Molnar I915_ENGINE_CLASS_INVALID = -1 223f091f1d6SIngo Molnar }; 224f091f1d6SIngo Molnar 2250fdd435cSArnaldo Carvalho de Melo /** 2260fdd435cSArnaldo Carvalho de Melo * struct i915_engine_class_instance - Engine class/instance identifier 2270fdd435cSArnaldo Carvalho de Melo * 228e6aff9f8SArnaldo Carvalho de Melo * There may be more than one engine fulfilling any role within the system. 229e6aff9f8SArnaldo Carvalho de Melo * Each engine of a class is given a unique instance number and therefore 230e6aff9f8SArnaldo Carvalho de Melo * any engine can be specified by its class:instance tuplet. APIs that allow 231e6aff9f8SArnaldo Carvalho de Melo * access to any engine in the system will use struct i915_engine_class_instance 232e6aff9f8SArnaldo Carvalho de Melo * for this identification. 233e6aff9f8SArnaldo Carvalho de Melo */ 234e6aff9f8SArnaldo Carvalho de Melo struct i915_engine_class_instance { 2350fdd435cSArnaldo Carvalho de Melo /** 2360fdd435cSArnaldo Carvalho de Melo * @engine_class: 2370fdd435cSArnaldo Carvalho de Melo * 2380fdd435cSArnaldo Carvalho de Melo * Engine class from enum drm_i915_gem_engine_class 2390fdd435cSArnaldo Carvalho de Melo */ 2400fdd435cSArnaldo Carvalho de Melo __u16 engine_class; 24195dc663aSArnaldo Carvalho de Melo #define I915_ENGINE_CLASS_INVALID_NONE -1 24295dc663aSArnaldo Carvalho de Melo #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 2430fdd435cSArnaldo Carvalho de Melo 2440fdd435cSArnaldo Carvalho de Melo /** 2450fdd435cSArnaldo Carvalho de Melo * @engine_instance: 2460fdd435cSArnaldo Carvalho de Melo * 2470fdd435cSArnaldo Carvalho de Melo * Engine instance. 2480fdd435cSArnaldo Carvalho de Melo */ 2490fdd435cSArnaldo Carvalho de Melo __u16 engine_instance; 250e6aff9f8SArnaldo Carvalho de Melo }; 251e6aff9f8SArnaldo Carvalho de Melo 252f091f1d6SIngo Molnar /** 253f091f1d6SIngo Molnar * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 254f091f1d6SIngo Molnar * 255f091f1d6SIngo Molnar */ 256f091f1d6SIngo Molnar 257f091f1d6SIngo Molnar enum drm_i915_pmu_engine_sample { 258f091f1d6SIngo Molnar I915_SAMPLE_BUSY = 0, 259f091f1d6SIngo Molnar I915_SAMPLE_WAIT = 1, 260f091f1d6SIngo Molnar I915_SAMPLE_SEMA = 2 261f091f1d6SIngo Molnar }; 262f091f1d6SIngo Molnar 263f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_BITS (4) 264f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_MASK (0xf) 265f091f1d6SIngo Molnar #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 266f091f1d6SIngo Molnar #define I915_PMU_CLASS_SHIFT \ 267f091f1d6SIngo Molnar (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 268f091f1d6SIngo Molnar 269f091f1d6SIngo Molnar #define __I915_PMU_ENGINE(class, instance, sample) \ 270f091f1d6SIngo Molnar ((class) << I915_PMU_CLASS_SHIFT | \ 271f091f1d6SIngo Molnar (instance) << I915_PMU_SAMPLE_BITS | \ 272f091f1d6SIngo Molnar (sample)) 273f091f1d6SIngo Molnar 274f091f1d6SIngo Molnar #define I915_PMU_ENGINE_BUSY(class, instance) \ 275f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 276f091f1d6SIngo Molnar 277f091f1d6SIngo Molnar #define I915_PMU_ENGINE_WAIT(class, instance) \ 278f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 279f091f1d6SIngo Molnar 280f091f1d6SIngo Molnar #define I915_PMU_ENGINE_SEMA(class, instance) \ 281f091f1d6SIngo Molnar __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 282f091f1d6SIngo Molnar 283*142256d2SArnaldo Carvalho de Melo /* 284*142256d2SArnaldo Carvalho de Melo * Top 4 bits of every non-engine counter are GT id. 285*142256d2SArnaldo Carvalho de Melo */ 286*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_GT_SHIFT (60) 287*142256d2SArnaldo Carvalho de Melo 288*142256d2SArnaldo Carvalho de Melo #define ___I915_PMU_OTHER(gt, x) \ 289*142256d2SArnaldo Carvalho de Melo (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ 290*142256d2SArnaldo Carvalho de Melo ((__u64)(gt) << __I915_PMU_GT_SHIFT)) 291*142256d2SArnaldo Carvalho de Melo 292*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) 293f091f1d6SIngo Molnar 294f091f1d6SIngo Molnar #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 295f091f1d6SIngo Molnar #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 296f091f1d6SIngo Molnar #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 297f091f1d6SIngo Molnar #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 298c2446944SArnaldo Carvalho de Melo #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 299f091f1d6SIngo Molnar 300c2446944SArnaldo Carvalho de Melo #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY 301f091f1d6SIngo Molnar 302*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) 303*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) 304*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) 305*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) 306*142256d2SArnaldo Carvalho de Melo #define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) 307*142256d2SArnaldo Carvalho de Melo 308c1737f2bSArnaldo Carvalho de Melo /* Each region is a minimum of 16k, and there are at most 255 of them. 309c1737f2bSArnaldo Carvalho de Melo */ 310c1737f2bSArnaldo Carvalho de Melo #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 311c1737f2bSArnaldo Carvalho de Melo * of chars for next/prev indices */ 312c1737f2bSArnaldo Carvalho de Melo #define I915_LOG_MIN_TEX_REGION_SIZE 14 313c1737f2bSArnaldo Carvalho de Melo 314c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_init { 315c1737f2bSArnaldo Carvalho de Melo enum { 316c1737f2bSArnaldo Carvalho de Melo I915_INIT_DMA = 0x01, 317c1737f2bSArnaldo Carvalho de Melo I915_CLEANUP_DMA = 0x02, 318c1737f2bSArnaldo Carvalho de Melo I915_RESUME_DMA = 0x03 319c1737f2bSArnaldo Carvalho de Melo } func; 320c1737f2bSArnaldo Carvalho de Melo unsigned int mmio_offset; 321c1737f2bSArnaldo Carvalho de Melo int sarea_priv_offset; 322c1737f2bSArnaldo Carvalho de Melo unsigned int ring_start; 323c1737f2bSArnaldo Carvalho de Melo unsigned int ring_end; 324c1737f2bSArnaldo Carvalho de Melo unsigned int ring_size; 325c1737f2bSArnaldo Carvalho de Melo unsigned int front_offset; 326c1737f2bSArnaldo Carvalho de Melo unsigned int back_offset; 327c1737f2bSArnaldo Carvalho de Melo unsigned int depth_offset; 328c1737f2bSArnaldo Carvalho de Melo unsigned int w; 329c1737f2bSArnaldo Carvalho de Melo unsigned int h; 330c1737f2bSArnaldo Carvalho de Melo unsigned int pitch; 331c1737f2bSArnaldo Carvalho de Melo unsigned int pitch_bits; 332c1737f2bSArnaldo Carvalho de Melo unsigned int back_pitch; 333c1737f2bSArnaldo Carvalho de Melo unsigned int depth_pitch; 334c1737f2bSArnaldo Carvalho de Melo unsigned int cpp; 335c1737f2bSArnaldo Carvalho de Melo unsigned int chipset; 336c1737f2bSArnaldo Carvalho de Melo } drm_i915_init_t; 337c1737f2bSArnaldo Carvalho de Melo 338c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_sarea { 339c1737f2bSArnaldo Carvalho de Melo struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 340c1737f2bSArnaldo Carvalho de Melo int last_upload; /* last time texture was uploaded */ 341c1737f2bSArnaldo Carvalho de Melo int last_enqueue; /* last time a buffer was enqueued */ 342c1737f2bSArnaldo Carvalho de Melo int last_dispatch; /* age of the most recently dispatched buffer */ 343c1737f2bSArnaldo Carvalho de Melo int ctxOwner; /* last context to upload state */ 344c1737f2bSArnaldo Carvalho de Melo int texAge; 345c1737f2bSArnaldo Carvalho de Melo int pf_enabled; /* is pageflipping allowed? */ 346c1737f2bSArnaldo Carvalho de Melo int pf_active; 347c1737f2bSArnaldo Carvalho de Melo int pf_current_page; /* which buffer is being displayed? */ 348c1737f2bSArnaldo Carvalho de Melo int perf_boxes; /* performance boxes to be displayed */ 349c1737f2bSArnaldo Carvalho de Melo int width, height; /* screen size in pixels */ 350c1737f2bSArnaldo Carvalho de Melo 351c1737f2bSArnaldo Carvalho de Melo drm_handle_t front_handle; 352c1737f2bSArnaldo Carvalho de Melo int front_offset; 353c1737f2bSArnaldo Carvalho de Melo int front_size; 354c1737f2bSArnaldo Carvalho de Melo 355c1737f2bSArnaldo Carvalho de Melo drm_handle_t back_handle; 356c1737f2bSArnaldo Carvalho de Melo int back_offset; 357c1737f2bSArnaldo Carvalho de Melo int back_size; 358c1737f2bSArnaldo Carvalho de Melo 359c1737f2bSArnaldo Carvalho de Melo drm_handle_t depth_handle; 360c1737f2bSArnaldo Carvalho de Melo int depth_offset; 361c1737f2bSArnaldo Carvalho de Melo int depth_size; 362c1737f2bSArnaldo Carvalho de Melo 363c1737f2bSArnaldo Carvalho de Melo drm_handle_t tex_handle; 364c1737f2bSArnaldo Carvalho de Melo int tex_offset; 365c1737f2bSArnaldo Carvalho de Melo int tex_size; 366c1737f2bSArnaldo Carvalho de Melo int log_tex_granularity; 367c1737f2bSArnaldo Carvalho de Melo int pitch; 368c1737f2bSArnaldo Carvalho de Melo int rotation; /* 0, 90, 180 or 270 */ 369c1737f2bSArnaldo Carvalho de Melo int rotated_offset; 370c1737f2bSArnaldo Carvalho de Melo int rotated_size; 371c1737f2bSArnaldo Carvalho de Melo int rotated_pitch; 372c1737f2bSArnaldo Carvalho de Melo int virtualX, virtualY; 373c1737f2bSArnaldo Carvalho de Melo 374c1737f2bSArnaldo Carvalho de Melo unsigned int front_tiled; 375c1737f2bSArnaldo Carvalho de Melo unsigned int back_tiled; 376c1737f2bSArnaldo Carvalho de Melo unsigned int depth_tiled; 377c1737f2bSArnaldo Carvalho de Melo unsigned int rotated_tiled; 378c1737f2bSArnaldo Carvalho de Melo unsigned int rotated2_tiled; 379c1737f2bSArnaldo Carvalho de Melo 380c1737f2bSArnaldo Carvalho de Melo int pipeA_x; 381c1737f2bSArnaldo Carvalho de Melo int pipeA_y; 382c1737f2bSArnaldo Carvalho de Melo int pipeA_w; 383c1737f2bSArnaldo Carvalho de Melo int pipeA_h; 384c1737f2bSArnaldo Carvalho de Melo int pipeB_x; 385c1737f2bSArnaldo Carvalho de Melo int pipeB_y; 386c1737f2bSArnaldo Carvalho de Melo int pipeB_w; 387c1737f2bSArnaldo Carvalho de Melo int pipeB_h; 388c1737f2bSArnaldo Carvalho de Melo 389c1737f2bSArnaldo Carvalho de Melo /* fill out some space for old userspace triple buffer */ 390c1737f2bSArnaldo Carvalho de Melo drm_handle_t unused_handle; 391c1737f2bSArnaldo Carvalho de Melo __u32 unused1, unused2, unused3; 392c1737f2bSArnaldo Carvalho de Melo 393c1737f2bSArnaldo Carvalho de Melo /* buffer object handles for static buffers. May change 394c1737f2bSArnaldo Carvalho de Melo * over the lifetime of the client. 395c1737f2bSArnaldo Carvalho de Melo */ 396c1737f2bSArnaldo Carvalho de Melo __u32 front_bo_handle; 397c1737f2bSArnaldo Carvalho de Melo __u32 back_bo_handle; 398c1737f2bSArnaldo Carvalho de Melo __u32 unused_bo_handle; 399c1737f2bSArnaldo Carvalho de Melo __u32 depth_bo_handle; 400c1737f2bSArnaldo Carvalho de Melo 401c1737f2bSArnaldo Carvalho de Melo } drm_i915_sarea_t; 402c1737f2bSArnaldo Carvalho de Melo 403c1737f2bSArnaldo Carvalho de Melo /* due to userspace building against these headers we need some compat here */ 404c1737f2bSArnaldo Carvalho de Melo #define planeA_x pipeA_x 405c1737f2bSArnaldo Carvalho de Melo #define planeA_y pipeA_y 406c1737f2bSArnaldo Carvalho de Melo #define planeA_w pipeA_w 407c1737f2bSArnaldo Carvalho de Melo #define planeA_h pipeA_h 408c1737f2bSArnaldo Carvalho de Melo #define planeB_x pipeB_x 409c1737f2bSArnaldo Carvalho de Melo #define planeB_y pipeB_y 410c1737f2bSArnaldo Carvalho de Melo #define planeB_w pipeB_w 411c1737f2bSArnaldo Carvalho de Melo #define planeB_h pipeB_h 412c1737f2bSArnaldo Carvalho de Melo 413c1737f2bSArnaldo Carvalho de Melo /* Flags for perf_boxes 414c1737f2bSArnaldo Carvalho de Melo */ 415c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_RING_EMPTY 0x1 416c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_FLIP 0x2 417c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_WAIT 0x4 418c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_TEXTURE_LOAD 0x8 419c1737f2bSArnaldo Carvalho de Melo #define I915_BOX_LOST_CONTEXT 0x10 420c1737f2bSArnaldo Carvalho de Melo 421c1737f2bSArnaldo Carvalho de Melo /* 422c1737f2bSArnaldo Carvalho de Melo * i915 specific ioctls. 423c1737f2bSArnaldo Carvalho de Melo * 424c1737f2bSArnaldo Carvalho de Melo * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 425c1737f2bSArnaldo Carvalho de Melo * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 426c1737f2bSArnaldo Carvalho de Melo * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 427c1737f2bSArnaldo Carvalho de Melo */ 428c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT 0x00 429c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLUSH 0x01 430c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FLIP 0x02 431c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_BATCHBUFFER 0x03 432c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_EMIT 0x04 433c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_IRQ_WAIT 0x05 434c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GETPARAM 0x06 435c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SETPARAM 0x07 436c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_ALLOC 0x08 437c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_FREE 0x09 438c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_INIT_HEAP 0x0a 439c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_CMDBUFFER 0x0b 440c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_DESTROY_HEAP 0x0c 441c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_VBLANK_PIPE 0x0d 442c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_VBLANK_PIPE 0x0e 443c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_SWAP 0x0f 444c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_HWS_ADDR 0x11 445c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_INIT 0x13 446c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER 0x14 447c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PIN 0x15 448c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_UNPIN 0x16 449c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_BUSY 0x17 450c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_THROTTLE 0x18 451c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_ENTERVT 0x19 452c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_LEAVEVT 0x1a 453c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CREATE 0x1b 454c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PREAD 0x1c 455c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_PWRITE 0x1d 456c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP 0x1e 457c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_DOMAIN 0x1f 458c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SW_FINISH 0x20 459c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_TILING 0x21 460c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_TILING 0x22 461c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_APERTURE 0x23 462c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MMAP_GTT 0x24 463c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 464c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_MADVISE 0x26 465c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 466c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_OVERLAY_ATTRS 0x28 467c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2 0x29 468c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 469c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 470c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 471c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_WAIT 0x2c 472c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 473c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 474c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_SET_CACHING 0x2f 475c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_GET_CACHING 0x30 476c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_REG_READ 0x31 477c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GET_RESET_STATS 0x32 478c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_USERPTR 0x33 479c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 480c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 481c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_PERF_OPEN 0x36 482549a3976SIngo Molnar #define DRM_I915_PERF_ADD_CONFIG 0x37 483549a3976SIngo Molnar #define DRM_I915_PERF_REMOVE_CONFIG 0x38 48401f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY 0x39 48595dc663aSArnaldo Carvalho de Melo #define DRM_I915_GEM_VM_CREATE 0x3a 48695dc663aSArnaldo Carvalho de Melo #define DRM_I915_GEM_VM_DESTROY 0x3b 4874a1cddeaSArnaldo Carvalho de Melo #define DRM_I915_GEM_CREATE_EXT 0x3c 488e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes */ 489c1737f2bSArnaldo Carvalho de Melo 490c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 491c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 492c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 493c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 494c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 495c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 496c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 497c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 498c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 499c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 500c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 501c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 502c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 503c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 504c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 505c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 506c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 507c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 508c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 509c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 510c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 511c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 512c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 513c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 514c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 515c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 516c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 517c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 518c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 519c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 5204a1cddeaSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 521c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 522c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 523c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 524c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 525365f9cc1SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 526c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 527c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 528c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 529c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 530c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 531c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 532c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 533c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 534c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 535c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 536c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 537c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 538c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 539e6aff9f8SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 540c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 541c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 542c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 543c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 544c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 545c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 546c1737f2bSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 547549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 548549a3976SIngo Molnar #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 54901f97511SArnaldo Carvalho de Melo #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 55095dc663aSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 55195dc663aSArnaldo Carvalho de Melo #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 552c1737f2bSArnaldo Carvalho de Melo 553c1737f2bSArnaldo Carvalho de Melo /* Allow drivers to submit batchbuffers directly to hardware, relying 554c1737f2bSArnaldo Carvalho de Melo * on the security mechanisms provided by hardware. 555c1737f2bSArnaldo Carvalho de Melo */ 556c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_batchbuffer { 557c1737f2bSArnaldo Carvalho de Melo int start; /* agp offset */ 558c1737f2bSArnaldo Carvalho de Melo int used; /* nr bytes in use */ 559c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 560c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 561c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 562c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 563c1737f2bSArnaldo Carvalho de Melo } drm_i915_batchbuffer_t; 564c1737f2bSArnaldo Carvalho de Melo 565c1737f2bSArnaldo Carvalho de Melo /* As above, but pass a pointer to userspace buffer which can be 566c1737f2bSArnaldo Carvalho de Melo * validated by the kernel prior to sending to hardware. 567c1737f2bSArnaldo Carvalho de Melo */ 568c1737f2bSArnaldo Carvalho de Melo typedef struct _drm_i915_cmdbuffer { 569c1737f2bSArnaldo Carvalho de Melo char __user *buf; /* pointer to userspace command buffer */ 570c1737f2bSArnaldo Carvalho de Melo int sz; /* nr bytes in buf */ 571c1737f2bSArnaldo Carvalho de Melo int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 572c1737f2bSArnaldo Carvalho de Melo int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 573c1737f2bSArnaldo Carvalho de Melo int num_cliprects; /* mulitpass with multiple cliprects? */ 574c1737f2bSArnaldo Carvalho de Melo struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 575c1737f2bSArnaldo Carvalho de Melo } drm_i915_cmdbuffer_t; 576c1737f2bSArnaldo Carvalho de Melo 577c1737f2bSArnaldo Carvalho de Melo /* Userspace can request & wait on irq's: 578c1737f2bSArnaldo Carvalho de Melo */ 579c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_emit { 580c1737f2bSArnaldo Carvalho de Melo int __user *irq_seq; 581c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_emit_t; 582c1737f2bSArnaldo Carvalho de Melo 583c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_irq_wait { 584c1737f2bSArnaldo Carvalho de Melo int irq_seq; 585c1737f2bSArnaldo Carvalho de Melo } drm_i915_irq_wait_t; 586c1737f2bSArnaldo Carvalho de Melo 5878858ecb5SArnaldo Carvalho de Melo /* 5888858ecb5SArnaldo Carvalho de Melo * Different modes of per-process Graphics Translation Table, 5898858ecb5SArnaldo Carvalho de Melo * see I915_PARAM_HAS_ALIASING_PPGTT 5908858ecb5SArnaldo Carvalho de Melo */ 5918858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_NONE 0 5928858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_ALIASING 1 5938858ecb5SArnaldo Carvalho de Melo #define I915_GEM_PPGTT_FULL 2 5948858ecb5SArnaldo Carvalho de Melo 595c1737f2bSArnaldo Carvalho de Melo /* Ioctl to query kernel params: 596c1737f2bSArnaldo Carvalho de Melo */ 597c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_IRQ_ACTIVE 1 598c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_ALLOW_BATCHBUFFER 2 599c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_LAST_DISPATCH 3 600c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CHIPSET_ID 4 601c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEM 5 602c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_NUM_FENCES_AVAIL 6 603c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_OVERLAY 7 604c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PAGEFLIPPING 8 605c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXECBUF2 9 606c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD 10 607c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BLT 11 608c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_FENCING 12 609c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_RINGS 13 610c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CONSTANTS 14 611c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RELAXED_DELTA 15 612c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GEN7_SOL_RESET 16 613c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_LLC 17 614c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_ALIASING_PPGTT 18 615c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WAIT_TIMEOUT 19 616c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SEMAPHORES 20 617c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 618c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_VEBOX 22 619c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SECURE_BATCHES 23 620c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_PINNED_BATCHES 24 621c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_NO_RELOC 25 622c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 623c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_WT 27 624c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_CMD_PARSER_VERSION 28 625c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 626c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_VERSION 30 627c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_BSD2 31 628c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_REVISION 32 629c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_TOTAL 33 630c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_EU_TOTAL 34 631c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_GPU_RESET 35 632c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_RESOURCE_STREAMER 36 633c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_SOFTPIN 37 634c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_POOLED_EU 38 635c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MIN_EU_IN_POOL 39 636c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_MMAP_GTT_VERSION 40 637c1737f2bSArnaldo Carvalho de Melo 638485be0cbSArnaldo Carvalho de Melo /* 639485be0cbSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 640c1737f2bSArnaldo Carvalho de Melo * priorities and the driver will attempt to execute batches in priority order. 641485be0cbSArnaldo Carvalho de Melo * The param returns a capability bitmask, nonzero implies that the scheduler 642485be0cbSArnaldo Carvalho de Melo * is enabled, with different features present according to the mask. 643485be0cbSArnaldo Carvalho de Melo * 644485be0cbSArnaldo Carvalho de Melo * The initial priority for each batch is supplied by the context and is 645485be0cbSArnaldo Carvalho de Melo * controlled via I915_CONTEXT_PARAM_PRIORITY. 646c1737f2bSArnaldo Carvalho de Melo */ 647c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_SCHEDULER 41 648485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 649485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 650485be0cbSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 651e6aff9f8SArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 65208a96a31SArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 6534dc24d7cSArnaldo Carvalho de Melo /* 6544dc24d7cSArnaldo Carvalho de Melo * Indicates the 2k user priority levels are statically mapped into 3 buckets as 6554dc24d7cSArnaldo Carvalho de Melo * follows: 6564dc24d7cSArnaldo Carvalho de Melo * 6574dc24d7cSArnaldo Carvalho de Melo * -1k to -1 Low priority 6584dc24d7cSArnaldo Carvalho de Melo * 0 Normal priority 6594dc24d7cSArnaldo Carvalho de Melo * 1 to 1k Highest priority 6604dc24d7cSArnaldo Carvalho de Melo */ 6614dc24d7cSArnaldo Carvalho de Melo #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 662485be0cbSArnaldo Carvalho de Melo 663eeac18e2SArnaldo Carvalho de Melo /* 664eeac18e2SArnaldo Carvalho de Melo * Query the status of HuC load. 665eeac18e2SArnaldo Carvalho de Melo * 666eeac18e2SArnaldo Carvalho de Melo * The query can fail in the following scenarios with the listed error codes: 667eeac18e2SArnaldo Carvalho de Melo * -ENODEV if HuC is not present on this platform, 668eeac18e2SArnaldo Carvalho de Melo * -EOPNOTSUPP if HuC firmware usage is disabled, 669eeac18e2SArnaldo Carvalho de Melo * -ENOPKG if HuC firmware fetch failed, 670eeac18e2SArnaldo Carvalho de Melo * -ENOEXEC if HuC firmware is invalid or mismatched, 671eeac18e2SArnaldo Carvalho de Melo * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC, 672eeac18e2SArnaldo Carvalho de Melo * -EIO if the FW transfer or the FW authentication failed. 673eeac18e2SArnaldo Carvalho de Melo * 674eeac18e2SArnaldo Carvalho de Melo * If the IOCTL is successful, the returned parameter will be set to one of the 675eeac18e2SArnaldo Carvalho de Melo * following values: 676eeac18e2SArnaldo Carvalho de Melo * * 0 if HuC firmware load is not complete, 677*142256d2SArnaldo Carvalho de Melo * * 1 if HuC firmware is loaded and fully authenticated, 678*142256d2SArnaldo Carvalho de Melo * * 2 if HuC firmware is loaded and authenticated for clear media only 679eeac18e2SArnaldo Carvalho de Melo */ 680c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HUC_STATUS 42 681c1737f2bSArnaldo Carvalho de Melo 682c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 683c1737f2bSArnaldo Carvalho de Melo * synchronisation with implicit fencing on individual objects. 684c1737f2bSArnaldo Carvalho de Melo * See EXEC_OBJECT_ASYNC. 685c1737f2bSArnaldo Carvalho de Melo */ 686c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_ASYNC 43 687c1737f2bSArnaldo Carvalho de Melo 688c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 689c1737f2bSArnaldo Carvalho de Melo * both being able to pass in a sync_file fd to wait upon before executing, 690c1737f2bSArnaldo Carvalho de Melo * and being able to return a new sync_file fd that is signaled when the 691c1737f2bSArnaldo Carvalho de Melo * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 692c1737f2bSArnaldo Carvalho de Melo */ 693c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_FENCE 44 694c1737f2bSArnaldo Carvalho de Melo 695c1737f2bSArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 696c1737f2bSArnaldo Carvalho de Melo * user specified bufffers for post-mortem debugging of GPU hangs. See 697c1737f2bSArnaldo Carvalho de Melo * EXEC_OBJECT_CAPTURE. 698c1737f2bSArnaldo Carvalho de Melo */ 699c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_CAPTURE 45 700c1737f2bSArnaldo Carvalho de Melo 701c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SLICE_MASK 46 702c1737f2bSArnaldo Carvalho de Melo 703c1737f2bSArnaldo Carvalho de Melo /* Assuming it's uniform for each slice, this queries the mask of subslices 704c1737f2bSArnaldo Carvalho de Melo * per-slice for this system. 705c1737f2bSArnaldo Carvalho de Melo */ 706c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_SUBSLICE_MASK 47 707c1737f2bSArnaldo Carvalho de Melo 708c1737f2bSArnaldo Carvalho de Melo /* 709c1737f2bSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 710c1737f2bSArnaldo Carvalho de Melo * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 711c1737f2bSArnaldo Carvalho de Melo */ 712c1737f2bSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 713c1737f2bSArnaldo Carvalho de Melo 714549a3976SIngo Molnar /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 715549a3976SIngo Molnar * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 716549a3976SIngo Molnar */ 717549a3976SIngo Molnar #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 718549a3976SIngo Molnar 719f091f1d6SIngo Molnar /* 720f091f1d6SIngo Molnar * Query whether every context (both per-file default and user created) is 721f091f1d6SIngo Molnar * isolated (insofar as HW supports). If this parameter is not true, then 722f091f1d6SIngo Molnar * freshly created contexts may inherit values from an existing context, 723f091f1d6SIngo Molnar * rather than default HW values. If true, it also ensures (insofar as HW 724f091f1d6SIngo Molnar * supports) that all state set by this context will not leak to any other 725f091f1d6SIngo Molnar * context. 726f091f1d6SIngo Molnar * 727f091f1d6SIngo Molnar * As not every engine across every gen support contexts, the returned 728f091f1d6SIngo Molnar * value reports the support of context isolation for individual engines by 729f091f1d6SIngo Molnar * returning a bitmask of each engine class set to true if that class supports 730f091f1d6SIngo Molnar * isolation. 731f091f1d6SIngo Molnar */ 732f091f1d6SIngo Molnar #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 733f091f1d6SIngo Molnar 734f091f1d6SIngo Molnar /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 735f091f1d6SIngo Molnar * registers. This used to be fixed per platform but from CNL onwards, this 736f091f1d6SIngo Molnar * might vary depending on the parts. 737f091f1d6SIngo Molnar */ 738f091f1d6SIngo Molnar #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 739f091f1d6SIngo Molnar 74053f00f45SArnaldo Carvalho de Melo /* 74153f00f45SArnaldo Carvalho de Melo * Once upon a time we supposed that writes through the GGTT would be 74253f00f45SArnaldo Carvalho de Melo * immediately in physical memory (once flushed out of the CPU path). However, 74353f00f45SArnaldo Carvalho de Melo * on a few different processors and chipsets, this is not necessarily the case 74453f00f45SArnaldo Carvalho de Melo * as the writes appear to be buffered internally. Thus a read of the backing 74553f00f45SArnaldo Carvalho de Melo * storage (physical memory) via a different path (with different physical tags 74653f00f45SArnaldo Carvalho de Melo * to the indirect write via the GGTT) will see stale values from before 74753f00f45SArnaldo Carvalho de Melo * the GGTT write. Inside the kernel, we can for the most part keep track of 74853f00f45SArnaldo Carvalho de Melo * the different read/write domains in use (e.g. set-domain), but the assumption 74953f00f45SArnaldo Carvalho de Melo * of coherency is baked into the ABI, hence reporting its true state in this 75053f00f45SArnaldo Carvalho de Melo * parameter. 75153f00f45SArnaldo Carvalho de Melo * 75253f00f45SArnaldo Carvalho de Melo * Reports true when writes via mmap_gtt are immediately visible following an 75353f00f45SArnaldo Carvalho de Melo * lfence to flush the WCB. 75453f00f45SArnaldo Carvalho de Melo * 75553f00f45SArnaldo Carvalho de Melo * Reports false when writes via mmap_gtt are indeterminately delayed in an in 75653f00f45SArnaldo Carvalho de Melo * internal buffer and are _not_ immediately visible to third parties accessing 75753f00f45SArnaldo Carvalho de Melo * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 75853f00f45SArnaldo Carvalho de Melo * communications channel when reporting false is strongly disadvised. 75953f00f45SArnaldo Carvalho de Melo */ 76053f00f45SArnaldo Carvalho de Melo #define I915_PARAM_MMAP_GTT_COHERENT 52 76153f00f45SArnaldo Carvalho de Melo 76295dc663aSArnaldo Carvalho de Melo /* 76395dc663aSArnaldo Carvalho de Melo * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel 76495dc663aSArnaldo Carvalho de Melo * execution through use of explicit fence support. 76595dc663aSArnaldo Carvalho de Melo * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. 76695dc663aSArnaldo Carvalho de Melo */ 76795dc663aSArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 7680b3fca6aSArnaldo Carvalho de Melo 7690b3fca6aSArnaldo Carvalho de Melo /* 7700b3fca6aSArnaldo Carvalho de Melo * Revision of the i915-perf uAPI. The value returned helps determine what 7710b3fca6aSArnaldo Carvalho de Melo * i915-perf features are available. See drm_i915_perf_property_id. 7720b3fca6aSArnaldo Carvalho de Melo */ 7730b3fca6aSArnaldo Carvalho de Melo #define I915_PARAM_PERF_REVISION 54 7740b3fca6aSArnaldo Carvalho de Melo 7759e228f48SArnaldo Carvalho de Melo /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 7769e228f48SArnaldo Carvalho de Melo * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See 7779e228f48SArnaldo Carvalho de Melo * I915_EXEC_USE_EXTENSIONS. 7789e228f48SArnaldo Carvalho de Melo */ 7799e228f48SArnaldo Carvalho de Melo #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 7809e228f48SArnaldo Carvalho de Melo 7814dc24d7cSArnaldo Carvalho de Melo /* Query if the kernel supports the I915_USERPTR_PROBE flag. */ 7824dc24d7cSArnaldo Carvalho de Melo #define I915_PARAM_HAS_USERPTR_PROBE 56 7834dc24d7cSArnaldo Carvalho de Melo 784eeac18e2SArnaldo Carvalho de Melo /* 785eeac18e2SArnaldo Carvalho de Melo * Frequency of the timestamps in OA reports. This used to be the same as the CS 786eeac18e2SArnaldo Carvalho de Melo * timestamp frequency, but differs on some platforms. 787eeac18e2SArnaldo Carvalho de Melo */ 788eeac18e2SArnaldo Carvalho de Melo #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57 789eeac18e2SArnaldo Carvalho de Melo 790*142256d2SArnaldo Carvalho de Melo /* 791*142256d2SArnaldo Carvalho de Melo * Query the status of PXP support in i915. 792*142256d2SArnaldo Carvalho de Melo * 793*142256d2SArnaldo Carvalho de Melo * The query can fail in the following scenarios with the listed error codes: 794*142256d2SArnaldo Carvalho de Melo * -ENODEV = PXP support is not available on the GPU device or in the 795*142256d2SArnaldo Carvalho de Melo * kernel due to missing component drivers or kernel configs. 796*142256d2SArnaldo Carvalho de Melo * 797*142256d2SArnaldo Carvalho de Melo * If the IOCTL is successful, the returned parameter will be set to one of 798*142256d2SArnaldo Carvalho de Melo * the following values: 799*142256d2SArnaldo Carvalho de Melo * 1 = PXP feature is supported and is ready for use. 800*142256d2SArnaldo Carvalho de Melo * 2 = PXP feature is supported but should be ready soon (pending 801*142256d2SArnaldo Carvalho de Melo * initialization of non-i915 system dependencies). 802*142256d2SArnaldo Carvalho de Melo * 803*142256d2SArnaldo Carvalho de Melo * NOTE: When param is supported (positive return values), user space should 804*142256d2SArnaldo Carvalho de Melo * still refer to the GEM PXP context-creation UAPI header specs to be 805*142256d2SArnaldo Carvalho de Melo * aware of possible failure due to system state machine at the time. 806*142256d2SArnaldo Carvalho de Melo */ 807*142256d2SArnaldo Carvalho de Melo #define I915_PARAM_PXP_STATUS 58 808*142256d2SArnaldo Carvalho de Melo 809e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 810e6aff9f8SArnaldo Carvalho de Melo 81154cd4cdeSArnaldo Carvalho de Melo /** 81254cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_getparam - Driver parameter query structure. 81354cd4cdeSArnaldo Carvalho de Melo */ 81454cd4cdeSArnaldo Carvalho de Melo struct drm_i915_getparam { 81554cd4cdeSArnaldo Carvalho de Melo /** @param: Driver parameter to query. */ 816c1737f2bSArnaldo Carvalho de Melo __s32 param; 81754cd4cdeSArnaldo Carvalho de Melo 81854cd4cdeSArnaldo Carvalho de Melo /** 81954cd4cdeSArnaldo Carvalho de Melo * @value: Address of memory where queried value should be put. 82054cd4cdeSArnaldo Carvalho de Melo * 821c1737f2bSArnaldo Carvalho de Melo * WARNING: Using pointers instead of fixed-size u64 means we need to write 822c1737f2bSArnaldo Carvalho de Melo * compat32 code. Don't repeat this mistake. 823c1737f2bSArnaldo Carvalho de Melo */ 824c1737f2bSArnaldo Carvalho de Melo int __user *value; 82554cd4cdeSArnaldo Carvalho de Melo }; 82654cd4cdeSArnaldo Carvalho de Melo 82754cd4cdeSArnaldo Carvalho de Melo /** 82854cd4cdeSArnaldo Carvalho de Melo * typedef drm_i915_getparam_t - Driver parameter query structure. 82954cd4cdeSArnaldo Carvalho de Melo * See struct drm_i915_getparam. 83054cd4cdeSArnaldo Carvalho de Melo */ 83154cd4cdeSArnaldo Carvalho de Melo typedef struct drm_i915_getparam drm_i915_getparam_t; 832c1737f2bSArnaldo Carvalho de Melo 833c1737f2bSArnaldo Carvalho de Melo /* Ioctl to set kernel params: 834c1737f2bSArnaldo Carvalho de Melo */ 835c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 836c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 837c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 838c1737f2bSArnaldo Carvalho de Melo #define I915_SETPARAM_NUM_USED_FENCES 4 839e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes */ 840c1737f2bSArnaldo Carvalho de Melo 841c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_setparam { 842c1737f2bSArnaldo Carvalho de Melo int param; 843c1737f2bSArnaldo Carvalho de Melo int value; 844c1737f2bSArnaldo Carvalho de Melo } drm_i915_setparam_t; 845c1737f2bSArnaldo Carvalho de Melo 846c1737f2bSArnaldo Carvalho de Melo /* A memory manager for regions of shared memory: 847c1737f2bSArnaldo Carvalho de Melo */ 848c1737f2bSArnaldo Carvalho de Melo #define I915_MEM_REGION_AGP 1 849c1737f2bSArnaldo Carvalho de Melo 850c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_alloc { 851c1737f2bSArnaldo Carvalho de Melo int region; 852c1737f2bSArnaldo Carvalho de Melo int alignment; 853c1737f2bSArnaldo Carvalho de Melo int size; 854c1737f2bSArnaldo Carvalho de Melo int __user *region_offset; /* offset from start of fb or agp */ 855c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_alloc_t; 856c1737f2bSArnaldo Carvalho de Melo 857c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_free { 858c1737f2bSArnaldo Carvalho de Melo int region; 859c1737f2bSArnaldo Carvalho de Melo int region_offset; 860c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_free_t; 861c1737f2bSArnaldo Carvalho de Melo 862c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_init_heap { 863c1737f2bSArnaldo Carvalho de Melo int region; 864c1737f2bSArnaldo Carvalho de Melo int size; 865c1737f2bSArnaldo Carvalho de Melo int start; 866c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_init_heap_t; 867c1737f2bSArnaldo Carvalho de Melo 868c1737f2bSArnaldo Carvalho de Melo /* Allow memory manager to be torn down and re-initialized (eg on 869c1737f2bSArnaldo Carvalho de Melo * rotate): 870c1737f2bSArnaldo Carvalho de Melo */ 871c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_mem_destroy_heap { 872c1737f2bSArnaldo Carvalho de Melo int region; 873c1737f2bSArnaldo Carvalho de Melo } drm_i915_mem_destroy_heap_t; 874c1737f2bSArnaldo Carvalho de Melo 875c1737f2bSArnaldo Carvalho de Melo /* Allow X server to configure which pipes to monitor for vblank signals 876c1737f2bSArnaldo Carvalho de Melo */ 877c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_A 1 878c1737f2bSArnaldo Carvalho de Melo #define DRM_I915_VBLANK_PIPE_B 2 879c1737f2bSArnaldo Carvalho de Melo 880c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_pipe { 881c1737f2bSArnaldo Carvalho de Melo int pipe; 882c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_pipe_t; 883c1737f2bSArnaldo Carvalho de Melo 884c1737f2bSArnaldo Carvalho de Melo /* Schedule buffer swap at given vertical blank: 885c1737f2bSArnaldo Carvalho de Melo */ 886c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_vblank_swap { 887c1737f2bSArnaldo Carvalho de Melo drm_drawable_t drawable; 888c1737f2bSArnaldo Carvalho de Melo enum drm_vblank_seq_type seqtype; 889c1737f2bSArnaldo Carvalho de Melo unsigned int sequence; 890c1737f2bSArnaldo Carvalho de Melo } drm_i915_vblank_swap_t; 891c1737f2bSArnaldo Carvalho de Melo 892c1737f2bSArnaldo Carvalho de Melo typedef struct drm_i915_hws_addr { 893c1737f2bSArnaldo Carvalho de Melo __u64 addr; 894c1737f2bSArnaldo Carvalho de Melo } drm_i915_hws_addr_t; 895c1737f2bSArnaldo Carvalho de Melo 896c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_init { 897c1737f2bSArnaldo Carvalho de Melo /** 898c1737f2bSArnaldo Carvalho de Melo * Beginning offset in the GTT to be managed by the DRM memory 899c1737f2bSArnaldo Carvalho de Melo * manager. 900c1737f2bSArnaldo Carvalho de Melo */ 901c1737f2bSArnaldo Carvalho de Melo __u64 gtt_start; 902c1737f2bSArnaldo Carvalho de Melo /** 903c1737f2bSArnaldo Carvalho de Melo * Ending offset in the GTT to be managed by the DRM memory 904c1737f2bSArnaldo Carvalho de Melo * manager. 905c1737f2bSArnaldo Carvalho de Melo */ 906c1737f2bSArnaldo Carvalho de Melo __u64 gtt_end; 907c1737f2bSArnaldo Carvalho de Melo }; 908c1737f2bSArnaldo Carvalho de Melo 909c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_create { 910c1737f2bSArnaldo Carvalho de Melo /** 911c1737f2bSArnaldo Carvalho de Melo * Requested size for the object. 912c1737f2bSArnaldo Carvalho de Melo * 913c1737f2bSArnaldo Carvalho de Melo * The (page-aligned) allocated size for the object will be returned. 914c1737f2bSArnaldo Carvalho de Melo */ 915c1737f2bSArnaldo Carvalho de Melo __u64 size; 916c1737f2bSArnaldo Carvalho de Melo /** 917c1737f2bSArnaldo Carvalho de Melo * Returned handle for the object. 918c1737f2bSArnaldo Carvalho de Melo * 919c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 920c1737f2bSArnaldo Carvalho de Melo */ 921c1737f2bSArnaldo Carvalho de Melo __u32 handle; 922c1737f2bSArnaldo Carvalho de Melo __u32 pad; 923c1737f2bSArnaldo Carvalho de Melo }; 924c1737f2bSArnaldo Carvalho de Melo 925c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pread { 926c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being read. */ 927c1737f2bSArnaldo Carvalho de Melo __u32 handle; 928c1737f2bSArnaldo Carvalho de Melo __u32 pad; 929c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to read from */ 930c1737f2bSArnaldo Carvalho de Melo __u64 offset; 931c1737f2bSArnaldo Carvalho de Melo /** Length of data to read */ 932c1737f2bSArnaldo Carvalho de Melo __u64 size; 933c1737f2bSArnaldo Carvalho de Melo /** 934c1737f2bSArnaldo Carvalho de Melo * Pointer to write the data into. 935c1737f2bSArnaldo Carvalho de Melo * 936c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 937c1737f2bSArnaldo Carvalho de Melo */ 938c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 939c1737f2bSArnaldo Carvalho de Melo }; 940c1737f2bSArnaldo Carvalho de Melo 941c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pwrite { 942c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being written to. */ 943c1737f2bSArnaldo Carvalho de Melo __u32 handle; 944c1737f2bSArnaldo Carvalho de Melo __u32 pad; 945c1737f2bSArnaldo Carvalho de Melo /** Offset into the object to write to */ 946c1737f2bSArnaldo Carvalho de Melo __u64 offset; 947c1737f2bSArnaldo Carvalho de Melo /** Length of data to write */ 948c1737f2bSArnaldo Carvalho de Melo __u64 size; 949c1737f2bSArnaldo Carvalho de Melo /** 950c1737f2bSArnaldo Carvalho de Melo * Pointer to read the data from. 951c1737f2bSArnaldo Carvalho de Melo * 952c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 953c1737f2bSArnaldo Carvalho de Melo */ 954c1737f2bSArnaldo Carvalho de Melo __u64 data_ptr; 955c1737f2bSArnaldo Carvalho de Melo }; 956c1737f2bSArnaldo Carvalho de Melo 957c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap { 958c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 959c1737f2bSArnaldo Carvalho de Melo __u32 handle; 960c1737f2bSArnaldo Carvalho de Melo __u32 pad; 961c1737f2bSArnaldo Carvalho de Melo /** Offset in the object to map. */ 962c1737f2bSArnaldo Carvalho de Melo __u64 offset; 963c1737f2bSArnaldo Carvalho de Melo /** 964c1737f2bSArnaldo Carvalho de Melo * Length of data to map. 965c1737f2bSArnaldo Carvalho de Melo * 966c1737f2bSArnaldo Carvalho de Melo * The value will be page-aligned. 967c1737f2bSArnaldo Carvalho de Melo */ 968c1737f2bSArnaldo Carvalho de Melo __u64 size; 969c1737f2bSArnaldo Carvalho de Melo /** 970c1737f2bSArnaldo Carvalho de Melo * Returned pointer the data was mapped at. 971c1737f2bSArnaldo Carvalho de Melo * 972c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 973c1737f2bSArnaldo Carvalho de Melo */ 974c1737f2bSArnaldo Carvalho de Melo __u64 addr_ptr; 975c1737f2bSArnaldo Carvalho de Melo 976c1737f2bSArnaldo Carvalho de Melo /** 977c1737f2bSArnaldo Carvalho de Melo * Flags for extended behaviour. 978c1737f2bSArnaldo Carvalho de Melo * 979c1737f2bSArnaldo Carvalho de Melo * Added in version 2. 980c1737f2bSArnaldo Carvalho de Melo */ 981c1737f2bSArnaldo Carvalho de Melo __u64 flags; 982c1737f2bSArnaldo Carvalho de Melo #define I915_MMAP_WC 0x1 983c1737f2bSArnaldo Carvalho de Melo }; 984c1737f2bSArnaldo Carvalho de Melo 985c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_mmap_gtt { 986c1737f2bSArnaldo Carvalho de Melo /** Handle for the object being mapped. */ 987c1737f2bSArnaldo Carvalho de Melo __u32 handle; 988c1737f2bSArnaldo Carvalho de Melo __u32 pad; 989c1737f2bSArnaldo Carvalho de Melo /** 990c1737f2bSArnaldo Carvalho de Melo * Fake offset to use for subsequent mmap call 991c1737f2bSArnaldo Carvalho de Melo * 992c1737f2bSArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 993c1737f2bSArnaldo Carvalho de Melo */ 994c1737f2bSArnaldo Carvalho de Melo __u64 offset; 995c1737f2bSArnaldo Carvalho de Melo }; 996c1737f2bSArnaldo Carvalho de Melo 9974dc24d7cSArnaldo Carvalho de Melo /** 9984dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. 9994dc24d7cSArnaldo Carvalho de Melo * 10004dc24d7cSArnaldo Carvalho de Melo * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, 10014dc24d7cSArnaldo Carvalho de Melo * and is used to retrieve the fake offset to mmap an object specified by &handle. 10024dc24d7cSArnaldo Carvalho de Melo * 10034dc24d7cSArnaldo Carvalho de Melo * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. 10044dc24d7cSArnaldo Carvalho de Melo * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave 10054dc24d7cSArnaldo Carvalho de Melo * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. 10064dc24d7cSArnaldo Carvalho de Melo */ 1007365f9cc1SArnaldo Carvalho de Melo struct drm_i915_gem_mmap_offset { 10084dc24d7cSArnaldo Carvalho de Melo /** @handle: Handle for the object being mapped. */ 1009365f9cc1SArnaldo Carvalho de Melo __u32 handle; 10104dc24d7cSArnaldo Carvalho de Melo /** @pad: Must be zero */ 1011365f9cc1SArnaldo Carvalho de Melo __u32 pad; 1012365f9cc1SArnaldo Carvalho de Melo /** 10134dc24d7cSArnaldo Carvalho de Melo * @offset: The fake offset to use for subsequent mmap call 1014365f9cc1SArnaldo Carvalho de Melo * 1015365f9cc1SArnaldo Carvalho de Melo * This is a fixed-size type for 32/64 compatibility. 1016365f9cc1SArnaldo Carvalho de Melo */ 1017365f9cc1SArnaldo Carvalho de Melo __u64 offset; 1018365f9cc1SArnaldo Carvalho de Melo 1019365f9cc1SArnaldo Carvalho de Melo /** 10204dc24d7cSArnaldo Carvalho de Melo * @flags: Flags for extended behaviour. 1021365f9cc1SArnaldo Carvalho de Melo * 10224dc24d7cSArnaldo Carvalho de Melo * It is mandatory that one of the `MMAP_OFFSET` types 10234dc24d7cSArnaldo Carvalho de Melo * should be included: 10244dc24d7cSArnaldo Carvalho de Melo * 10254dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) 10264dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. 10274dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. 10284dc24d7cSArnaldo Carvalho de Melo * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. 10294dc24d7cSArnaldo Carvalho de Melo * 10304dc24d7cSArnaldo Carvalho de Melo * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid 10314dc24d7cSArnaldo Carvalho de Melo * type. On devices without local memory, this caching mode is invalid. 10324dc24d7cSArnaldo Carvalho de Melo * 10334dc24d7cSArnaldo Carvalho de Melo * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will 10344dc24d7cSArnaldo Carvalho de Melo * be used, depending on the object placement on creation. WB will be used 10354dc24d7cSArnaldo Carvalho de Melo * when the object can only exist in system memory, WC otherwise. 1036365f9cc1SArnaldo Carvalho de Melo */ 1037365f9cc1SArnaldo Carvalho de Melo __u64 flags; 10384dc24d7cSArnaldo Carvalho de Melo 1039365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_GTT 0 1040365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_WC 1 1041365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_WB 2 1042365f9cc1SArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_UC 3 10434dc24d7cSArnaldo Carvalho de Melo #define I915_MMAP_OFFSET_FIXED 4 1044365f9cc1SArnaldo Carvalho de Melo 10454dc24d7cSArnaldo Carvalho de Melo /** 10464dc24d7cSArnaldo Carvalho de Melo * @extensions: Zero-terminated chain of extensions. 1047365f9cc1SArnaldo Carvalho de Melo * 1048365f9cc1SArnaldo Carvalho de Melo * No current extensions defined; mbz. 1049365f9cc1SArnaldo Carvalho de Melo */ 1050365f9cc1SArnaldo Carvalho de Melo __u64 extensions; 1051365f9cc1SArnaldo Carvalho de Melo }; 1052365f9cc1SArnaldo Carvalho de Melo 10534dc24d7cSArnaldo Carvalho de Melo /** 10544dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in 10554dc24d7cSArnaldo Carvalho de Melo * preparation for accessing the pages via some CPU domain. 10564dc24d7cSArnaldo Carvalho de Melo * 10574dc24d7cSArnaldo Carvalho de Melo * Specifying a new write or read domain will flush the object out of the 10584dc24d7cSArnaldo Carvalho de Melo * previous domain(if required), before then updating the objects domain 10594dc24d7cSArnaldo Carvalho de Melo * tracking with the new domain. 10604dc24d7cSArnaldo Carvalho de Melo * 10614dc24d7cSArnaldo Carvalho de Melo * Note this might involve waiting for the object first if it is still active on 10624dc24d7cSArnaldo Carvalho de Melo * the GPU. 10634dc24d7cSArnaldo Carvalho de Melo * 10644dc24d7cSArnaldo Carvalho de Melo * Supported values for @read_domains and @write_domain: 10654dc24d7cSArnaldo Carvalho de Melo * 10664dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_WC: Uncached write-combined domain 10674dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_CPU: CPU cache domain 10684dc24d7cSArnaldo Carvalho de Melo * - I915_GEM_DOMAIN_GTT: Mappable aperture domain 10694dc24d7cSArnaldo Carvalho de Melo * 10704dc24d7cSArnaldo Carvalho de Melo * All other domains are rejected. 10714dc24d7cSArnaldo Carvalho de Melo * 10724dc24d7cSArnaldo Carvalho de Melo * Note that for discrete, starting from DG1, this is no longer supported, and 10734dc24d7cSArnaldo Carvalho de Melo * is instead rejected. On such platforms the CPU domain is effectively static, 10744dc24d7cSArnaldo Carvalho de Melo * where we also only support a single &drm_i915_gem_mmap_offset cache mode, 10754dc24d7cSArnaldo Carvalho de Melo * which can't be set explicitly and instead depends on the object placements, 10764dc24d7cSArnaldo Carvalho de Melo * as per the below. 10774dc24d7cSArnaldo Carvalho de Melo * 10784dc24d7cSArnaldo Carvalho de Melo * Implicit caching rules, starting from DG1: 10794dc24d7cSArnaldo Carvalho de Melo * 10804dc24d7cSArnaldo Carvalho de Melo * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 10814dc24d7cSArnaldo Carvalho de Melo * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 10824dc24d7cSArnaldo Carvalho de Melo * mapped as write-combined only. 10834dc24d7cSArnaldo Carvalho de Melo * 10844dc24d7cSArnaldo Carvalho de Melo * - Everything else is always allocated and mapped as write-back, with the 10854dc24d7cSArnaldo Carvalho de Melo * guarantee that everything is also coherent with the GPU. 10864dc24d7cSArnaldo Carvalho de Melo * 10874dc24d7cSArnaldo Carvalho de Melo * Note that this is likely to change in the future again, where we might need 10884dc24d7cSArnaldo Carvalho de Melo * more flexibility on future devices, so making this all explicit as part of a 10894dc24d7cSArnaldo Carvalho de Melo * new &drm_i915_gem_create_ext extension is probable. 10904dc24d7cSArnaldo Carvalho de Melo */ 1091c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_domain { 10924dc24d7cSArnaldo Carvalho de Melo /** @handle: Handle for the object. */ 1093c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1094c1737f2bSArnaldo Carvalho de Melo 10954dc24d7cSArnaldo Carvalho de Melo /** @read_domains: New read domains. */ 1096c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 1097c1737f2bSArnaldo Carvalho de Melo 10984dc24d7cSArnaldo Carvalho de Melo /** 10994dc24d7cSArnaldo Carvalho de Melo * @write_domain: New write domain. 11004dc24d7cSArnaldo Carvalho de Melo * 11014dc24d7cSArnaldo Carvalho de Melo * Note that having something in the write domain implies it's in the 11024dc24d7cSArnaldo Carvalho de Melo * read domain, and only that read domain. 11034dc24d7cSArnaldo Carvalho de Melo */ 1104c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 1105c1737f2bSArnaldo Carvalho de Melo }; 1106c1737f2bSArnaldo Carvalho de Melo 1107c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_sw_finish { 1108c1737f2bSArnaldo Carvalho de Melo /** Handle for the object */ 1109c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1110c1737f2bSArnaldo Carvalho de Melo }; 1111c1737f2bSArnaldo Carvalho de Melo 1112c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_relocation_entry { 1113c1737f2bSArnaldo Carvalho de Melo /** 1114c1737f2bSArnaldo Carvalho de Melo * Handle of the buffer being pointed to by this relocation entry. 1115c1737f2bSArnaldo Carvalho de Melo * 1116c1737f2bSArnaldo Carvalho de Melo * It's appealing to make this be an index into the mm_validate_entry 1117c1737f2bSArnaldo Carvalho de Melo * list to refer to the buffer, but this allows the driver to create 1118c1737f2bSArnaldo Carvalho de Melo * a relocation list for state buffers and not re-write it per 1119c1737f2bSArnaldo Carvalho de Melo * exec using the buffer. 1120c1737f2bSArnaldo Carvalho de Melo */ 1121c1737f2bSArnaldo Carvalho de Melo __u32 target_handle; 1122c1737f2bSArnaldo Carvalho de Melo 1123c1737f2bSArnaldo Carvalho de Melo /** 1124c1737f2bSArnaldo Carvalho de Melo * Value to be added to the offset of the target buffer to make up 1125c1737f2bSArnaldo Carvalho de Melo * the relocation entry. 1126c1737f2bSArnaldo Carvalho de Melo */ 1127c1737f2bSArnaldo Carvalho de Melo __u32 delta; 1128c1737f2bSArnaldo Carvalho de Melo 1129c1737f2bSArnaldo Carvalho de Melo /** Offset in the buffer the relocation entry will be written into */ 1130c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1131c1737f2bSArnaldo Carvalho de Melo 1132c1737f2bSArnaldo Carvalho de Melo /** 1133c1737f2bSArnaldo Carvalho de Melo * Offset value of the target buffer that the relocation entry was last 1134c1737f2bSArnaldo Carvalho de Melo * written as. 1135c1737f2bSArnaldo Carvalho de Melo * 1136c1737f2bSArnaldo Carvalho de Melo * If the buffer has the same offset as last time, we can skip syncing 1137c1737f2bSArnaldo Carvalho de Melo * and writing the relocation. This value is written back out by 1138c1737f2bSArnaldo Carvalho de Melo * the execbuffer ioctl when the relocation is written. 1139c1737f2bSArnaldo Carvalho de Melo */ 1140c1737f2bSArnaldo Carvalho de Melo __u64 presumed_offset; 1141c1737f2bSArnaldo Carvalho de Melo 1142c1737f2bSArnaldo Carvalho de Melo /** 1143c1737f2bSArnaldo Carvalho de Melo * Target memory domains read by this operation. 1144c1737f2bSArnaldo Carvalho de Melo */ 1145c1737f2bSArnaldo Carvalho de Melo __u32 read_domains; 1146c1737f2bSArnaldo Carvalho de Melo 1147c1737f2bSArnaldo Carvalho de Melo /** 1148c1737f2bSArnaldo Carvalho de Melo * Target memory domains written by this operation. 1149c1737f2bSArnaldo Carvalho de Melo * 1150c1737f2bSArnaldo Carvalho de Melo * Note that only one domain may be written by the whole 1151c1737f2bSArnaldo Carvalho de Melo * execbuffer operation, so that where there are conflicts, 1152c1737f2bSArnaldo Carvalho de Melo * the application will get -EINVAL back. 1153c1737f2bSArnaldo Carvalho de Melo */ 1154c1737f2bSArnaldo Carvalho de Melo __u32 write_domain; 1155c1737f2bSArnaldo Carvalho de Melo }; 1156c1737f2bSArnaldo Carvalho de Melo 1157c1737f2bSArnaldo Carvalho de Melo /** @{ 1158c1737f2bSArnaldo Carvalho de Melo * Intel memory domains 1159c1737f2bSArnaldo Carvalho de Melo * 1160c1737f2bSArnaldo Carvalho de Melo * Most of these just align with the various caches in 1161c1737f2bSArnaldo Carvalho de Melo * the system and are used to flush and invalidate as 1162c1737f2bSArnaldo Carvalho de Melo * objects end up cached in different domains. 1163c1737f2bSArnaldo Carvalho de Melo */ 1164c1737f2bSArnaldo Carvalho de Melo /** CPU cache */ 1165c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_CPU 0x00000001 1166c1737f2bSArnaldo Carvalho de Melo /** Render cache, used by 2D and 3D drawing */ 1167c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_RENDER 0x00000002 1168c1737f2bSArnaldo Carvalho de Melo /** Sampler cache, used by texture engine */ 1169c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_SAMPLER 0x00000004 1170c1737f2bSArnaldo Carvalho de Melo /** Command queue, used to load batch buffers */ 1171c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_COMMAND 0x00000008 1172c1737f2bSArnaldo Carvalho de Melo /** Instruction cache, used by shader programs */ 1173c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 1174c1737f2bSArnaldo Carvalho de Melo /** Vertex address cache */ 1175c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_VERTEX 0x00000020 1176c1737f2bSArnaldo Carvalho de Melo /** GTT domain - aperture and scanout */ 1177c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_GTT 0x00000040 1178c1737f2bSArnaldo Carvalho de Melo /** WC domain - uncached access */ 1179c1737f2bSArnaldo Carvalho de Melo #define I915_GEM_DOMAIN_WC 0x00000080 1180c1737f2bSArnaldo Carvalho de Melo /** @} */ 1181c1737f2bSArnaldo Carvalho de Melo 1182c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object { 1183c1737f2bSArnaldo Carvalho de Melo /** 1184c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 1185c1737f2bSArnaldo Carvalho de Melo * operation. 1186c1737f2bSArnaldo Carvalho de Melo */ 1187c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1188c1737f2bSArnaldo Carvalho de Melo 1189c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 1190c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 1191c1737f2bSArnaldo Carvalho de Melo /** 1192c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 1193c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 1194c1737f2bSArnaldo Carvalho de Melo */ 1195c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 1196c1737f2bSArnaldo Carvalho de Melo 1197c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 1198c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1199c1737f2bSArnaldo Carvalho de Melo 1200c1737f2bSArnaldo Carvalho de Melo /** 1201c1737f2bSArnaldo Carvalho de Melo * Returned value of the updated offset of the object, for future 1202c1737f2bSArnaldo Carvalho de Melo * presumed_offset writes. 1203c1737f2bSArnaldo Carvalho de Melo */ 1204c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1205c1737f2bSArnaldo Carvalho de Melo }; 1206c1737f2bSArnaldo Carvalho de Melo 12070fdee797SArnaldo Carvalho de Melo /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */ 1208c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer { 1209c1737f2bSArnaldo Carvalho de Melo /** 1210c1737f2bSArnaldo Carvalho de Melo * List of buffers to be validated with their relocations to be 1211c1737f2bSArnaldo Carvalho de Melo * performend on them. 1212c1737f2bSArnaldo Carvalho de Melo * 1213c1737f2bSArnaldo Carvalho de Melo * This is a pointer to an array of struct drm_i915_gem_validate_entry. 1214c1737f2bSArnaldo Carvalho de Melo * 1215c1737f2bSArnaldo Carvalho de Melo * These buffers must be listed in an order such that all relocations 1216c1737f2bSArnaldo Carvalho de Melo * a buffer is performing refer to buffers that have already appeared 1217c1737f2bSArnaldo Carvalho de Melo * in the validate list. 1218c1737f2bSArnaldo Carvalho de Melo */ 1219c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 1220c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 1221c1737f2bSArnaldo Carvalho de Melo 1222c1737f2bSArnaldo Carvalho de Melo /** Offset in the batchbuffer to start execution from. */ 1223c1737f2bSArnaldo Carvalho de Melo __u32 batch_start_offset; 1224c1737f2bSArnaldo Carvalho de Melo /** Bytes used in batchbuffer from batch_start_offset */ 1225c1737f2bSArnaldo Carvalho de Melo __u32 batch_len; 1226c1737f2bSArnaldo Carvalho de Melo __u32 DR1; 1227c1737f2bSArnaldo Carvalho de Melo __u32 DR4; 1228c1737f2bSArnaldo Carvalho de Melo __u32 num_cliprects; 1229c1737f2bSArnaldo Carvalho de Melo /** This is a struct drm_clip_rect *cliprects */ 1230c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 1231c1737f2bSArnaldo Carvalho de Melo }; 1232c1737f2bSArnaldo Carvalho de Melo 1233c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_exec_object2 { 1234c1737f2bSArnaldo Carvalho de Melo /** 1235c1737f2bSArnaldo Carvalho de Melo * User's handle for a buffer to be bound into the GTT for this 1236c1737f2bSArnaldo Carvalho de Melo * operation. 1237c1737f2bSArnaldo Carvalho de Melo */ 1238c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1239c1737f2bSArnaldo Carvalho de Melo 1240c1737f2bSArnaldo Carvalho de Melo /** Number of relocations to be performed on this buffer */ 1241c1737f2bSArnaldo Carvalho de Melo __u32 relocation_count; 1242c1737f2bSArnaldo Carvalho de Melo /** 1243c1737f2bSArnaldo Carvalho de Melo * Pointer to array of struct drm_i915_gem_relocation_entry containing 1244c1737f2bSArnaldo Carvalho de Melo * the relocations to be performed in this buffer. 1245c1737f2bSArnaldo Carvalho de Melo */ 1246c1737f2bSArnaldo Carvalho de Melo __u64 relocs_ptr; 1247c1737f2bSArnaldo Carvalho de Melo 1248c1737f2bSArnaldo Carvalho de Melo /** Required alignment in graphics aperture */ 1249c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1250c1737f2bSArnaldo Carvalho de Melo 1251c1737f2bSArnaldo Carvalho de Melo /** 1252c1737f2bSArnaldo Carvalho de Melo * When the EXEC_OBJECT_PINNED flag is specified this is populated by 1253c1737f2bSArnaldo Carvalho de Melo * the user with the GTT offset at which this object will be pinned. 1254f444b2d1SArnaldo Carvalho de Melo * 1255c1737f2bSArnaldo Carvalho de Melo * When the I915_EXEC_NO_RELOC flag is specified this must contain the 1256c1737f2bSArnaldo Carvalho de Melo * presumed_offset of the object. 1257f444b2d1SArnaldo Carvalho de Melo * 1258c1737f2bSArnaldo Carvalho de Melo * During execbuffer2 the kernel populates it with the value of the 1259c1737f2bSArnaldo Carvalho de Melo * current GTT offset of the object, for future presumed_offset writes. 1260f444b2d1SArnaldo Carvalho de Melo * 1261f444b2d1SArnaldo Carvalho de Melo * See struct drm_i915_gem_create_ext for the rules when dealing with 1262f444b2d1SArnaldo Carvalho de Melo * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with 1263f444b2d1SArnaldo Carvalho de Melo * minimum page sizes, like DG2. 1264c1737f2bSArnaldo Carvalho de Melo */ 1265c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1266c1737f2bSArnaldo Carvalho de Melo 1267c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 1268c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_NEEDS_GTT (1<<1) 1269c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_WRITE (1<<2) 1270c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 1271c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PINNED (1<<4) 1272c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 1273c1737f2bSArnaldo Carvalho de Melo /* The kernel implicitly tracks GPU activity on all GEM objects, and 1274c1737f2bSArnaldo Carvalho de Melo * synchronises operations with outstanding rendering. This includes 1275c1737f2bSArnaldo Carvalho de Melo * rendering on other devices if exported via dma-buf. However, sometimes 1276c1737f2bSArnaldo Carvalho de Melo * this tracking is too coarse and the user knows better. For example, 1277c1737f2bSArnaldo Carvalho de Melo * if the object is split into non-overlapping ranges shared between different 1278c1737f2bSArnaldo Carvalho de Melo * clients or engines (i.e. suballocating objects), the implicit tracking 1279c1737f2bSArnaldo Carvalho de Melo * by kernel assumes that each operation affects the whole object rather 1280c1737f2bSArnaldo Carvalho de Melo * than an individual range, causing needless synchronisation between clients. 1281c1737f2bSArnaldo Carvalho de Melo * The kernel will also forgo any CPU cache flushes prior to rendering from 1282c1737f2bSArnaldo Carvalho de Melo * the object as the client is expected to be also handling such domain 1283c1737f2bSArnaldo Carvalho de Melo * tracking. 1284c1737f2bSArnaldo Carvalho de Melo * 1285c1737f2bSArnaldo Carvalho de Melo * The kernel maintains the implicit tracking in order to manage resources 1286c1737f2bSArnaldo Carvalho de Melo * used by the GPU - this flag only disables the synchronisation prior to 1287c1737f2bSArnaldo Carvalho de Melo * rendering with this object in this execbuf. 1288c1737f2bSArnaldo Carvalho de Melo * 1289c1737f2bSArnaldo Carvalho de Melo * Opting out of implicit synhronisation requires the user to do its own 1290c1737f2bSArnaldo Carvalho de Melo * explicit tracking to avoid rendering corruption. See, for example, 1291c1737f2bSArnaldo Carvalho de Melo * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 1292c1737f2bSArnaldo Carvalho de Melo */ 1293c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_ASYNC (1<<6) 1294c1737f2bSArnaldo Carvalho de Melo /* Request that the contents of this execobject be copied into the error 1295c1737f2bSArnaldo Carvalho de Melo * state upon a GPU hang involving this batch for post-mortem debugging. 1296c1737f2bSArnaldo Carvalho de Melo * These buffers are recorded in no particular order as "user" in 1297c1737f2bSArnaldo Carvalho de Melo * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 1298c1737f2bSArnaldo Carvalho de Melo * if the kernel supports this flag. 1299c1737f2bSArnaldo Carvalho de Melo */ 1300c1737f2bSArnaldo Carvalho de Melo #define EXEC_OBJECT_CAPTURE (1<<7) 1301c1737f2bSArnaldo Carvalho de Melo /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 1302c1737f2bSArnaldo Carvalho de Melo #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 1303c1737f2bSArnaldo Carvalho de Melo __u64 flags; 1304c1737f2bSArnaldo Carvalho de Melo 1305c1737f2bSArnaldo Carvalho de Melo union { 1306c1737f2bSArnaldo Carvalho de Melo __u64 rsvd1; 1307c1737f2bSArnaldo Carvalho de Melo __u64 pad_to_size; 1308c1737f2bSArnaldo Carvalho de Melo }; 1309c1737f2bSArnaldo Carvalho de Melo __u64 rsvd2; 1310c1737f2bSArnaldo Carvalho de Melo }; 1311c1737f2bSArnaldo Carvalho de Melo 1312549a3976SIngo Molnar /** 131354cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_exec_fence - An input or output fence for the execbuf 131454cd4cdeSArnaldo Carvalho de Melo * ioctl. 131554cd4cdeSArnaldo Carvalho de Melo * 131654cd4cdeSArnaldo Carvalho de Melo * The request will wait for input fence to signal before submission. 131754cd4cdeSArnaldo Carvalho de Melo * 131854cd4cdeSArnaldo Carvalho de Melo * The returned output fence will be signaled after the completion of the 131954cd4cdeSArnaldo Carvalho de Melo * request. 1320549a3976SIngo Molnar */ 132154cd4cdeSArnaldo Carvalho de Melo struct drm_i915_gem_exec_fence { 132254cd4cdeSArnaldo Carvalho de Melo /** @handle: User's handle for a drm_syncobj to wait on or signal. */ 1323549a3976SIngo Molnar __u32 handle; 1324549a3976SIngo Molnar 132554cd4cdeSArnaldo Carvalho de Melo /** 132654cd4cdeSArnaldo Carvalho de Melo * @flags: Supported flags are: 132754cd4cdeSArnaldo Carvalho de Melo * 132854cd4cdeSArnaldo Carvalho de Melo * I915_EXEC_FENCE_WAIT: 132954cd4cdeSArnaldo Carvalho de Melo * Wait for the input fence before request submission. 133054cd4cdeSArnaldo Carvalho de Melo * 133154cd4cdeSArnaldo Carvalho de Melo * I915_EXEC_FENCE_SIGNAL: 133254cd4cdeSArnaldo Carvalho de Melo * Return request completion fence as output 133354cd4cdeSArnaldo Carvalho de Melo */ 133454cd4cdeSArnaldo Carvalho de Melo __u32 flags; 1335549a3976SIngo Molnar #define I915_EXEC_FENCE_WAIT (1<<0) 1336549a3976SIngo Molnar #define I915_EXEC_FENCE_SIGNAL (1<<1) 1337505ee767SIngo Molnar #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1338549a3976SIngo Molnar }; 1339549a3976SIngo Molnar 134054cd4cdeSArnaldo Carvalho de Melo /** 134154cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_execbuffer_ext_timeline_fences - Timeline fences 134254cd4cdeSArnaldo Carvalho de Melo * for execbuf ioctl. 134354cd4cdeSArnaldo Carvalho de Melo * 13449e228f48SArnaldo Carvalho de Melo * This structure describes an array of drm_syncobj and associated points for 13459e228f48SArnaldo Carvalho de Melo * timeline variants of drm_syncobj. It is invalid to append this structure to 13469e228f48SArnaldo Carvalho de Melo * the execbuf if I915_EXEC_FENCE_ARRAY is set. 13479e228f48SArnaldo Carvalho de Melo */ 13489e228f48SArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer_ext_timeline_fences { 134954cd4cdeSArnaldo Carvalho de Melo #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 135054cd4cdeSArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 13519e228f48SArnaldo Carvalho de Melo struct i915_user_extension base; 13529e228f48SArnaldo Carvalho de Melo 13539e228f48SArnaldo Carvalho de Melo /** 135454cd4cdeSArnaldo Carvalho de Melo * @fence_count: Number of elements in the @handles_ptr & @value_ptr 135554cd4cdeSArnaldo Carvalho de Melo * arrays. 13569e228f48SArnaldo Carvalho de Melo */ 13579e228f48SArnaldo Carvalho de Melo __u64 fence_count; 13589e228f48SArnaldo Carvalho de Melo 13599e228f48SArnaldo Carvalho de Melo /** 136054cd4cdeSArnaldo Carvalho de Melo * @handles_ptr: Pointer to an array of struct drm_i915_gem_exec_fence 136154cd4cdeSArnaldo Carvalho de Melo * of length @fence_count. 13629e228f48SArnaldo Carvalho de Melo */ 13639e228f48SArnaldo Carvalho de Melo __u64 handles_ptr; 13649e228f48SArnaldo Carvalho de Melo 13659e228f48SArnaldo Carvalho de Melo /** 136654cd4cdeSArnaldo Carvalho de Melo * @values_ptr: Pointer to an array of u64 values of length 136754cd4cdeSArnaldo Carvalho de Melo * @fence_count. 136854cd4cdeSArnaldo Carvalho de Melo * Values must be 0 for a binary drm_syncobj. A Value of 0 for a 136954cd4cdeSArnaldo Carvalho de Melo * timeline drm_syncobj is invalid as it turns a drm_syncobj into a 137054cd4cdeSArnaldo Carvalho de Melo * binary one. 13719e228f48SArnaldo Carvalho de Melo */ 13729e228f48SArnaldo Carvalho de Melo __u64 values_ptr; 13739e228f48SArnaldo Carvalho de Melo }; 13749e228f48SArnaldo Carvalho de Melo 1375c1737f2bSArnaldo Carvalho de Melo /** 137654cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_execbuffer2 - Structure for DRM_I915_GEM_EXECBUFFER2 137754cd4cdeSArnaldo Carvalho de Melo * ioctl. 1378c1737f2bSArnaldo Carvalho de Melo */ 137954cd4cdeSArnaldo Carvalho de Melo struct drm_i915_gem_execbuffer2 { 138054cd4cdeSArnaldo Carvalho de Melo /** @buffers_ptr: Pointer to a list of gem_exec_object2 structs */ 1381c1737f2bSArnaldo Carvalho de Melo __u64 buffers_ptr; 138254cd4cdeSArnaldo Carvalho de Melo 138354cd4cdeSArnaldo Carvalho de Melo /** @buffer_count: Number of elements in @buffers_ptr array */ 1384c1737f2bSArnaldo Carvalho de Melo __u32 buffer_count; 1385c1737f2bSArnaldo Carvalho de Melo 1386549a3976SIngo Molnar /** 138754cd4cdeSArnaldo Carvalho de Melo * @batch_start_offset: Offset in the batchbuffer to start execution 138854cd4cdeSArnaldo Carvalho de Melo * from. 138954cd4cdeSArnaldo Carvalho de Melo */ 139054cd4cdeSArnaldo Carvalho de Melo __u32 batch_start_offset; 139154cd4cdeSArnaldo Carvalho de Melo 139254cd4cdeSArnaldo Carvalho de Melo /** 139354cd4cdeSArnaldo Carvalho de Melo * @batch_len: Length in bytes of the batch buffer, starting from the 139454cd4cdeSArnaldo Carvalho de Melo * @batch_start_offset. If 0, length is assumed to be the batch buffer 139554cd4cdeSArnaldo Carvalho de Melo * object size. 139654cd4cdeSArnaldo Carvalho de Melo */ 139754cd4cdeSArnaldo Carvalho de Melo __u32 batch_len; 139854cd4cdeSArnaldo Carvalho de Melo 139954cd4cdeSArnaldo Carvalho de Melo /** @DR1: deprecated */ 140054cd4cdeSArnaldo Carvalho de Melo __u32 DR1; 140154cd4cdeSArnaldo Carvalho de Melo 140254cd4cdeSArnaldo Carvalho de Melo /** @DR4: deprecated */ 140354cd4cdeSArnaldo Carvalho de Melo __u32 DR4; 140454cd4cdeSArnaldo Carvalho de Melo 140554cd4cdeSArnaldo Carvalho de Melo /** @num_cliprects: See @cliprects_ptr */ 140654cd4cdeSArnaldo Carvalho de Melo __u32 num_cliprects; 140754cd4cdeSArnaldo Carvalho de Melo 140854cd4cdeSArnaldo Carvalho de Melo /** 140954cd4cdeSArnaldo Carvalho de Melo * @cliprects_ptr: Kernel clipping was a DRI1 misfeature. 141054cd4cdeSArnaldo Carvalho de Melo * 141154cd4cdeSArnaldo Carvalho de Melo * It is invalid to use this field if I915_EXEC_FENCE_ARRAY or 141254cd4cdeSArnaldo Carvalho de Melo * I915_EXEC_USE_EXTENSIONS flags are not set. 14139e228f48SArnaldo Carvalho de Melo * 14149e228f48SArnaldo Carvalho de Melo * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array 141554cd4cdeSArnaldo Carvalho de Melo * of &drm_i915_gem_exec_fence and @num_cliprects is the length of the 141654cd4cdeSArnaldo Carvalho de Melo * array. 14179e228f48SArnaldo Carvalho de Melo * 14189e228f48SArnaldo Carvalho de Melo * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a 141954cd4cdeSArnaldo Carvalho de Melo * single &i915_user_extension and num_cliprects is 0. 1420549a3976SIngo Molnar */ 1421c1737f2bSArnaldo Carvalho de Melo __u64 cliprects_ptr; 142254cd4cdeSArnaldo Carvalho de Melo 142354cd4cdeSArnaldo Carvalho de Melo /** @flags: Execbuf flags */ 142454cd4cdeSArnaldo Carvalho de Melo __u64 flags; 1425e6aff9f8SArnaldo Carvalho de Melo #define I915_EXEC_RING_MASK (0x3f) 1426c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_DEFAULT (0<<0) 1427c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RENDER (1<<0) 1428c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD (2<<0) 1429c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BLT (3<<0) 1430c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_VEBOX (4<<0) 1431c1737f2bSArnaldo Carvalho de Melo 1432c1737f2bSArnaldo Carvalho de Melo /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1433c1737f2bSArnaldo Carvalho de Melo * Gen6+ only supports relative addressing to dynamic state (default) and 1434c1737f2bSArnaldo Carvalho de Melo * absolute addressing. 1435c1737f2bSArnaldo Carvalho de Melo * 1436c1737f2bSArnaldo Carvalho de Melo * These flags are ignored for the BSD and BLT rings. 1437c1737f2bSArnaldo Carvalho de Melo */ 1438c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_MASK (3<<6) 1439c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1440c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1441c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1442c1737f2bSArnaldo Carvalho de Melo 1443c1737f2bSArnaldo Carvalho de Melo /** Resets the SO write offset registers for transform feedback on gen7. */ 1444c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1445c1737f2bSArnaldo Carvalho de Melo 1446c1737f2bSArnaldo Carvalho de Melo /** Request a privileged ("secure") batch buffer. Note only available for 1447c1737f2bSArnaldo Carvalho de Melo * DRM_ROOT_ONLY | DRM_MASTER processes. 1448c1737f2bSArnaldo Carvalho de Melo */ 1449c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_SECURE (1<<9) 1450c1737f2bSArnaldo Carvalho de Melo 1451c1737f2bSArnaldo Carvalho de Melo /** Inform the kernel that the batch is and will always be pinned. This 1452c1737f2bSArnaldo Carvalho de Melo * negates the requirement for a workaround to be performed to avoid 1453c1737f2bSArnaldo Carvalho de Melo * an incoherent CS (such as can be found on 830/845). If this flag is 1454c1737f2bSArnaldo Carvalho de Melo * not passed, the kernel will endeavour to make sure the batch is 1455c1737f2bSArnaldo Carvalho de Melo * coherent with the CS before execution. If this flag is passed, 1456c1737f2bSArnaldo Carvalho de Melo * userspace assumes the responsibility for ensuring the same. 1457c1737f2bSArnaldo Carvalho de Melo */ 1458c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_IS_PINNED (1<<10) 1459c1737f2bSArnaldo Carvalho de Melo 1460c1737f2bSArnaldo Carvalho de Melo /** Provide a hint to the kernel that the command stream and auxiliary 1461c1737f2bSArnaldo Carvalho de Melo * state buffers already holds the correct presumed addresses and so the 1462c1737f2bSArnaldo Carvalho de Melo * relocation process may be skipped if no buffers need to be moved in 1463c1737f2bSArnaldo Carvalho de Melo * preparation for the execbuffer. 1464c1737f2bSArnaldo Carvalho de Melo */ 1465c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_NO_RELOC (1<<11) 1466c1737f2bSArnaldo Carvalho de Melo 1467c1737f2bSArnaldo Carvalho de Melo /** Use the reloc.handle as an index into the exec object array rather 1468c1737f2bSArnaldo Carvalho de Melo * than as the per-file handle. 1469c1737f2bSArnaldo Carvalho de Melo */ 1470c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_HANDLE_LUT (1<<12) 1471c1737f2bSArnaldo Carvalho de Melo 1472c1737f2bSArnaldo Carvalho de Melo /** Used for switching BSD rings on the platforms with two BSD rings */ 1473c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_SHIFT (13) 1474c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1475c1737f2bSArnaldo Carvalho de Melo /* default ping-pong mode */ 1476c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1477c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1478c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 1479c1737f2bSArnaldo Carvalho de Melo 1480c1737f2bSArnaldo Carvalho de Melo /** Tell the kernel that the batchbuffer is processed by 1481c1737f2bSArnaldo Carvalho de Melo * the resource streamer. 1482c1737f2bSArnaldo Carvalho de Melo */ 1483c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1484c1737f2bSArnaldo Carvalho de Melo 1485c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1486c1737f2bSArnaldo Carvalho de Melo * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1487c1737f2bSArnaldo Carvalho de Melo * the batch. 1488c1737f2bSArnaldo Carvalho de Melo * 1489c1737f2bSArnaldo Carvalho de Melo * Returns -EINVAL if the sync_file fd cannot be found. 1490c1737f2bSArnaldo Carvalho de Melo */ 1491c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_IN (1<<16) 1492c1737f2bSArnaldo Carvalho de Melo 1493c1737f2bSArnaldo Carvalho de Melo /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1494c1737f2bSArnaldo Carvalho de Melo * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1495c1737f2bSArnaldo Carvalho de Melo * to the caller, and it should be close() after use. (The fd is a regular 1496c1737f2bSArnaldo Carvalho de Melo * file descriptor and will be cleaned up on process termination. It holds 1497c1737f2bSArnaldo Carvalho de Melo * a reference to the request, but nothing else.) 1498c1737f2bSArnaldo Carvalho de Melo * 1499c1737f2bSArnaldo Carvalho de Melo * The sync_file fd can be combined with other sync_file and passed either 1500c1737f2bSArnaldo Carvalho de Melo * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1501c1737f2bSArnaldo Carvalho de Melo * will only occur after this request completes), or to other devices. 1502c1737f2bSArnaldo Carvalho de Melo * 1503c1737f2bSArnaldo Carvalho de Melo * Using I915_EXEC_FENCE_OUT requires use of 1504c1737f2bSArnaldo Carvalho de Melo * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1505c1737f2bSArnaldo Carvalho de Melo * back to userspace. Failure to do so will cause the out-fence to always 1506c1737f2bSArnaldo Carvalho de Melo * be reported as zero, and the real fence fd to be leaked. 1507c1737f2bSArnaldo Carvalho de Melo */ 1508c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_OUT (1<<17) 1509c1737f2bSArnaldo Carvalho de Melo 1510c1737f2bSArnaldo Carvalho de Melo /* 1511c1737f2bSArnaldo Carvalho de Melo * Traditionally the execbuf ioctl has only considered the final element in 1512c1737f2bSArnaldo Carvalho de Melo * the execobject[] to be the executable batch. Often though, the client 1513c1737f2bSArnaldo Carvalho de Melo * will known the batch object prior to construction and being able to place 1514c1737f2bSArnaldo Carvalho de Melo * it into the execobject[] array first can simplify the relocation tracking. 1515c1737f2bSArnaldo Carvalho de Melo * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 1516c1737f2bSArnaldo Carvalho de Melo * execobject[] as the * batch instead (the default is to use the last 1517c1737f2bSArnaldo Carvalho de Melo * element). 1518c1737f2bSArnaldo Carvalho de Melo */ 1519c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_BATCH_FIRST (1<<18) 1520549a3976SIngo Molnar 1521549a3976SIngo Molnar /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1522549a3976SIngo Molnar * define an array of i915_gem_exec_fence structures which specify a set of 1523549a3976SIngo Molnar * dma fences to wait upon or signal. 1524549a3976SIngo Molnar */ 1525549a3976SIngo Molnar #define I915_EXEC_FENCE_ARRAY (1<<19) 1526549a3976SIngo Molnar 152795dc663aSArnaldo Carvalho de Melo /* 152895dc663aSArnaldo Carvalho de Melo * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent 152995dc663aSArnaldo Carvalho de Melo * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 153095dc663aSArnaldo Carvalho de Melo * the batch. 153195dc663aSArnaldo Carvalho de Melo * 153295dc663aSArnaldo Carvalho de Melo * Returns -EINVAL if the sync_file fd cannot be found. 153395dc663aSArnaldo Carvalho de Melo */ 153495dc663aSArnaldo Carvalho de Melo #define I915_EXEC_FENCE_SUBMIT (1 << 20) 153595dc663aSArnaldo Carvalho de Melo 15369e228f48SArnaldo Carvalho de Melo /* 15379e228f48SArnaldo Carvalho de Melo * Setting I915_EXEC_USE_EXTENSIONS implies that 15389e228f48SArnaldo Carvalho de Melo * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked 15399e228f48SArnaldo Carvalho de Melo * list of i915_user_extension. Each i915_user_extension node is the base of a 15409e228f48SArnaldo Carvalho de Melo * larger structure. The list of supported structures are listed in the 15419e228f48SArnaldo Carvalho de Melo * drm_i915_gem_execbuffer_ext enum. 15429e228f48SArnaldo Carvalho de Melo */ 15439e228f48SArnaldo Carvalho de Melo #define I915_EXEC_USE_EXTENSIONS (1 << 21) 15449e228f48SArnaldo Carvalho de Melo #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) 1545c1737f2bSArnaldo Carvalho de Melo 154654cd4cdeSArnaldo Carvalho de Melo /** @rsvd1: Context id */ 154754cd4cdeSArnaldo Carvalho de Melo __u64 rsvd1; 154854cd4cdeSArnaldo Carvalho de Melo 154954cd4cdeSArnaldo Carvalho de Melo /** 155054cd4cdeSArnaldo Carvalho de Melo * @rsvd2: in and out sync_file file descriptors. 155154cd4cdeSArnaldo Carvalho de Melo * 155254cd4cdeSArnaldo Carvalho de Melo * When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the 155354cd4cdeSArnaldo Carvalho de Melo * lower 32 bits of this field will have the in sync_file fd (input). 155454cd4cdeSArnaldo Carvalho de Melo * 155554cd4cdeSArnaldo Carvalho de Melo * When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this 155654cd4cdeSArnaldo Carvalho de Melo * field will have the out sync_file fd (output). 155754cd4cdeSArnaldo Carvalho de Melo */ 155854cd4cdeSArnaldo Carvalho de Melo __u64 rsvd2; 155954cd4cdeSArnaldo Carvalho de Melo }; 156054cd4cdeSArnaldo Carvalho de Melo 1561c1737f2bSArnaldo Carvalho de Melo #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1562c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_set_context_id(eb2, context) \ 1563c1737f2bSArnaldo Carvalho de Melo (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1564c1737f2bSArnaldo Carvalho de Melo #define i915_execbuffer2_get_context_id(eb2) \ 1565c1737f2bSArnaldo Carvalho de Melo ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1566c1737f2bSArnaldo Carvalho de Melo 1567c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_pin { 1568c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be pinned. */ 1569c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1570c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1571c1737f2bSArnaldo Carvalho de Melo 1572c1737f2bSArnaldo Carvalho de Melo /** alignment required within the aperture */ 1573c1737f2bSArnaldo Carvalho de Melo __u64 alignment; 1574c1737f2bSArnaldo Carvalho de Melo 1575c1737f2bSArnaldo Carvalho de Melo /** Returned GTT offset of the buffer. */ 1576c1737f2bSArnaldo Carvalho de Melo __u64 offset; 1577c1737f2bSArnaldo Carvalho de Melo }; 1578c1737f2bSArnaldo Carvalho de Melo 1579c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_unpin { 1580c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to be unpinned. */ 1581c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1582c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1583c1737f2bSArnaldo Carvalho de Melo }; 1584c1737f2bSArnaldo Carvalho de Melo 1585c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_busy { 1586c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to check for busy */ 1587c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1588c1737f2bSArnaldo Carvalho de Melo 1589c1737f2bSArnaldo Carvalho de Melo /** Return busy status 1590c1737f2bSArnaldo Carvalho de Melo * 1591c1737f2bSArnaldo Carvalho de Melo * A return of 0 implies that the object is idle (after 1592c1737f2bSArnaldo Carvalho de Melo * having flushed any pending activity), and a non-zero return that 1593c1737f2bSArnaldo Carvalho de Melo * the object is still in-flight on the GPU. (The GPU has not yet 1594c1737f2bSArnaldo Carvalho de Melo * signaled completion for all pending requests that reference the 1595c1737f2bSArnaldo Carvalho de Melo * object.) An object is guaranteed to become idle eventually (so 1596c1737f2bSArnaldo Carvalho de Melo * long as no new GPU commands are executed upon it). Due to the 1597c1737f2bSArnaldo Carvalho de Melo * asynchronous nature of the hardware, an object reported 1598c1737f2bSArnaldo Carvalho de Melo * as busy may become idle before the ioctl is completed. 1599c1737f2bSArnaldo Carvalho de Melo * 1600c1737f2bSArnaldo Carvalho de Melo * Furthermore, if the object is busy, which engine is busy is only 1601e6aff9f8SArnaldo Carvalho de Melo * provided as a guide and only indirectly by reporting its class 1602e6aff9f8SArnaldo Carvalho de Melo * (there may be more than one engine in each class). There are race 1603e6aff9f8SArnaldo Carvalho de Melo * conditions which prevent the report of which engines are busy from 1604e6aff9f8SArnaldo Carvalho de Melo * being always accurate. However, the converse is not true. If the 1605e6aff9f8SArnaldo Carvalho de Melo * object is idle, the result of the ioctl, that all engines are idle, 1606e6aff9f8SArnaldo Carvalho de Melo * is accurate. 1607c1737f2bSArnaldo Carvalho de Melo * 1608c1737f2bSArnaldo Carvalho de Melo * The returned dword is split into two fields to indicate both 1609e6aff9f8SArnaldo Carvalho de Melo * the engine classess on which the object is being read, and the 1610e6aff9f8SArnaldo Carvalho de Melo * engine class on which it is currently being written (if any). 1611c1737f2bSArnaldo Carvalho de Melo * 1612c1737f2bSArnaldo Carvalho de Melo * The low word (bits 0:15) indicate if the object is being written 1613c1737f2bSArnaldo Carvalho de Melo * to by any engine (there can only be one, as the GEM implicit 1614c1737f2bSArnaldo Carvalho de Melo * synchronisation rules force writes to be serialised). Only the 1615e6aff9f8SArnaldo Carvalho de Melo * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1616e6aff9f8SArnaldo Carvalho de Melo * 1 not 0 etc) for the last write is reported. 1617c1737f2bSArnaldo Carvalho de Melo * 1618e6aff9f8SArnaldo Carvalho de Melo * The high word (bits 16:31) are a bitmask of which engines classes 1619e6aff9f8SArnaldo Carvalho de Melo * are currently reading from the object. Multiple engines may be 1620c1737f2bSArnaldo Carvalho de Melo * reading from the object simultaneously. 1621c1737f2bSArnaldo Carvalho de Melo * 1622e6aff9f8SArnaldo Carvalho de Melo * The value of each engine class is the same as specified in the 16234dc24d7cSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. 1624e6aff9f8SArnaldo Carvalho de Melo * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 16254dc24d7cSArnaldo Carvalho de Melo * Some hardware may have parallel execution engines, e.g. multiple 16264dc24d7cSArnaldo Carvalho de Melo * media engines, which are mapped to the same class identifier and so 16274dc24d7cSArnaldo Carvalho de Melo * are not separately reported for busyness. 1628c1737f2bSArnaldo Carvalho de Melo * 1629c1737f2bSArnaldo Carvalho de Melo * Caveat emptor: 1630c1737f2bSArnaldo Carvalho de Melo * Only the boolean result of this query is reliable; that is whether 1631c1737f2bSArnaldo Carvalho de Melo * the object is idle or busy. The report of which engines are busy 1632c1737f2bSArnaldo Carvalho de Melo * should be only used as a heuristic. 1633c1737f2bSArnaldo Carvalho de Melo */ 1634c1737f2bSArnaldo Carvalho de Melo __u32 busy; 1635c1737f2bSArnaldo Carvalho de Melo }; 1636c1737f2bSArnaldo Carvalho de Melo 1637c1737f2bSArnaldo Carvalho de Melo /** 16384dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_caching - Set or get the caching for given object 16394dc24d7cSArnaldo Carvalho de Melo * handle. 1640c1737f2bSArnaldo Carvalho de Melo * 16414dc24d7cSArnaldo Carvalho de Melo * Allow userspace to control the GTT caching bits for a given object when the 16424dc24d7cSArnaldo Carvalho de Melo * object is later mapped through the ppGTT(or GGTT on older platforms lacking 16434dc24d7cSArnaldo Carvalho de Melo * ppGTT support, or if the object is used for scanout). Note that this might 16444dc24d7cSArnaldo Carvalho de Melo * require unbinding the object from the GTT first, if its current caching value 16454dc24d7cSArnaldo Carvalho de Melo * doesn't match. 1646c1737f2bSArnaldo Carvalho de Melo * 16474dc24d7cSArnaldo Carvalho de Melo * Note that this all changes on discrete platforms, starting from DG1, the 16484dc24d7cSArnaldo Carvalho de Melo * set/get caching is no longer supported, and is now rejected. Instead the CPU 16494dc24d7cSArnaldo Carvalho de Melo * caching attributes(WB vs WC) will become an immutable creation time property 16504dc24d7cSArnaldo Carvalho de Melo * for the object, along with the GTT caching level. For now we don't expose any 16514dc24d7cSArnaldo Carvalho de Melo * new uAPI for this, instead on DG1 this is all implicit, although this largely 16524dc24d7cSArnaldo Carvalho de Melo * shouldn't matter since DG1 is coherent by default(without any way of 16534dc24d7cSArnaldo Carvalho de Melo * controlling it). 1654c1737f2bSArnaldo Carvalho de Melo * 16554dc24d7cSArnaldo Carvalho de Melo * Implicit caching rules, starting from DG1: 16564dc24d7cSArnaldo Carvalho de Melo * 16574dc24d7cSArnaldo Carvalho de Melo * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 16584dc24d7cSArnaldo Carvalho de Melo * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 16594dc24d7cSArnaldo Carvalho de Melo * mapped as write-combined only. 16604dc24d7cSArnaldo Carvalho de Melo * 16614dc24d7cSArnaldo Carvalho de Melo * - Everything else is always allocated and mapped as write-back, with the 16624dc24d7cSArnaldo Carvalho de Melo * guarantee that everything is also coherent with the GPU. 16634dc24d7cSArnaldo Carvalho de Melo * 16644dc24d7cSArnaldo Carvalho de Melo * Note that this is likely to change in the future again, where we might need 16654dc24d7cSArnaldo Carvalho de Melo * more flexibility on future devices, so making this all explicit as part of a 16664dc24d7cSArnaldo Carvalho de Melo * new &drm_i915_gem_create_ext extension is probable. 16674dc24d7cSArnaldo Carvalho de Melo * 16684dc24d7cSArnaldo Carvalho de Melo * Side note: Part of the reason for this is that changing the at-allocation-time CPU 16694dc24d7cSArnaldo Carvalho de Melo * caching attributes for the pages might be required(and is expensive) if we 16704dc24d7cSArnaldo Carvalho de Melo * need to then CPU map the pages later with different caching attributes. This 16714dc24d7cSArnaldo Carvalho de Melo * inconsistent caching behaviour, while supported on x86, is not universally 16724dc24d7cSArnaldo Carvalho de Melo * supported on other architectures. So for simplicity we opt for setting 16734dc24d7cSArnaldo Carvalho de Melo * everything at creation time, whilst also making it immutable, on discrete 16744dc24d7cSArnaldo Carvalho de Melo * platforms. 1675c1737f2bSArnaldo Carvalho de Melo */ 1676c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_caching { 1677c1737f2bSArnaldo Carvalho de Melo /** 16784dc24d7cSArnaldo Carvalho de Melo * @handle: Handle of the buffer to set/get the caching level. 16794dc24d7cSArnaldo Carvalho de Melo */ 1680c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1681c1737f2bSArnaldo Carvalho de Melo 1682c1737f2bSArnaldo Carvalho de Melo /** 16834dc24d7cSArnaldo Carvalho de Melo * @caching: The GTT caching level to apply or possible return value. 1684c1737f2bSArnaldo Carvalho de Melo * 16854dc24d7cSArnaldo Carvalho de Melo * The supported @caching values: 16864dc24d7cSArnaldo Carvalho de Melo * 16874dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_NONE: 16884dc24d7cSArnaldo Carvalho de Melo * 16894dc24d7cSArnaldo Carvalho de Melo * GPU access is not coherent with CPU caches. Default for machines 16904dc24d7cSArnaldo Carvalho de Melo * without an LLC. This means manual flushing might be needed, if we 16914dc24d7cSArnaldo Carvalho de Melo * want GPU access to be coherent. 16924dc24d7cSArnaldo Carvalho de Melo * 16934dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_CACHED: 16944dc24d7cSArnaldo Carvalho de Melo * 16954dc24d7cSArnaldo Carvalho de Melo * GPU access is coherent with CPU caches and furthermore the data is 16964dc24d7cSArnaldo Carvalho de Melo * cached in last-level caches shared between CPU cores and the GPU GT. 16974dc24d7cSArnaldo Carvalho de Melo * 16984dc24d7cSArnaldo Carvalho de Melo * I915_CACHING_DISPLAY: 16994dc24d7cSArnaldo Carvalho de Melo * 17004dc24d7cSArnaldo Carvalho de Melo * Special GPU caching mode which is coherent with the scanout engines. 17014dc24d7cSArnaldo Carvalho de Melo * Transparently falls back to I915_CACHING_NONE on platforms where no 17024dc24d7cSArnaldo Carvalho de Melo * special cache mode (like write-through or gfdt flushing) is 17034dc24d7cSArnaldo Carvalho de Melo * available. The kernel automatically sets this mode when using a 17044dc24d7cSArnaldo Carvalho de Melo * buffer as a scanout target. Userspace can manually set this mode to 17054dc24d7cSArnaldo Carvalho de Melo * avoid a costly stall and clflush in the hotpath of drawing the first 17064dc24d7cSArnaldo Carvalho de Melo * frame. 17074dc24d7cSArnaldo Carvalho de Melo */ 17084dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_NONE 0 17094dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_CACHED 1 17104dc24d7cSArnaldo Carvalho de Melo #define I915_CACHING_DISPLAY 2 1711c1737f2bSArnaldo Carvalho de Melo __u32 caching; 1712c1737f2bSArnaldo Carvalho de Melo }; 1713c1737f2bSArnaldo Carvalho de Melo 1714c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_NONE 0 1715c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_X 1 1716c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_Y 2 171706cf00c4SArnaldo Carvalho de Melo /* 171806cf00c4SArnaldo Carvalho de Melo * Do not add new tiling types here. The I915_TILING_* values are for 171906cf00c4SArnaldo Carvalho de Melo * de-tiling fence registers that no longer exist on modern platforms. Although 172006cf00c4SArnaldo Carvalho de Melo * the hardware may support new types of tiling in general (e.g., Tile4), we 172106cf00c4SArnaldo Carvalho de Melo * do not need to add them to the uapi that is specific to now-defunct ioctls. 172206cf00c4SArnaldo Carvalho de Melo */ 1723c1737f2bSArnaldo Carvalho de Melo #define I915_TILING_LAST I915_TILING_Y 1724c1737f2bSArnaldo Carvalho de Melo 1725c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_NONE 0 1726c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9 1 1727c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10 2 1728c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_11 3 1729c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_11 4 1730c1737f2bSArnaldo Carvalho de Melo /* Not seen by userland */ 1731c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1732c1737f2bSArnaldo Carvalho de Melo /* Seen by userland. */ 1733c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_17 6 1734c1737f2bSArnaldo Carvalho de Melo #define I915_BIT_6_SWIZZLE_9_10_17 7 1735c1737f2bSArnaldo Carvalho de Melo 1736c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_set_tiling { 1737c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to have its tiling state updated */ 1738c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1739c1737f2bSArnaldo Carvalho de Melo 1740c1737f2bSArnaldo Carvalho de Melo /** 1741c1737f2bSArnaldo Carvalho de Melo * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1742c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1743c1737f2bSArnaldo Carvalho de Melo * 1744c1737f2bSArnaldo Carvalho de Melo * This value is to be set on request, and will be updated by the 1745c1737f2bSArnaldo Carvalho de Melo * kernel on successful return with the actual chosen tiling layout. 1746c1737f2bSArnaldo Carvalho de Melo * 1747c1737f2bSArnaldo Carvalho de Melo * The tiling mode may be demoted to I915_TILING_NONE when the system 1748c1737f2bSArnaldo Carvalho de Melo * has bit 6 swizzling that can't be managed correctly by GEM. 1749c1737f2bSArnaldo Carvalho de Melo * 1750c1737f2bSArnaldo Carvalho de Melo * Buffer contents become undefined when changing tiling_mode. 1751c1737f2bSArnaldo Carvalho de Melo */ 1752c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1753c1737f2bSArnaldo Carvalho de Melo 1754c1737f2bSArnaldo Carvalho de Melo /** 1755c1737f2bSArnaldo Carvalho de Melo * Stride in bytes for the object when in I915_TILING_X or 1756c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y. 1757c1737f2bSArnaldo Carvalho de Melo */ 1758c1737f2bSArnaldo Carvalho de Melo __u32 stride; 1759c1737f2bSArnaldo Carvalho de Melo 1760c1737f2bSArnaldo Carvalho de Melo /** 1761c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1762c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1763c1737f2bSArnaldo Carvalho de Melo */ 1764c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1765c1737f2bSArnaldo Carvalho de Melo }; 1766c1737f2bSArnaldo Carvalho de Melo 1767c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_tiling { 1768c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to get tiling state for. */ 1769c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1770c1737f2bSArnaldo Carvalho de Melo 1771c1737f2bSArnaldo Carvalho de Melo /** 1772c1737f2bSArnaldo Carvalho de Melo * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1773c1737f2bSArnaldo Carvalho de Melo * I915_TILING_Y). 1774c1737f2bSArnaldo Carvalho de Melo */ 1775c1737f2bSArnaldo Carvalho de Melo __u32 tiling_mode; 1776c1737f2bSArnaldo Carvalho de Melo 1777c1737f2bSArnaldo Carvalho de Melo /** 1778c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1779c1737f2bSArnaldo Carvalho de Melo * mmap mapping. 1780c1737f2bSArnaldo Carvalho de Melo */ 1781c1737f2bSArnaldo Carvalho de Melo __u32 swizzle_mode; 1782c1737f2bSArnaldo Carvalho de Melo 1783c1737f2bSArnaldo Carvalho de Melo /** 1784c1737f2bSArnaldo Carvalho de Melo * Returned address bit 6 swizzling required for CPU access through 1785c1737f2bSArnaldo Carvalho de Melo * mmap mapping whilst bound. 1786c1737f2bSArnaldo Carvalho de Melo */ 1787c1737f2bSArnaldo Carvalho de Melo __u32 phys_swizzle_mode; 1788c1737f2bSArnaldo Carvalho de Melo }; 1789c1737f2bSArnaldo Carvalho de Melo 1790c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_get_aperture { 1791c1737f2bSArnaldo Carvalho de Melo /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1792c1737f2bSArnaldo Carvalho de Melo __u64 aper_size; 1793c1737f2bSArnaldo Carvalho de Melo 1794c1737f2bSArnaldo Carvalho de Melo /** 1795c1737f2bSArnaldo Carvalho de Melo * Available space in the aperture used by i915_gem_execbuffer, in 1796c1737f2bSArnaldo Carvalho de Melo * bytes 1797c1737f2bSArnaldo Carvalho de Melo */ 1798c1737f2bSArnaldo Carvalho de Melo __u64 aper_available_size; 1799c1737f2bSArnaldo Carvalho de Melo }; 1800c1737f2bSArnaldo Carvalho de Melo 1801c1737f2bSArnaldo Carvalho de Melo struct drm_i915_get_pipe_from_crtc_id { 1802c1737f2bSArnaldo Carvalho de Melo /** ID of CRTC being requested **/ 1803c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1804c1737f2bSArnaldo Carvalho de Melo 1805c1737f2bSArnaldo Carvalho de Melo /** pipe of requested CRTC **/ 1806c1737f2bSArnaldo Carvalho de Melo __u32 pipe; 1807c1737f2bSArnaldo Carvalho de Melo }; 1808c1737f2bSArnaldo Carvalho de Melo 1809c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_WILLNEED 0 1810c1737f2bSArnaldo Carvalho de Melo #define I915_MADV_DONTNEED 1 1811c1737f2bSArnaldo Carvalho de Melo #define __I915_MADV_PURGED 2 /* internal state */ 1812c1737f2bSArnaldo Carvalho de Melo 1813c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_madvise { 1814c1737f2bSArnaldo Carvalho de Melo /** Handle of the buffer to change the backing store advice */ 1815c1737f2bSArnaldo Carvalho de Melo __u32 handle; 1816c1737f2bSArnaldo Carvalho de Melo 1817c1737f2bSArnaldo Carvalho de Melo /* Advice: either the buffer will be needed again in the near future, 1818c1737f2bSArnaldo Carvalho de Melo * or wont be and could be discarded under memory pressure. 1819c1737f2bSArnaldo Carvalho de Melo */ 1820c1737f2bSArnaldo Carvalho de Melo __u32 madv; 1821c1737f2bSArnaldo Carvalho de Melo 1822c1737f2bSArnaldo Carvalho de Melo /** Whether the backing store still exists. */ 1823c1737f2bSArnaldo Carvalho de Melo __u32 retained; 1824c1737f2bSArnaldo Carvalho de Melo }; 1825c1737f2bSArnaldo Carvalho de Melo 1826c1737f2bSArnaldo Carvalho de Melo /* flags */ 1827c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_TYPE_MASK 0xff 1828c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PLANAR 0x01 1829c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV_PACKED 0x02 1830c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB 0x03 1831c1737f2bSArnaldo Carvalho de Melo 1832c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DEPTH_MASK 0xff00 1833c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB24 0x1000 1834c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB16 0x2000 1835c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_RGB15 0x3000 1836c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV422 0x0100 1837c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV411 0x0200 1838c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV420 0x0300 1839c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_YUV410 0x0400 1840c1737f2bSArnaldo Carvalho de Melo 1841c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_SWAP_MASK 0xff0000 1842c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_NO_SWAP 0x000000 1843c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UV_SWAP 0x010000 1844c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_SWAP 0x020000 1845c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1846c1737f2bSArnaldo Carvalho de Melo 1847c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_FLAGS_MASK 0xff000000 1848c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_ENABLE 0x01000000 1849c1737f2bSArnaldo Carvalho de Melo 1850c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_put_image { 1851c1737f2bSArnaldo Carvalho de Melo /* various flags and src format description */ 1852c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1853c1737f2bSArnaldo Carvalho de Melo /* source picture description */ 1854c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1855c1737f2bSArnaldo Carvalho de Melo /* stride values and offsets are in bytes, buffer relative */ 1856c1737f2bSArnaldo Carvalho de Melo __u16 stride_Y; /* stride for packed formats */ 1857c1737f2bSArnaldo Carvalho de Melo __u16 stride_UV; 1858c1737f2bSArnaldo Carvalho de Melo __u32 offset_Y; /* offset for packet formats */ 1859c1737f2bSArnaldo Carvalho de Melo __u32 offset_U; 1860c1737f2bSArnaldo Carvalho de Melo __u32 offset_V; 1861c1737f2bSArnaldo Carvalho de Melo /* in pixels */ 1862c1737f2bSArnaldo Carvalho de Melo __u16 src_width; 1863c1737f2bSArnaldo Carvalho de Melo __u16 src_height; 1864c1737f2bSArnaldo Carvalho de Melo /* to compensate the scaling factors for partially covered surfaces */ 1865c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_width; 1866c1737f2bSArnaldo Carvalho de Melo __u16 src_scan_height; 1867c1737f2bSArnaldo Carvalho de Melo /* output crtc description */ 1868c1737f2bSArnaldo Carvalho de Melo __u32 crtc_id; 1869c1737f2bSArnaldo Carvalho de Melo __u16 dst_x; 1870c1737f2bSArnaldo Carvalho de Melo __u16 dst_y; 1871c1737f2bSArnaldo Carvalho de Melo __u16 dst_width; 1872c1737f2bSArnaldo Carvalho de Melo __u16 dst_height; 1873c1737f2bSArnaldo Carvalho de Melo }; 1874c1737f2bSArnaldo Carvalho de Melo 1875c1737f2bSArnaldo Carvalho de Melo /* flags */ 1876c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1877c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1878c1737f2bSArnaldo Carvalho de Melo #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1879c1737f2bSArnaldo Carvalho de Melo struct drm_intel_overlay_attrs { 1880c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1881c1737f2bSArnaldo Carvalho de Melo __u32 color_key; 1882c1737f2bSArnaldo Carvalho de Melo __s32 brightness; 1883c1737f2bSArnaldo Carvalho de Melo __u32 contrast; 1884c1737f2bSArnaldo Carvalho de Melo __u32 saturation; 1885c1737f2bSArnaldo Carvalho de Melo __u32 gamma0; 1886c1737f2bSArnaldo Carvalho de Melo __u32 gamma1; 1887c1737f2bSArnaldo Carvalho de Melo __u32 gamma2; 1888c1737f2bSArnaldo Carvalho de Melo __u32 gamma3; 1889c1737f2bSArnaldo Carvalho de Melo __u32 gamma4; 1890c1737f2bSArnaldo Carvalho de Melo __u32 gamma5; 1891c1737f2bSArnaldo Carvalho de Melo }; 1892c1737f2bSArnaldo Carvalho de Melo 1893c1737f2bSArnaldo Carvalho de Melo /* 1894c1737f2bSArnaldo Carvalho de Melo * Intel sprite handling 1895c1737f2bSArnaldo Carvalho de Melo * 1896c1737f2bSArnaldo Carvalho de Melo * Color keying works with a min/mask/max tuple. Both source and destination 1897c1737f2bSArnaldo Carvalho de Melo * color keying is allowed. 1898c1737f2bSArnaldo Carvalho de Melo * 1899c1737f2bSArnaldo Carvalho de Melo * Source keying: 1900c1737f2bSArnaldo Carvalho de Melo * Sprite pixels within the min & max values, masked against the color channels 1901c1737f2bSArnaldo Carvalho de Melo * specified in the mask field, will be transparent. All other pixels will 1902c1737f2bSArnaldo Carvalho de Melo * be displayed on top of the primary plane. For RGB surfaces, only the min 1903c1737f2bSArnaldo Carvalho de Melo * and mask fields will be used; ranged compares are not allowed. 1904c1737f2bSArnaldo Carvalho de Melo * 1905c1737f2bSArnaldo Carvalho de Melo * Destination keying: 1906c1737f2bSArnaldo Carvalho de Melo * Primary plane pixels that match the min value, masked against the color 1907c1737f2bSArnaldo Carvalho de Melo * channels specified in the mask field, will be replaced by corresponding 1908c1737f2bSArnaldo Carvalho de Melo * pixels from the sprite plane. 1909c1737f2bSArnaldo Carvalho de Melo * 1910c1737f2bSArnaldo Carvalho de Melo * Note that source & destination keying are exclusive; only one can be 1911c1737f2bSArnaldo Carvalho de Melo * active on a given plane. 1912c1737f2bSArnaldo Carvalho de Melo */ 1913c1737f2bSArnaldo Carvalho de Melo 191401f97511SArnaldo Carvalho de Melo #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 191501f97511SArnaldo Carvalho de Melo * flags==0 to disable colorkeying. 191601f97511SArnaldo Carvalho de Melo */ 1917c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_DESTINATION (1<<1) 1918c1737f2bSArnaldo Carvalho de Melo #define I915_SET_COLORKEY_SOURCE (1<<2) 1919c1737f2bSArnaldo Carvalho de Melo struct drm_intel_sprite_colorkey { 1920c1737f2bSArnaldo Carvalho de Melo __u32 plane_id; 1921c1737f2bSArnaldo Carvalho de Melo __u32 min_value; 1922c1737f2bSArnaldo Carvalho de Melo __u32 channel_mask; 1923c1737f2bSArnaldo Carvalho de Melo __u32 max_value; 1924c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1925c1737f2bSArnaldo Carvalho de Melo }; 1926c1737f2bSArnaldo Carvalho de Melo 1927c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_wait { 1928c1737f2bSArnaldo Carvalho de Melo /** Handle of BO we shall wait on */ 1929c1737f2bSArnaldo Carvalho de Melo __u32 bo_handle; 1930c1737f2bSArnaldo Carvalho de Melo __u32 flags; 1931c1737f2bSArnaldo Carvalho de Melo /** Number of nanoseconds to wait, Returns time remaining. */ 1932c1737f2bSArnaldo Carvalho de Melo __s64 timeout_ns; 1933c1737f2bSArnaldo Carvalho de Melo }; 1934c1737f2bSArnaldo Carvalho de Melo 1935c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_create { 1936e6aff9f8SArnaldo Carvalho de Melo __u32 ctx_id; /* output: id of new context*/ 1937c1737f2bSArnaldo Carvalho de Melo __u32 pad; 1938c1737f2bSArnaldo Carvalho de Melo }; 1939c1737f2bSArnaldo Carvalho de Melo 194054cd4cdeSArnaldo Carvalho de Melo /** 194154cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext - Structure for creating contexts. 194254cd4cdeSArnaldo Carvalho de Melo */ 1943e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_create_ext { 194454cd4cdeSArnaldo Carvalho de Melo /** @ctx_id: Id of the created context (output) */ 194554cd4cdeSArnaldo Carvalho de Melo __u32 ctx_id; 194654cd4cdeSArnaldo Carvalho de Melo 194754cd4cdeSArnaldo Carvalho de Melo /** 194854cd4cdeSArnaldo Carvalho de Melo * @flags: Supported flags are: 194954cd4cdeSArnaldo Carvalho de Melo * 195054cd4cdeSArnaldo Carvalho de Melo * I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS: 195154cd4cdeSArnaldo Carvalho de Melo * 195254cd4cdeSArnaldo Carvalho de Melo * Extensions may be appended to this structure and driver must check 195354cd4cdeSArnaldo Carvalho de Melo * for those. See @extensions. 195454cd4cdeSArnaldo Carvalho de Melo * 195554cd4cdeSArnaldo Carvalho de Melo * I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE 195654cd4cdeSArnaldo Carvalho de Melo * 195754cd4cdeSArnaldo Carvalho de Melo * Created context will have single timeline. 195854cd4cdeSArnaldo Carvalho de Melo */ 1959e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 1960e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 196195dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1962e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 196395dc663aSArnaldo Carvalho de Melo (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 196454cd4cdeSArnaldo Carvalho de Melo 196554cd4cdeSArnaldo Carvalho de Melo /** 196654cd4cdeSArnaldo Carvalho de Melo * @extensions: Zero-terminated chain of extensions. 196754cd4cdeSArnaldo Carvalho de Melo * 196854cd4cdeSArnaldo Carvalho de Melo * I915_CONTEXT_CREATE_EXT_SETPARAM: 196954cd4cdeSArnaldo Carvalho de Melo * Context parameter to set or query during context creation. 197054cd4cdeSArnaldo Carvalho de Melo * See struct drm_i915_gem_context_create_ext_setparam. 197154cd4cdeSArnaldo Carvalho de Melo * 197254cd4cdeSArnaldo Carvalho de Melo * I915_CONTEXT_CREATE_EXT_CLONE: 197354cd4cdeSArnaldo Carvalho de Melo * This extension has been removed. On the off chance someone somewhere 197454cd4cdeSArnaldo Carvalho de Melo * has attempted to use it, never re-use this extension number. 197554cd4cdeSArnaldo Carvalho de Melo */ 1976e6aff9f8SArnaldo Carvalho de Melo __u64 extensions; 197754cd4cdeSArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 197854cd4cdeSArnaldo Carvalho de Melo #define I915_CONTEXT_CREATE_EXT_CLONE 1 1979e6aff9f8SArnaldo Carvalho de Melo }; 1980e6aff9f8SArnaldo Carvalho de Melo 198154cd4cdeSArnaldo Carvalho de Melo /** 198254cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_context_param - Context parameter to set or query. 198354cd4cdeSArnaldo Carvalho de Melo */ 1984e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param { 198554cd4cdeSArnaldo Carvalho de Melo /** @ctx_id: Context id */ 1986e6aff9f8SArnaldo Carvalho de Melo __u32 ctx_id; 198754cd4cdeSArnaldo Carvalho de Melo 198854cd4cdeSArnaldo Carvalho de Melo /** @size: Size of the parameter @value */ 1989e6aff9f8SArnaldo Carvalho de Melo __u32 size; 199054cd4cdeSArnaldo Carvalho de Melo 199154cd4cdeSArnaldo Carvalho de Melo /** @param: Parameter to set or query */ 1992e6aff9f8SArnaldo Carvalho de Melo __u64 param; 1993e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 19944dc24d7cSArnaldo Carvalho de Melo /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance 19954dc24d7cSArnaldo Carvalho de Melo * someone somewhere has attempted to use it, never re-use this context 19964dc24d7cSArnaldo Carvalho de Melo * param number. 19974dc24d7cSArnaldo Carvalho de Melo */ 1998e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1999e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 2000e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 2001e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_BANNABLE 0x5 2002e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PRIORITY 0x6 2003e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 2004e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_DEFAULT_PRIORITY 0 2005e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 2006e6aff9f8SArnaldo Carvalho de Melo /* 2007e6aff9f8SArnaldo Carvalho de Melo * When using the following param, value should be a pointer to 2008e6aff9f8SArnaldo Carvalho de Melo * drm_i915_gem_context_param_sseu. 2009e6aff9f8SArnaldo Carvalho de Melo */ 2010e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_SSEU 0x7 2011e6aff9f8SArnaldo Carvalho de Melo 2012e6aff9f8SArnaldo Carvalho de Melo /* 2013e6aff9f8SArnaldo Carvalho de Melo * Not all clients may want to attempt automatic recover of a context after 2014e6aff9f8SArnaldo Carvalho de Melo * a hang (for example, some clients may only submit very small incremental 2015e6aff9f8SArnaldo Carvalho de Melo * batches relying on known logical state of previous batches which will never 2016e6aff9f8SArnaldo Carvalho de Melo * recover correctly and each attempt will hang), and so would prefer that 2017e6aff9f8SArnaldo Carvalho de Melo * the context is forever banned instead. 2018e6aff9f8SArnaldo Carvalho de Melo * 2019e6aff9f8SArnaldo Carvalho de Melo * If set to false (0), after a reset, subsequent (and in flight) rendering 2020e6aff9f8SArnaldo Carvalho de Melo * from this context is discarded, and the client will need to create a new 2021e6aff9f8SArnaldo Carvalho de Melo * context to use instead. 2022e6aff9f8SArnaldo Carvalho de Melo * 2023e6aff9f8SArnaldo Carvalho de Melo * If set to true (1), the kernel will automatically attempt to recover the 2024e6aff9f8SArnaldo Carvalho de Melo * context by skipping the hanging batch and executing the next batch starting 2025e6aff9f8SArnaldo Carvalho de Melo * from the default context state (discarding the incomplete logical context 2026e6aff9f8SArnaldo Carvalho de Melo * state lost due to the reset). 2027e6aff9f8SArnaldo Carvalho de Melo * 2028e6aff9f8SArnaldo Carvalho de Melo * On creation, all new contexts are marked as recoverable. 2029e6aff9f8SArnaldo Carvalho de Melo */ 2030e6aff9f8SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 203195dc663aSArnaldo Carvalho de Melo 203295dc663aSArnaldo Carvalho de Melo /* 203395dc663aSArnaldo Carvalho de Melo * The id of the associated virtual memory address space (ppGTT) of 203495dc663aSArnaldo Carvalho de Melo * this context. Can be retrieved and passed to another context 203595dc663aSArnaldo Carvalho de Melo * (on the same fd) for both to use the same ppGTT and so share 203695dc663aSArnaldo Carvalho de Melo * address layouts, and avoid reloading the page tables on context 203795dc663aSArnaldo Carvalho de Melo * switches between themselves. 203895dc663aSArnaldo Carvalho de Melo * 203995dc663aSArnaldo Carvalho de Melo * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 204095dc663aSArnaldo Carvalho de Melo */ 204195dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_VM 0x9 204295dc663aSArnaldo Carvalho de Melo 204395dc663aSArnaldo Carvalho de Melo /* 204495dc663aSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_ENGINES: 204595dc663aSArnaldo Carvalho de Melo * 204695dc663aSArnaldo Carvalho de Melo * Bind this context to operate on this subset of available engines. Henceforth, 204795dc663aSArnaldo Carvalho de Melo * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 204895dc663aSArnaldo Carvalho de Melo * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 204995dc663aSArnaldo Carvalho de Melo * and upwards. Slots 0...N are filled in using the specified (class, instance). 205095dc663aSArnaldo Carvalho de Melo * Use 205195dc663aSArnaldo Carvalho de Melo * engine_class: I915_ENGINE_CLASS_INVALID, 205295dc663aSArnaldo Carvalho de Melo * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 205395dc663aSArnaldo Carvalho de Melo * to specify a gap in the array that can be filled in later, e.g. by a 205495dc663aSArnaldo Carvalho de Melo * virtual engine used for load balancing. 205595dc663aSArnaldo Carvalho de Melo * 205695dc663aSArnaldo Carvalho de Melo * Setting the number of engines bound to the context to 0, by passing a zero 205795dc663aSArnaldo Carvalho de Melo * sized argument, will revert back to default settings. 205895dc663aSArnaldo Carvalho de Melo * 205995dc663aSArnaldo Carvalho de Melo * See struct i915_context_param_engines. 206095dc663aSArnaldo Carvalho de Melo * 206195dc663aSArnaldo Carvalho de Melo * Extensions: 206295dc663aSArnaldo Carvalho de Melo * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 206395dc663aSArnaldo Carvalho de Melo * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 206406cf00c4SArnaldo Carvalho de Melo * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT) 206595dc663aSArnaldo Carvalho de Melo */ 206695dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_ENGINES 0xa 20670b3fca6aSArnaldo Carvalho de Melo 20680b3fca6aSArnaldo Carvalho de Melo /* 20690b3fca6aSArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_PERSISTENCE: 20700b3fca6aSArnaldo Carvalho de Melo * 20710b3fca6aSArnaldo Carvalho de Melo * Allow the context and active rendering to survive the process until 20720b3fca6aSArnaldo Carvalho de Melo * completion. Persistence allows fire-and-forget clients to queue up a 20730b3fca6aSArnaldo Carvalho de Melo * bunch of work, hand the output over to a display server and then quit. 20740b3fca6aSArnaldo Carvalho de Melo * If the context is marked as not persistent, upon closing (either via 20750b3fca6aSArnaldo Carvalho de Melo * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure 20760b3fca6aSArnaldo Carvalho de Melo * or process termination), the context and any outstanding requests will be 20770b3fca6aSArnaldo Carvalho de Melo * cancelled (and exported fences for cancelled requests marked as -EIO). 20780b3fca6aSArnaldo Carvalho de Melo * 20790b3fca6aSArnaldo Carvalho de Melo * By default, new contexts allow persistence. 20800b3fca6aSArnaldo Carvalho de Melo */ 20810b3fca6aSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 208254a58ebcSArnaldo Carvalho de Melo 20834dc24d7cSArnaldo Carvalho de Melo /* This API has been removed. On the off chance someone somewhere has 20844dc24d7cSArnaldo Carvalho de Melo * attempted to use it, never re-use this context param number. 208554a58ebcSArnaldo Carvalho de Melo */ 208654a58ebcSArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_RINGSIZE 0xc 208706cf00c4SArnaldo Carvalho de Melo 208806cf00c4SArnaldo Carvalho de Melo /* 208906cf00c4SArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_PROTECTED_CONTENT: 209006cf00c4SArnaldo Carvalho de Melo * 209106cf00c4SArnaldo Carvalho de Melo * Mark that the context makes use of protected content, which will result 209206cf00c4SArnaldo Carvalho de Melo * in the context being invalidated when the protected content session is. 209306cf00c4SArnaldo Carvalho de Melo * Given that the protected content session is killed on suspend, the device 209406cf00c4SArnaldo Carvalho de Melo * is kept awake for the lifetime of a protected context, so the user should 209506cf00c4SArnaldo Carvalho de Melo * make sure to dispose of them once done. 209606cf00c4SArnaldo Carvalho de Melo * This flag can only be set at context creation time and, when set to true, 209706cf00c4SArnaldo Carvalho de Melo * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE 209806cf00c4SArnaldo Carvalho de Melo * to false. This flag can't be set to true in conjunction with setting the 209906cf00c4SArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example: 210006cf00c4SArnaldo Carvalho de Melo * 210106cf00c4SArnaldo Carvalho de Melo * .. code-block:: C 210206cf00c4SArnaldo Carvalho de Melo * 210306cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_protected = { 210406cf00c4SArnaldo Carvalho de Melo * .base = { 210506cf00c4SArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 210606cf00c4SArnaldo Carvalho de Melo * }, 210706cf00c4SArnaldo Carvalho de Melo * .param = { 210806cf00c4SArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT, 210906cf00c4SArnaldo Carvalho de Melo * .value = 1, 211006cf00c4SArnaldo Carvalho de Melo * } 211106cf00c4SArnaldo Carvalho de Melo * }; 211206cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_norecover = { 211306cf00c4SArnaldo Carvalho de Melo * .base = { 211406cf00c4SArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 211506cf00c4SArnaldo Carvalho de Melo * .next_extension = to_user_pointer(&p_protected), 211606cf00c4SArnaldo Carvalho de Melo * }, 211706cf00c4SArnaldo Carvalho de Melo * .param = { 211806cf00c4SArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_RECOVERABLE, 211906cf00c4SArnaldo Carvalho de Melo * .value = 0, 212006cf00c4SArnaldo Carvalho de Melo * } 212106cf00c4SArnaldo Carvalho de Melo * }; 212206cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext create = { 212306cf00c4SArnaldo Carvalho de Melo * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 212406cf00c4SArnaldo Carvalho de Melo * .extensions = to_user_pointer(&p_norecover); 212506cf00c4SArnaldo Carvalho de Melo * }; 212606cf00c4SArnaldo Carvalho de Melo * 212706cf00c4SArnaldo Carvalho de Melo * ctx_id = gem_context_create_ext(drm_fd, &create); 212806cf00c4SArnaldo Carvalho de Melo * 212906cf00c4SArnaldo Carvalho de Melo * In addition to the normal failure cases, setting this flag during context 213006cf00c4SArnaldo Carvalho de Melo * creation can result in the following errors: 213106cf00c4SArnaldo Carvalho de Melo * 213206cf00c4SArnaldo Carvalho de Melo * -ENODEV: feature not available 213306cf00c4SArnaldo Carvalho de Melo * -EPERM: trying to mark a recoverable or not bannable context as protected 2134*142256d2SArnaldo Carvalho de Melo * -ENXIO: A dependency such as a component driver or firmware is not yet 2135*142256d2SArnaldo Carvalho de Melo * loaded so user space may need to attempt again. Depending on the 2136*142256d2SArnaldo Carvalho de Melo * device, this error may be reported if protected context creation is 2137*142256d2SArnaldo Carvalho de Melo * attempted very early after kernel start because the internal timeout 2138*142256d2SArnaldo Carvalho de Melo * waiting for such dependencies is not guaranteed to be larger than 2139*142256d2SArnaldo Carvalho de Melo * required (numbers differ depending on system and kernel config): 2140*142256d2SArnaldo Carvalho de Melo * - ADL/RPL: dependencies may take up to 3 seconds from kernel start 2141*142256d2SArnaldo Carvalho de Melo * while context creation internal timeout is 250 milisecs 2142*142256d2SArnaldo Carvalho de Melo * - MTL: dependencies may take up to 8 seconds from kernel start 2143*142256d2SArnaldo Carvalho de Melo * while context creation internal timeout is 250 milisecs 2144*142256d2SArnaldo Carvalho de Melo * NOTE: such dependencies happen once, so a subsequent call to create a 2145*142256d2SArnaldo Carvalho de Melo * protected context after a prior successful call will not experience 2146*142256d2SArnaldo Carvalho de Melo * such timeouts and will not return -ENXIO (unless the driver is reloaded, 2147*142256d2SArnaldo Carvalho de Melo * or, depending on the device, resumes from a suspended state). 2148*142256d2SArnaldo Carvalho de Melo * -EIO: The firmware did not succeed in creating the protected context. 214906cf00c4SArnaldo Carvalho de Melo */ 215006cf00c4SArnaldo Carvalho de Melo #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd 2151e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 2152e6aff9f8SArnaldo Carvalho de Melo 215354cd4cdeSArnaldo Carvalho de Melo /** @value: Context parameter value to be set or queried */ 2154e6aff9f8SArnaldo Carvalho de Melo __u64 value; 2155e6aff9f8SArnaldo Carvalho de Melo }; 2156e6aff9f8SArnaldo Carvalho de Melo 21574a1cddeaSArnaldo Carvalho de Melo /* 2158e6aff9f8SArnaldo Carvalho de Melo * Context SSEU programming 2159e6aff9f8SArnaldo Carvalho de Melo * 2160e6aff9f8SArnaldo Carvalho de Melo * It may be necessary for either functional or performance reason to configure 2161e6aff9f8SArnaldo Carvalho de Melo * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 2162e6aff9f8SArnaldo Carvalho de Melo * Sub-slice/EU). 2163e6aff9f8SArnaldo Carvalho de Melo * 2164e6aff9f8SArnaldo Carvalho de Melo * This is done by configuring SSEU configuration using the below 2165e6aff9f8SArnaldo Carvalho de Melo * @struct drm_i915_gem_context_param_sseu for every supported engine which 2166e6aff9f8SArnaldo Carvalho de Melo * userspace intends to use. 2167e6aff9f8SArnaldo Carvalho de Melo * 2168e6aff9f8SArnaldo Carvalho de Melo * Not all GPUs or engines support this functionality in which case an error 2169e6aff9f8SArnaldo Carvalho de Melo * code -ENODEV will be returned. 2170e6aff9f8SArnaldo Carvalho de Melo * 2171e6aff9f8SArnaldo Carvalho de Melo * Also, flexibility of possible SSEU configuration permutations varies between 2172e6aff9f8SArnaldo Carvalho de Melo * GPU generations and software imposed limitations. Requesting such a 2173e6aff9f8SArnaldo Carvalho de Melo * combination will return an error code of -EINVAL. 2174e6aff9f8SArnaldo Carvalho de Melo * 2175e6aff9f8SArnaldo Carvalho de Melo * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 2176e6aff9f8SArnaldo Carvalho de Melo * favour of a single global setting. 2177e6aff9f8SArnaldo Carvalho de Melo */ 2178e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param_sseu { 2179e6aff9f8SArnaldo Carvalho de Melo /* 2180e6aff9f8SArnaldo Carvalho de Melo * Engine class & instance to be configured or queried. 2181e6aff9f8SArnaldo Carvalho de Melo */ 2182e6aff9f8SArnaldo Carvalho de Melo struct i915_engine_class_instance engine; 2183e6aff9f8SArnaldo Carvalho de Melo 2184e6aff9f8SArnaldo Carvalho de Melo /* 218595dc663aSArnaldo Carvalho de Melo * Unknown flags must be cleared to zero. 2186e6aff9f8SArnaldo Carvalho de Melo */ 2187e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 218895dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 2189e6aff9f8SArnaldo Carvalho de Melo 2190e6aff9f8SArnaldo Carvalho de Melo /* 2191e6aff9f8SArnaldo Carvalho de Melo * Mask of slices to enable for the context. Valid values are a subset 2192e6aff9f8SArnaldo Carvalho de Melo * of the bitmask value returned for I915_PARAM_SLICE_MASK. 2193e6aff9f8SArnaldo Carvalho de Melo */ 2194e6aff9f8SArnaldo Carvalho de Melo __u64 slice_mask; 2195e6aff9f8SArnaldo Carvalho de Melo 2196e6aff9f8SArnaldo Carvalho de Melo /* 2197e6aff9f8SArnaldo Carvalho de Melo * Mask of subslices to enable for the context. Valid values are a 2198e6aff9f8SArnaldo Carvalho de Melo * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 2199e6aff9f8SArnaldo Carvalho de Melo */ 2200e6aff9f8SArnaldo Carvalho de Melo __u64 subslice_mask; 2201e6aff9f8SArnaldo Carvalho de Melo 2202e6aff9f8SArnaldo Carvalho de Melo /* 2203e6aff9f8SArnaldo Carvalho de Melo * Minimum/Maximum number of EUs to enable per subslice for the 2204e6aff9f8SArnaldo Carvalho de Melo * context. min_eus_per_subslice must be inferior or equal to 2205e6aff9f8SArnaldo Carvalho de Melo * max_eus_per_subslice. 2206e6aff9f8SArnaldo Carvalho de Melo */ 2207e6aff9f8SArnaldo Carvalho de Melo __u16 min_eus_per_subslice; 2208e6aff9f8SArnaldo Carvalho de Melo __u16 max_eus_per_subslice; 2209e6aff9f8SArnaldo Carvalho de Melo 2210e6aff9f8SArnaldo Carvalho de Melo /* 2211e6aff9f8SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 2212e6aff9f8SArnaldo Carvalho de Melo */ 2213e6aff9f8SArnaldo Carvalho de Melo __u32 rsvd; 2214e6aff9f8SArnaldo Carvalho de Melo }; 2215e6aff9f8SArnaldo Carvalho de Melo 22164dc24d7cSArnaldo Carvalho de Melo /** 22174dc24d7cSArnaldo Carvalho de Melo * DOC: Virtual Engine uAPI 22184dc24d7cSArnaldo Carvalho de Melo * 22194dc24d7cSArnaldo Carvalho de Melo * Virtual engine is a concept where userspace is able to configure a set of 22204dc24d7cSArnaldo Carvalho de Melo * physical engines, submit a batch buffer, and let the driver execute it on any 22214dc24d7cSArnaldo Carvalho de Melo * engine from the set as it sees fit. 22224dc24d7cSArnaldo Carvalho de Melo * 22234dc24d7cSArnaldo Carvalho de Melo * This is primarily useful on parts which have multiple instances of a same 22244dc24d7cSArnaldo Carvalho de Melo * class engine, like for example GT3+ Skylake parts with their two VCS engines. 22254dc24d7cSArnaldo Carvalho de Melo * 22264dc24d7cSArnaldo Carvalho de Melo * For instance userspace can enumerate all engines of a certain class using the 22274dc24d7cSArnaldo Carvalho de Melo * previously described `Engine Discovery uAPI`_. After that userspace can 22284dc24d7cSArnaldo Carvalho de Melo * create a GEM context with a placeholder slot for the virtual engine (using 22294dc24d7cSArnaldo Carvalho de Melo * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class 22304dc24d7cSArnaldo Carvalho de Melo * and instance respectively) and finally using the 22314dc24d7cSArnaldo Carvalho de Melo * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in 22324dc24d7cSArnaldo Carvalho de Melo * the same reserved slot. 22334dc24d7cSArnaldo Carvalho de Melo * 22344dc24d7cSArnaldo Carvalho de Melo * Example of creating a virtual engine and submitting a batch buffer to it: 22354dc24d7cSArnaldo Carvalho de Melo * 22364dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 22374dc24d7cSArnaldo Carvalho de Melo * 22384dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { 22394dc24d7cSArnaldo Carvalho de Melo * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, 22404dc24d7cSArnaldo Carvalho de Melo * .engine_index = 0, // Place this virtual engine into engine map slot 0 22414dc24d7cSArnaldo Carvalho de Melo * .num_siblings = 2, 22424dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, 22434dc24d7cSArnaldo Carvalho de Melo * { I915_ENGINE_CLASS_VIDEO, 1 }, }, 22444dc24d7cSArnaldo Carvalho de Melo * }; 22454dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { 22464dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_INVALID, 22474dc24d7cSArnaldo Carvalho de Melo * I915_ENGINE_CLASS_INVALID_NONE } }, 22484dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension 22494dc24d7cSArnaldo Carvalho de Melo * }; 22504dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_engines = { 22514dc24d7cSArnaldo Carvalho de Melo * .base = { 22524dc24d7cSArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 22534dc24d7cSArnaldo Carvalho de Melo * }, 22544dc24d7cSArnaldo Carvalho de Melo * .param = { 22554dc24d7cSArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_ENGINES, 22564dc24d7cSArnaldo Carvalho de Melo * .value = to_user_pointer(&engines), 22574dc24d7cSArnaldo Carvalho de Melo * .size = sizeof(engines), 22584dc24d7cSArnaldo Carvalho de Melo * }, 22594dc24d7cSArnaldo Carvalho de Melo * }; 22604dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext create = { 22614dc24d7cSArnaldo Carvalho de Melo * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 22624dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&p_engines); 22634dc24d7cSArnaldo Carvalho de Melo * }; 22644dc24d7cSArnaldo Carvalho de Melo * 22654dc24d7cSArnaldo Carvalho de Melo * ctx_id = gem_context_create_ext(drm_fd, &create); 22664dc24d7cSArnaldo Carvalho de Melo * 22674dc24d7cSArnaldo Carvalho de Melo * // Now we have created a GEM context with its engine map containing a 22684dc24d7cSArnaldo Carvalho de Melo * // single virtual engine. Submissions to this slot can go either to 22694dc24d7cSArnaldo Carvalho de Melo * // vcs0 or vcs1, depending on the load balancing algorithm used inside 22704dc24d7cSArnaldo Carvalho de Melo * // the driver. The load balancing is dynamic from one batch buffer to 22714dc24d7cSArnaldo Carvalho de Melo * // another and transparent to userspace. 22724dc24d7cSArnaldo Carvalho de Melo * 22734dc24d7cSArnaldo Carvalho de Melo * ... 22744dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 22754dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 0; // Submits to index 0 which is the virtual engine 22764dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 22774dc24d7cSArnaldo Carvalho de Melo */ 22784dc24d7cSArnaldo Carvalho de Melo 227995dc663aSArnaldo Carvalho de Melo /* 228095dc663aSArnaldo Carvalho de Melo * i915_context_engines_load_balance: 228195dc663aSArnaldo Carvalho de Melo * 228295dc663aSArnaldo Carvalho de Melo * Enable load balancing across this set of engines. 228395dc663aSArnaldo Carvalho de Melo * 228495dc663aSArnaldo Carvalho de Melo * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 228595dc663aSArnaldo Carvalho de Melo * used will proxy the execbuffer request onto one of the set of engines 228695dc663aSArnaldo Carvalho de Melo * in such a way as to distribute the load evenly across the set. 228795dc663aSArnaldo Carvalho de Melo * 228895dc663aSArnaldo Carvalho de Melo * The set of engines must be compatible (e.g. the same HW class) as they 228995dc663aSArnaldo Carvalho de Melo * will share the same logical GPU context and ring. 229095dc663aSArnaldo Carvalho de Melo * 229195dc663aSArnaldo Carvalho de Melo * To intermix rendering with the virtual engine and direct rendering onto 229295dc663aSArnaldo Carvalho de Melo * the backing engines (bypassing the load balancing proxy), the context must 229395dc663aSArnaldo Carvalho de Melo * be defined to use a single timeline for all engines. 229495dc663aSArnaldo Carvalho de Melo */ 229595dc663aSArnaldo Carvalho de Melo struct i915_context_engines_load_balance { 229695dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; 229795dc663aSArnaldo Carvalho de Melo 229895dc663aSArnaldo Carvalho de Melo __u16 engine_index; 229995dc663aSArnaldo Carvalho de Melo __u16 num_siblings; 230095dc663aSArnaldo Carvalho de Melo __u32 flags; /* all undefined flags must be zero */ 230195dc663aSArnaldo Carvalho de Melo 230295dc663aSArnaldo Carvalho de Melo __u64 mbz64; /* reserved for future use; must be zero */ 230395dc663aSArnaldo Carvalho de Melo 230494dfc73eSGustavo A. R. Silva struct i915_engine_class_instance engines[]; 230595dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 230695dc663aSArnaldo Carvalho de Melo 230795dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 230895dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; \ 230995dc663aSArnaldo Carvalho de Melo __u16 engine_index; \ 231095dc663aSArnaldo Carvalho de Melo __u16 num_siblings; \ 231195dc663aSArnaldo Carvalho de Melo __u32 flags; \ 231295dc663aSArnaldo Carvalho de Melo __u64 mbz64; \ 231395dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 231495dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 231595dc663aSArnaldo Carvalho de Melo 231695dc663aSArnaldo Carvalho de Melo /* 231795dc663aSArnaldo Carvalho de Melo * i915_context_engines_bond: 231895dc663aSArnaldo Carvalho de Melo * 231995dc663aSArnaldo Carvalho de Melo * Constructed bonded pairs for execution within a virtual engine. 232095dc663aSArnaldo Carvalho de Melo * 232195dc663aSArnaldo Carvalho de Melo * All engines are equal, but some are more equal than others. Given 232295dc663aSArnaldo Carvalho de Melo * the distribution of resources in the HW, it may be preferable to run 232395dc663aSArnaldo Carvalho de Melo * a request on a given subset of engines in parallel to a request on a 232495dc663aSArnaldo Carvalho de Melo * specific engine. We enable this selection of engines within a virtual 232595dc663aSArnaldo Carvalho de Melo * engine by specifying bonding pairs, for any given master engine we will 232695dc663aSArnaldo Carvalho de Melo * only execute on one of the corresponding siblings within the virtual engine. 232795dc663aSArnaldo Carvalho de Melo * 232895dc663aSArnaldo Carvalho de Melo * To execute a request in parallel on the master engine and a sibling requires 232995dc663aSArnaldo Carvalho de Melo * coordination with a I915_EXEC_FENCE_SUBMIT. 233095dc663aSArnaldo Carvalho de Melo */ 233195dc663aSArnaldo Carvalho de Melo struct i915_context_engines_bond { 233295dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; 233395dc663aSArnaldo Carvalho de Melo 233495dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance master; 233595dc663aSArnaldo Carvalho de Melo 233695dc663aSArnaldo Carvalho de Melo __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 233795dc663aSArnaldo Carvalho de Melo __u16 num_bonds; 233895dc663aSArnaldo Carvalho de Melo 233995dc663aSArnaldo Carvalho de Melo __u64 flags; /* all undefined flags must be zero */ 234095dc663aSArnaldo Carvalho de Melo __u64 mbz64[4]; /* reserved for future use; must be zero */ 234195dc663aSArnaldo Carvalho de Melo 234294dfc73eSGustavo A. R. Silva struct i915_engine_class_instance engines[]; 234395dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 234495dc663aSArnaldo Carvalho de Melo 234595dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 234695dc663aSArnaldo Carvalho de Melo struct i915_user_extension base; \ 234795dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance master; \ 234895dc663aSArnaldo Carvalho de Melo __u16 virtual_index; \ 234995dc663aSArnaldo Carvalho de Melo __u16 num_bonds; \ 235095dc663aSArnaldo Carvalho de Melo __u64 flags; \ 235195dc663aSArnaldo Carvalho de Melo __u64 mbz64[4]; \ 235295dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 235395dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 235495dc663aSArnaldo Carvalho de Melo 23554dc24d7cSArnaldo Carvalho de Melo /** 235606cf00c4SArnaldo Carvalho de Melo * struct i915_context_engines_parallel_submit - Configure engine for 235706cf00c4SArnaldo Carvalho de Melo * parallel submission. 235806cf00c4SArnaldo Carvalho de Melo * 235906cf00c4SArnaldo Carvalho de Melo * Setup a slot in the context engine map to allow multiple BBs to be submitted 236006cf00c4SArnaldo Carvalho de Melo * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU 236106cf00c4SArnaldo Carvalho de Melo * in parallel. Multiple hardware contexts are created internally in the i915 to 236206cf00c4SArnaldo Carvalho de Melo * run these BBs. Once a slot is configured for N BBs only N BBs can be 236306cf00c4SArnaldo Carvalho de Melo * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user 236406cf00c4SArnaldo Carvalho de Melo * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how 236506cf00c4SArnaldo Carvalho de Melo * many BBs there are based on the slot's configuration. The N BBs are the last 236606cf00c4SArnaldo Carvalho de Melo * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. 236706cf00c4SArnaldo Carvalho de Melo * 236806cf00c4SArnaldo Carvalho de Melo * The default placement behavior is to create implicit bonds between each 236906cf00c4SArnaldo Carvalho de Melo * context if each context maps to more than 1 physical engine (e.g. context is 237006cf00c4SArnaldo Carvalho de Melo * a virtual engine). Also we only allow contexts of same engine class and these 237106cf00c4SArnaldo Carvalho de Melo * contexts must be in logically contiguous order. Examples of the placement 237206cf00c4SArnaldo Carvalho de Melo * behavior are described below. Lastly, the default is to not allow BBs to be 237306cf00c4SArnaldo Carvalho de Melo * preempted mid-batch. Rather insert coordinated preemption points on all 237406cf00c4SArnaldo Carvalho de Melo * hardware contexts between each set of BBs. Flags could be added in the future 237506cf00c4SArnaldo Carvalho de Melo * to change both of these default behaviors. 237606cf00c4SArnaldo Carvalho de Melo * 237706cf00c4SArnaldo Carvalho de Melo * Returns -EINVAL if hardware context placement configuration is invalid or if 237806cf00c4SArnaldo Carvalho de Melo * the placement configuration isn't supported on the platform / submission 237906cf00c4SArnaldo Carvalho de Melo * interface. 238006cf00c4SArnaldo Carvalho de Melo * Returns -ENODEV if extension isn't supported on the platform / submission 238106cf00c4SArnaldo Carvalho de Melo * interface. 238206cf00c4SArnaldo Carvalho de Melo * 238306cf00c4SArnaldo Carvalho de Melo * .. code-block:: none 238406cf00c4SArnaldo Carvalho de Melo * 238506cf00c4SArnaldo Carvalho de Melo * Examples syntax: 238606cf00c4SArnaldo Carvalho de Melo * CS[X] = generic engine of same class, logical instance X 238706cf00c4SArnaldo Carvalho de Melo * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE 238806cf00c4SArnaldo Carvalho de Melo * 238906cf00c4SArnaldo Carvalho de Melo * Example 1 pseudo code: 239006cf00c4SArnaldo Carvalho de Melo * set_engines(INVALID) 239106cf00c4SArnaldo Carvalho de Melo * set_parallel(engine_index=0, width=2, num_siblings=1, 239206cf00c4SArnaldo Carvalho de Melo * engines=CS[0],CS[1]) 239306cf00c4SArnaldo Carvalho de Melo * 239406cf00c4SArnaldo Carvalho de Melo * Results in the following valid placement: 239506cf00c4SArnaldo Carvalho de Melo * CS[0], CS[1] 239606cf00c4SArnaldo Carvalho de Melo * 239706cf00c4SArnaldo Carvalho de Melo * Example 2 pseudo code: 239806cf00c4SArnaldo Carvalho de Melo * set_engines(INVALID) 239906cf00c4SArnaldo Carvalho de Melo * set_parallel(engine_index=0, width=2, num_siblings=2, 240006cf00c4SArnaldo Carvalho de Melo * engines=CS[0],CS[2],CS[1],CS[3]) 240106cf00c4SArnaldo Carvalho de Melo * 240206cf00c4SArnaldo Carvalho de Melo * Results in the following valid placements: 240306cf00c4SArnaldo Carvalho de Melo * CS[0], CS[1] 240406cf00c4SArnaldo Carvalho de Melo * CS[2], CS[3] 240506cf00c4SArnaldo Carvalho de Melo * 240606cf00c4SArnaldo Carvalho de Melo * This can be thought of as two virtual engines, each containing two 240706cf00c4SArnaldo Carvalho de Melo * engines thereby making a 2D array. However, there are bonds tying the 240806cf00c4SArnaldo Carvalho de Melo * entries together and placing restrictions on how they can be scheduled. 240906cf00c4SArnaldo Carvalho de Melo * Specifically, the scheduler can choose only vertical columns from the 2D 241006cf00c4SArnaldo Carvalho de Melo * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the 241106cf00c4SArnaldo Carvalho de Melo * scheduler wants to submit to CS[0], it must also choose CS[1] and vice 241206cf00c4SArnaldo Carvalho de Melo * versa. Same for CS[2] requires also using CS[3]. 241306cf00c4SArnaldo Carvalho de Melo * VE[0] = CS[0], CS[2] 241406cf00c4SArnaldo Carvalho de Melo * VE[1] = CS[1], CS[3] 241506cf00c4SArnaldo Carvalho de Melo * 241606cf00c4SArnaldo Carvalho de Melo * Example 3 pseudo code: 241706cf00c4SArnaldo Carvalho de Melo * set_engines(INVALID) 241806cf00c4SArnaldo Carvalho de Melo * set_parallel(engine_index=0, width=2, num_siblings=2, 241906cf00c4SArnaldo Carvalho de Melo * engines=CS[0],CS[1],CS[1],CS[3]) 242006cf00c4SArnaldo Carvalho de Melo * 242106cf00c4SArnaldo Carvalho de Melo * Results in the following valid and invalid placements: 242206cf00c4SArnaldo Carvalho de Melo * CS[0], CS[1] 242306cf00c4SArnaldo Carvalho de Melo * CS[1], CS[3] - Not logically contiguous, return -EINVAL 242406cf00c4SArnaldo Carvalho de Melo */ 242506cf00c4SArnaldo Carvalho de Melo struct i915_context_engines_parallel_submit { 242606cf00c4SArnaldo Carvalho de Melo /** 242706cf00c4SArnaldo Carvalho de Melo * @base: base user extension. 242806cf00c4SArnaldo Carvalho de Melo */ 242906cf00c4SArnaldo Carvalho de Melo struct i915_user_extension base; 243006cf00c4SArnaldo Carvalho de Melo 243106cf00c4SArnaldo Carvalho de Melo /** 243206cf00c4SArnaldo Carvalho de Melo * @engine_index: slot for parallel engine 243306cf00c4SArnaldo Carvalho de Melo */ 243406cf00c4SArnaldo Carvalho de Melo __u16 engine_index; 243506cf00c4SArnaldo Carvalho de Melo 243606cf00c4SArnaldo Carvalho de Melo /** 243706cf00c4SArnaldo Carvalho de Melo * @width: number of contexts per parallel engine or in other words the 243806cf00c4SArnaldo Carvalho de Melo * number of batches in each submission 243906cf00c4SArnaldo Carvalho de Melo */ 244006cf00c4SArnaldo Carvalho de Melo __u16 width; 244106cf00c4SArnaldo Carvalho de Melo 244206cf00c4SArnaldo Carvalho de Melo /** 244306cf00c4SArnaldo Carvalho de Melo * @num_siblings: number of siblings per context or in other words the 244406cf00c4SArnaldo Carvalho de Melo * number of possible placements for each submission 244506cf00c4SArnaldo Carvalho de Melo */ 244606cf00c4SArnaldo Carvalho de Melo __u16 num_siblings; 244706cf00c4SArnaldo Carvalho de Melo 244806cf00c4SArnaldo Carvalho de Melo /** 244906cf00c4SArnaldo Carvalho de Melo * @mbz16: reserved for future use; must be zero 245006cf00c4SArnaldo Carvalho de Melo */ 245106cf00c4SArnaldo Carvalho de Melo __u16 mbz16; 245206cf00c4SArnaldo Carvalho de Melo 245306cf00c4SArnaldo Carvalho de Melo /** 245406cf00c4SArnaldo Carvalho de Melo * @flags: all undefined flags must be zero, currently not defined flags 245506cf00c4SArnaldo Carvalho de Melo */ 245606cf00c4SArnaldo Carvalho de Melo __u64 flags; 245706cf00c4SArnaldo Carvalho de Melo 245806cf00c4SArnaldo Carvalho de Melo /** 245906cf00c4SArnaldo Carvalho de Melo * @mbz64: reserved for future use; must be zero 246006cf00c4SArnaldo Carvalho de Melo */ 246106cf00c4SArnaldo Carvalho de Melo __u64 mbz64[3]; 246206cf00c4SArnaldo Carvalho de Melo 246306cf00c4SArnaldo Carvalho de Melo /** 246406cf00c4SArnaldo Carvalho de Melo * @engines: 2-d array of engine instances to configure parallel engine 246506cf00c4SArnaldo Carvalho de Melo * 246606cf00c4SArnaldo Carvalho de Melo * length = width (i) * num_siblings (j) 246706cf00c4SArnaldo Carvalho de Melo * index = j + i * num_siblings 246806cf00c4SArnaldo Carvalho de Melo */ 246994dfc73eSGustavo A. R. Silva struct i915_engine_class_instance engines[]; 247006cf00c4SArnaldo Carvalho de Melo 247106cf00c4SArnaldo Carvalho de Melo } __packed; 247206cf00c4SArnaldo Carvalho de Melo 247306cf00c4SArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \ 247406cf00c4SArnaldo Carvalho de Melo struct i915_user_extension base; \ 247506cf00c4SArnaldo Carvalho de Melo __u16 engine_index; \ 247606cf00c4SArnaldo Carvalho de Melo __u16 width; \ 247706cf00c4SArnaldo Carvalho de Melo __u16 num_siblings; \ 247806cf00c4SArnaldo Carvalho de Melo __u16 mbz16; \ 247906cf00c4SArnaldo Carvalho de Melo __u64 flags; \ 248006cf00c4SArnaldo Carvalho de Melo __u64 mbz64[3]; \ 248106cf00c4SArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 248206cf00c4SArnaldo Carvalho de Melo } __attribute__((packed)) name__ 248306cf00c4SArnaldo Carvalho de Melo 248406cf00c4SArnaldo Carvalho de Melo /** 24854dc24d7cSArnaldo Carvalho de Melo * DOC: Context Engine Map uAPI 24864dc24d7cSArnaldo Carvalho de Melo * 24874dc24d7cSArnaldo Carvalho de Melo * Context engine map is a new way of addressing engines when submitting batch- 24884dc24d7cSArnaldo Carvalho de Melo * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` 24894dc24d7cSArnaldo Carvalho de Melo * inside the flags field of `struct drm_i915_gem_execbuffer2`. 24904dc24d7cSArnaldo Carvalho de Melo * 24914dc24d7cSArnaldo Carvalho de Melo * To use it created GEM contexts need to be configured with a list of engines 24924dc24d7cSArnaldo Carvalho de Melo * the user is intending to submit to. This is accomplished using the 24934dc24d7cSArnaldo Carvalho de Melo * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct 24944dc24d7cSArnaldo Carvalho de Melo * i915_context_param_engines`. 24954dc24d7cSArnaldo Carvalho de Melo * 24964dc24d7cSArnaldo Carvalho de Melo * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the 24974dc24d7cSArnaldo Carvalho de Melo * configured map. 24984dc24d7cSArnaldo Carvalho de Melo * 24994dc24d7cSArnaldo Carvalho de Melo * Example of creating such context and submitting against it: 25004dc24d7cSArnaldo Carvalho de Melo * 25014dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 25024dc24d7cSArnaldo Carvalho de Melo * 25034dc24d7cSArnaldo Carvalho de Melo * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { 25044dc24d7cSArnaldo Carvalho de Melo * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, 25054dc24d7cSArnaldo Carvalho de Melo * { I915_ENGINE_CLASS_COPY, 0 } } 25064dc24d7cSArnaldo Carvalho de Melo * }; 25074dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam p_engines = { 25084dc24d7cSArnaldo Carvalho de Melo * .base = { 25094dc24d7cSArnaldo Carvalho de Melo * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 25104dc24d7cSArnaldo Carvalho de Melo * }, 25114dc24d7cSArnaldo Carvalho de Melo * .param = { 25124dc24d7cSArnaldo Carvalho de Melo * .param = I915_CONTEXT_PARAM_ENGINES, 25134dc24d7cSArnaldo Carvalho de Melo * .value = to_user_pointer(&engines), 25144dc24d7cSArnaldo Carvalho de Melo * .size = sizeof(engines), 25154dc24d7cSArnaldo Carvalho de Melo * }, 25164dc24d7cSArnaldo Carvalho de Melo * }; 25174dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext create = { 25184dc24d7cSArnaldo Carvalho de Melo * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 25194dc24d7cSArnaldo Carvalho de Melo * .extensions = to_user_pointer(&p_engines); 25204dc24d7cSArnaldo Carvalho de Melo * }; 25214dc24d7cSArnaldo Carvalho de Melo * 25224dc24d7cSArnaldo Carvalho de Melo * ctx_id = gem_context_create_ext(drm_fd, &create); 25234dc24d7cSArnaldo Carvalho de Melo * 25244dc24d7cSArnaldo Carvalho de Melo * // We have now created a GEM context with two engines in the map: 25254dc24d7cSArnaldo Carvalho de Melo * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines 25264dc24d7cSArnaldo Carvalho de Melo * // will not be accessible from this context. 25274dc24d7cSArnaldo Carvalho de Melo * 25284dc24d7cSArnaldo Carvalho de Melo * ... 25294dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 25304dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context 25314dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 25324dc24d7cSArnaldo Carvalho de Melo * 25334dc24d7cSArnaldo Carvalho de Melo * ... 25344dc24d7cSArnaldo Carvalho de Melo * execbuf.rsvd1 = ctx_id; 25354dc24d7cSArnaldo Carvalho de Melo * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context 25364dc24d7cSArnaldo Carvalho de Melo * gem_execbuf(drm_fd, &execbuf); 25374dc24d7cSArnaldo Carvalho de Melo */ 25384dc24d7cSArnaldo Carvalho de Melo 253995dc663aSArnaldo Carvalho de Melo struct i915_context_param_engines { 254095dc663aSArnaldo Carvalho de Melo __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 254195dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 254295dc663aSArnaldo Carvalho de Melo #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 254306cf00c4SArnaldo Carvalho de Melo #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ 2544e7ec3a24SYanteng Si struct i915_engine_class_instance engines[]; 254595dc663aSArnaldo Carvalho de Melo } __attribute__((packed)); 254695dc663aSArnaldo Carvalho de Melo 254795dc663aSArnaldo Carvalho de Melo #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 254895dc663aSArnaldo Carvalho de Melo __u64 extensions; \ 254995dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engines[N__]; \ 255095dc663aSArnaldo Carvalho de Melo } __attribute__((packed)) name__ 255195dc663aSArnaldo Carvalho de Melo 255254cd4cdeSArnaldo Carvalho de Melo /** 255354cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_context_create_ext_setparam - Context parameter 255454cd4cdeSArnaldo Carvalho de Melo * to set or query during context creation. 255554cd4cdeSArnaldo Carvalho de Melo */ 2556e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_create_ext_setparam { 255754cd4cdeSArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 2558e6aff9f8SArnaldo Carvalho de Melo struct i915_user_extension base; 255954cd4cdeSArnaldo Carvalho de Melo 256054cd4cdeSArnaldo Carvalho de Melo /** 256154cd4cdeSArnaldo Carvalho de Melo * @param: Context parameter to set or query. 256254cd4cdeSArnaldo Carvalho de Melo * See struct drm_i915_gem_context_param. 256354cd4cdeSArnaldo Carvalho de Melo */ 2564e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_context_param param; 2565e6aff9f8SArnaldo Carvalho de Melo }; 2566e6aff9f8SArnaldo Carvalho de Melo 2567c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_context_destroy { 2568c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 2569c1737f2bSArnaldo Carvalho de Melo __u32 pad; 2570c1737f2bSArnaldo Carvalho de Melo }; 2571c1737f2bSArnaldo Carvalho de Melo 257254cd4cdeSArnaldo Carvalho de Melo /** 257354cd4cdeSArnaldo Carvalho de Melo * struct drm_i915_gem_vm_control - Structure to create or destroy VM. 257454cd4cdeSArnaldo Carvalho de Melo * 2575e6aff9f8SArnaldo Carvalho de Melo * DRM_I915_GEM_VM_CREATE - 2576e6aff9f8SArnaldo Carvalho de Melo * 2577e6aff9f8SArnaldo Carvalho de Melo * Create a new virtual memory address space (ppGTT) for use within a context 2578e6aff9f8SArnaldo Carvalho de Melo * on the same file. Extensions can be provided to configure exactly how the 2579e6aff9f8SArnaldo Carvalho de Melo * address space is setup upon creation. 2580e6aff9f8SArnaldo Carvalho de Melo * 2581e6aff9f8SArnaldo Carvalho de Melo * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 2582e6aff9f8SArnaldo Carvalho de Melo * returned in the outparam @id. 2583e6aff9f8SArnaldo Carvalho de Melo * 2584e6aff9f8SArnaldo Carvalho de Melo * An extension chain maybe provided, starting with @extensions, and terminated 2585e6aff9f8SArnaldo Carvalho de Melo * by the @next_extension being 0. Currently, no extensions are defined. 2586e6aff9f8SArnaldo Carvalho de Melo * 2587e6aff9f8SArnaldo Carvalho de Melo * DRM_I915_GEM_VM_DESTROY - 2588e6aff9f8SArnaldo Carvalho de Melo * 258954cd4cdeSArnaldo Carvalho de Melo * Destroys a previously created VM id, specified in @vm_id. 2590e6aff9f8SArnaldo Carvalho de Melo * 2591e6aff9f8SArnaldo Carvalho de Melo * No extensions or flags are allowed currently, and so must be zero. 2592e6aff9f8SArnaldo Carvalho de Melo */ 2593e6aff9f8SArnaldo Carvalho de Melo struct drm_i915_gem_vm_control { 259454cd4cdeSArnaldo Carvalho de Melo /** @extensions: Zero-terminated chain of extensions. */ 2595e6aff9f8SArnaldo Carvalho de Melo __u64 extensions; 259654cd4cdeSArnaldo Carvalho de Melo 259754cd4cdeSArnaldo Carvalho de Melo /** @flags: reserved for future usage, currently MBZ */ 2598e6aff9f8SArnaldo Carvalho de Melo __u32 flags; 259954cd4cdeSArnaldo Carvalho de Melo 260054cd4cdeSArnaldo Carvalho de Melo /** @vm_id: Id of the VM created or to be destroyed */ 2601e6aff9f8SArnaldo Carvalho de Melo __u32 vm_id; 2602e6aff9f8SArnaldo Carvalho de Melo }; 2603e6aff9f8SArnaldo Carvalho de Melo 2604c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reg_read { 2605c1737f2bSArnaldo Carvalho de Melo /* 2606c1737f2bSArnaldo Carvalho de Melo * Register offset. 2607c1737f2bSArnaldo Carvalho de Melo * For 64bit wide registers where the upper 32bits don't immediately 2608c1737f2bSArnaldo Carvalho de Melo * follow the lower 32bits, the offset of the lower 32bits must 2609c1737f2bSArnaldo Carvalho de Melo * be specified 2610c1737f2bSArnaldo Carvalho de Melo */ 2611c1737f2bSArnaldo Carvalho de Melo __u64 offset; 2612485be0cbSArnaldo Carvalho de Melo #define I915_REG_READ_8B_WA (1ul << 0) 2613485be0cbSArnaldo Carvalho de Melo 2614c1737f2bSArnaldo Carvalho de Melo __u64 val; /* Return value */ 2615c1737f2bSArnaldo Carvalho de Melo }; 2616e6aff9f8SArnaldo Carvalho de Melo 2617c1737f2bSArnaldo Carvalho de Melo /* Known registers: 2618c1737f2bSArnaldo Carvalho de Melo * 2619c1737f2bSArnaldo Carvalho de Melo * Render engine timestamp - 0x2358 + 64bit - gen7+ 2620c1737f2bSArnaldo Carvalho de Melo * - Note this register returns an invalid value if using the default 2621485be0cbSArnaldo Carvalho de Melo * single instruction 8byte read, in order to workaround that pass 2622485be0cbSArnaldo Carvalho de Melo * flag I915_REG_READ_8B_WA in offset field. 2623c1737f2bSArnaldo Carvalho de Melo * 2624c1737f2bSArnaldo Carvalho de Melo */ 2625c1737f2bSArnaldo Carvalho de Melo 2626c1737f2bSArnaldo Carvalho de Melo struct drm_i915_reset_stats { 2627c1737f2bSArnaldo Carvalho de Melo __u32 ctx_id; 2628c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2629c1737f2bSArnaldo Carvalho de Melo 2630c1737f2bSArnaldo Carvalho de Melo /* All resets since boot/module reload, for all contexts */ 2631c1737f2bSArnaldo Carvalho de Melo __u32 reset_count; 2632c1737f2bSArnaldo Carvalho de Melo 2633c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost when active in GPU, for this context */ 2634c1737f2bSArnaldo Carvalho de Melo __u32 batch_active; 2635c1737f2bSArnaldo Carvalho de Melo 2636c1737f2bSArnaldo Carvalho de Melo /* Number of batches lost pending for execution, for this context */ 2637c1737f2bSArnaldo Carvalho de Melo __u32 batch_pending; 2638c1737f2bSArnaldo Carvalho de Melo 2639c1737f2bSArnaldo Carvalho de Melo __u32 pad; 2640c1737f2bSArnaldo Carvalho de Melo }; 2641c1737f2bSArnaldo Carvalho de Melo 26424dc24d7cSArnaldo Carvalho de Melo /** 26434dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. 26444dc24d7cSArnaldo Carvalho de Melo * 26454dc24d7cSArnaldo Carvalho de Melo * Userptr objects have several restrictions on what ioctls can be used with the 26464dc24d7cSArnaldo Carvalho de Melo * object handle. 26474dc24d7cSArnaldo Carvalho de Melo */ 2648c1737f2bSArnaldo Carvalho de Melo struct drm_i915_gem_userptr { 26494dc24d7cSArnaldo Carvalho de Melo /** 26504dc24d7cSArnaldo Carvalho de Melo * @user_ptr: The pointer to the allocated memory. 26514dc24d7cSArnaldo Carvalho de Melo * 26524dc24d7cSArnaldo Carvalho de Melo * Needs to be aligned to PAGE_SIZE. 26534dc24d7cSArnaldo Carvalho de Melo */ 2654c1737f2bSArnaldo Carvalho de Melo __u64 user_ptr; 26554dc24d7cSArnaldo Carvalho de Melo 26564dc24d7cSArnaldo Carvalho de Melo /** 26574dc24d7cSArnaldo Carvalho de Melo * @user_size: 26584dc24d7cSArnaldo Carvalho de Melo * 26594dc24d7cSArnaldo Carvalho de Melo * The size in bytes for the allocated memory. This will also become the 26604dc24d7cSArnaldo Carvalho de Melo * object size. 26614dc24d7cSArnaldo Carvalho de Melo * 26624dc24d7cSArnaldo Carvalho de Melo * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, 26634dc24d7cSArnaldo Carvalho de Melo * or larger. 26644dc24d7cSArnaldo Carvalho de Melo */ 2665c1737f2bSArnaldo Carvalho de Melo __u64 user_size; 26664dc24d7cSArnaldo Carvalho de Melo 26674dc24d7cSArnaldo Carvalho de Melo /** 26684dc24d7cSArnaldo Carvalho de Melo * @flags: 26694dc24d7cSArnaldo Carvalho de Melo * 26704dc24d7cSArnaldo Carvalho de Melo * Supported flags: 26714dc24d7cSArnaldo Carvalho de Melo * 26724dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_READ_ONLY: 26734dc24d7cSArnaldo Carvalho de Melo * 26744dc24d7cSArnaldo Carvalho de Melo * Mark the object as readonly, this also means GPU access can only be 26754dc24d7cSArnaldo Carvalho de Melo * readonly. This is only supported on HW which supports readonly access 26764dc24d7cSArnaldo Carvalho de Melo * through the GTT. If the HW can't support readonly access, an error is 26774dc24d7cSArnaldo Carvalho de Melo * returned. 26784dc24d7cSArnaldo Carvalho de Melo * 26794dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_PROBE: 26804dc24d7cSArnaldo Carvalho de Melo * 26814dc24d7cSArnaldo Carvalho de Melo * Probe the provided @user_ptr range and validate that the @user_ptr is 26824dc24d7cSArnaldo Carvalho de Melo * indeed pointing to normal memory and that the range is also valid. 26834dc24d7cSArnaldo Carvalho de Melo * For example if some garbage address is given to the kernel, then this 26844dc24d7cSArnaldo Carvalho de Melo * should complain. 26854dc24d7cSArnaldo Carvalho de Melo * 26864dc24d7cSArnaldo Carvalho de Melo * Returns -EFAULT if the probe failed. 26874dc24d7cSArnaldo Carvalho de Melo * 26884dc24d7cSArnaldo Carvalho de Melo * Note that this doesn't populate the backing pages, and also doesn't 26894dc24d7cSArnaldo Carvalho de Melo * guarantee that the object will remain valid when the object is 26904dc24d7cSArnaldo Carvalho de Melo * eventually used. 26914dc24d7cSArnaldo Carvalho de Melo * 26924dc24d7cSArnaldo Carvalho de Melo * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE 26934dc24d7cSArnaldo Carvalho de Melo * returns a non-zero value. 26944dc24d7cSArnaldo Carvalho de Melo * 26954dc24d7cSArnaldo Carvalho de Melo * I915_USERPTR_UNSYNCHRONIZED: 26964dc24d7cSArnaldo Carvalho de Melo * 26974dc24d7cSArnaldo Carvalho de Melo * NOT USED. Setting this flag will result in an error. 26984dc24d7cSArnaldo Carvalho de Melo */ 2699c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2700c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_READ_ONLY 0x1 27014dc24d7cSArnaldo Carvalho de Melo #define I915_USERPTR_PROBE 0x2 2702c1737f2bSArnaldo Carvalho de Melo #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 2703c1737f2bSArnaldo Carvalho de Melo /** 27044dc24d7cSArnaldo Carvalho de Melo * @handle: Returned handle for the object. 2705c1737f2bSArnaldo Carvalho de Melo * 2706c1737f2bSArnaldo Carvalho de Melo * Object handles are nonzero. 2707c1737f2bSArnaldo Carvalho de Melo */ 2708c1737f2bSArnaldo Carvalho de Melo __u32 handle; 2709c1737f2bSArnaldo Carvalho de Melo }; 2710c1737f2bSArnaldo Carvalho de Melo 2711c1737f2bSArnaldo Carvalho de Melo enum drm_i915_oa_format { 2712c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13 = 1, /* HSW only */ 2713c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A29, /* HSW only */ 2714c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 2715c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8, /* HSW only */ 2716c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 2717c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 2718c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_C4_B8, /* HSW+ */ 2719c1737f2bSArnaldo Carvalho de Melo 2720c1737f2bSArnaldo Carvalho de Melo /* Gen8+ */ 2721c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12, 2722c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A12_B8_C8, 2723c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_A32u40_A4u32_B8_C8, 2724c1737f2bSArnaldo Carvalho de Melo 2725eeac18e2SArnaldo Carvalho de Melo /* DG2 */ 2726eeac18e2SArnaldo Carvalho de Melo I915_OAR_FORMAT_A32u40_A4u32_B8_C8, 2727eeac18e2SArnaldo Carvalho de Melo I915_OA_FORMAT_A24u40_A14u32_B8_C8, 2728eeac18e2SArnaldo Carvalho de Melo 2729e7ec3a24SYanteng Si /* MTL OAM */ 2730e7ec3a24SYanteng Si I915_OAM_FORMAT_MPEC8u64_B8_C8, 2731e7ec3a24SYanteng Si I915_OAM_FORMAT_MPEC8u32_B8_C8, 2732e7ec3a24SYanteng Si 2733c1737f2bSArnaldo Carvalho de Melo I915_OA_FORMAT_MAX /* non-ABI */ 2734c1737f2bSArnaldo Carvalho de Melo }; 2735c1737f2bSArnaldo Carvalho de Melo 2736c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_property_id { 2737c1737f2bSArnaldo Carvalho de Melo /** 2738c1737f2bSArnaldo Carvalho de Melo * Open the stream for a specific context handle (as used with 2739c1737f2bSArnaldo Carvalho de Melo * execbuffer2). A stream opened for a specific context this way 2740c1737f2bSArnaldo Carvalho de Melo * won't typically require root privileges. 27410b3fca6aSArnaldo Carvalho de Melo * 27420b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2743c1737f2bSArnaldo Carvalho de Melo */ 2744c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_CTX_HANDLE = 1, 2745c1737f2bSArnaldo Carvalho de Melo 2746c1737f2bSArnaldo Carvalho de Melo /** 2747c1737f2bSArnaldo Carvalho de Melo * A value of 1 requests the inclusion of raw OA unit reports as 2748c1737f2bSArnaldo Carvalho de Melo * part of stream samples. 27490b3fca6aSArnaldo Carvalho de Melo * 27500b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2751c1737f2bSArnaldo Carvalho de Melo */ 2752c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_SAMPLE_OA, 2753c1737f2bSArnaldo Carvalho de Melo 2754c1737f2bSArnaldo Carvalho de Melo /** 2755c1737f2bSArnaldo Carvalho de Melo * The value specifies which set of OA unit metrics should be 2756d01541d0SArnaldo Carvalho de Melo * configured, defining the contents of any OA unit reports. 27570b3fca6aSArnaldo Carvalho de Melo * 27580b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2759c1737f2bSArnaldo Carvalho de Melo */ 2760c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_METRICS_SET, 2761c1737f2bSArnaldo Carvalho de Melo 2762c1737f2bSArnaldo Carvalho de Melo /** 2763c1737f2bSArnaldo Carvalho de Melo * The value specifies the size and layout of OA unit reports. 27640b3fca6aSArnaldo Carvalho de Melo * 27650b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2766c1737f2bSArnaldo Carvalho de Melo */ 2767c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_FORMAT, 2768c1737f2bSArnaldo Carvalho de Melo 2769c1737f2bSArnaldo Carvalho de Melo /** 2770c1737f2bSArnaldo Carvalho de Melo * Specifying this property implicitly requests periodic OA unit 2771c1737f2bSArnaldo Carvalho de Melo * sampling and (at least on Haswell) the sampling frequency is derived 2772c1737f2bSArnaldo Carvalho de Melo * from this exponent as follows: 2773c1737f2bSArnaldo Carvalho de Melo * 2774c1737f2bSArnaldo Carvalho de Melo * 80ns * 2^(period_exponent + 1) 27750b3fca6aSArnaldo Carvalho de Melo * 27760b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 1. 2777c1737f2bSArnaldo Carvalho de Melo */ 2778c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_OA_EXPONENT, 2779c1737f2bSArnaldo Carvalho de Melo 27800b3fca6aSArnaldo Carvalho de Melo /** 27810b3fca6aSArnaldo Carvalho de Melo * Specifying this property is only valid when specify a context to 27820b3fca6aSArnaldo Carvalho de Melo * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property 27830b3fca6aSArnaldo Carvalho de Melo * will hold preemption of the particular context we want to gather 27840b3fca6aSArnaldo Carvalho de Melo * performance data about. The execbuf2 submissions must include a 27850b3fca6aSArnaldo Carvalho de Melo * drm_i915_gem_execbuffer_ext_perf parameter for this to apply. 27860b3fca6aSArnaldo Carvalho de Melo * 27870b3fca6aSArnaldo Carvalho de Melo * This property is available in perf revision 3. 27880b3fca6aSArnaldo Carvalho de Melo */ 27890b3fca6aSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_HOLD_PREEMPTION, 27900b3fca6aSArnaldo Carvalho de Melo 2791377cb673SArnaldo Carvalho de Melo /** 2792377cb673SArnaldo Carvalho de Melo * Specifying this pins all contexts to the specified SSEU power 2793377cb673SArnaldo Carvalho de Melo * configuration for the duration of the recording. 2794377cb673SArnaldo Carvalho de Melo * 2795377cb673SArnaldo Carvalho de Melo * This parameter's value is a pointer to a struct 2796377cb673SArnaldo Carvalho de Melo * drm_i915_gem_context_param_sseu. 2797377cb673SArnaldo Carvalho de Melo * 2798377cb673SArnaldo Carvalho de Melo * This property is available in perf revision 4. 2799377cb673SArnaldo Carvalho de Melo */ 2800377cb673SArnaldo Carvalho de Melo DRM_I915_PERF_PROP_GLOBAL_SSEU, 2801377cb673SArnaldo Carvalho de Melo 2802377cb673SArnaldo Carvalho de Melo /** 2803377cb673SArnaldo Carvalho de Melo * This optional parameter specifies the timer interval in nanoseconds 2804377cb673SArnaldo Carvalho de Melo * at which the i915 driver will check the OA buffer for available data. 2805377cb673SArnaldo Carvalho de Melo * Minimum allowed value is 100 microseconds. A default value is used by 2806377cb673SArnaldo Carvalho de Melo * the driver if this parameter is not specified. Note that larger timer 2807377cb673SArnaldo Carvalho de Melo * values will reduce cpu consumption during OA perf captures. However, 2808377cb673SArnaldo Carvalho de Melo * excessively large values would potentially result in OA buffer 2809377cb673SArnaldo Carvalho de Melo * overwrites as captures reach end of the OA buffer. 2810377cb673SArnaldo Carvalho de Melo * 2811377cb673SArnaldo Carvalho de Melo * This property is available in perf revision 5. 2812377cb673SArnaldo Carvalho de Melo */ 2813377cb673SArnaldo Carvalho de Melo DRM_I915_PERF_PROP_POLL_OA_PERIOD, 2814377cb673SArnaldo Carvalho de Melo 2815e7ec3a24SYanteng Si /** 2816e7ec3a24SYanteng Si * Multiple engines may be mapped to the same OA unit. The OA unit is 2817e7ec3a24SYanteng Si * identified by class:instance of any engine mapped to it. 2818e7ec3a24SYanteng Si * 2819e7ec3a24SYanteng Si * This parameter specifies the engine class and must be passed along 2820e7ec3a24SYanteng Si * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE. 2821e7ec3a24SYanteng Si * 2822e7ec3a24SYanteng Si * This property is available in perf revision 6. 2823e7ec3a24SYanteng Si */ 2824e7ec3a24SYanteng Si DRM_I915_PERF_PROP_OA_ENGINE_CLASS, 2825e7ec3a24SYanteng Si 2826e7ec3a24SYanteng Si /** 2827e7ec3a24SYanteng Si * This parameter specifies the engine instance and must be passed along 2828e7ec3a24SYanteng Si * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS. 2829e7ec3a24SYanteng Si * 2830e7ec3a24SYanteng Si * This property is available in perf revision 6. 2831e7ec3a24SYanteng Si */ 2832e7ec3a24SYanteng Si DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE, 2833e7ec3a24SYanteng Si 2834c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_PROP_MAX /* non-ABI */ 2835c1737f2bSArnaldo Carvalho de Melo }; 2836c1737f2bSArnaldo Carvalho de Melo 2837c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_open_param { 2838c1737f2bSArnaldo Carvalho de Melo __u32 flags; 2839c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 2840c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 2841c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_FLAG_DISABLED (1<<2) 2842c1737f2bSArnaldo Carvalho de Melo 2843c1737f2bSArnaldo Carvalho de Melo /** The number of u64 (id, value) pairs */ 2844c1737f2bSArnaldo Carvalho de Melo __u32 num_properties; 2845c1737f2bSArnaldo Carvalho de Melo 2846c1737f2bSArnaldo Carvalho de Melo /** 2847c1737f2bSArnaldo Carvalho de Melo * Pointer to array of u64 (id, value) pairs configuring the stream 2848c1737f2bSArnaldo Carvalho de Melo * to open. 2849c1737f2bSArnaldo Carvalho de Melo */ 2850c1737f2bSArnaldo Carvalho de Melo __u64 properties_ptr; 2851c1737f2bSArnaldo Carvalho de Melo }; 2852c1737f2bSArnaldo Carvalho de Melo 28534a1cddeaSArnaldo Carvalho de Melo /* 2854c1737f2bSArnaldo Carvalho de Melo * Enable data capture for a stream that was either opened in a disabled state 2855c1737f2bSArnaldo Carvalho de Melo * via I915_PERF_FLAG_DISABLED or was later disabled via 2856c1737f2bSArnaldo Carvalho de Melo * I915_PERF_IOCTL_DISABLE. 2857c1737f2bSArnaldo Carvalho de Melo * 2858c1737f2bSArnaldo Carvalho de Melo * It is intended to be cheaper to disable and enable a stream than it may be 2859c1737f2bSArnaldo Carvalho de Melo * to close and re-open a stream with the same configuration. 2860c1737f2bSArnaldo Carvalho de Melo * 2861c1737f2bSArnaldo Carvalho de Melo * It's undefined whether any pending data for the stream will be lost. 28620b3fca6aSArnaldo Carvalho de Melo * 28630b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 1. 2864c1737f2bSArnaldo Carvalho de Melo */ 2865c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 2866c1737f2bSArnaldo Carvalho de Melo 28674a1cddeaSArnaldo Carvalho de Melo /* 2868c1737f2bSArnaldo Carvalho de Melo * Disable data capture for a stream. 2869c1737f2bSArnaldo Carvalho de Melo * 2870c1737f2bSArnaldo Carvalho de Melo * It is an error to try and read a stream that is disabled. 28710b3fca6aSArnaldo Carvalho de Melo * 28720b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 1. 2873c1737f2bSArnaldo Carvalho de Melo */ 2874c1737f2bSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 2875c1737f2bSArnaldo Carvalho de Melo 28764a1cddeaSArnaldo Carvalho de Melo /* 28770b3fca6aSArnaldo Carvalho de Melo * Change metrics_set captured by a stream. 28780b3fca6aSArnaldo Carvalho de Melo * 28790b3fca6aSArnaldo Carvalho de Melo * If the stream is bound to a specific context, the configuration change 28800b3fca6aSArnaldo Carvalho de Melo * will performed inline with that context such that it takes effect before 28810b3fca6aSArnaldo Carvalho de Melo * the next execbuf submission. 28820b3fca6aSArnaldo Carvalho de Melo * 28830b3fca6aSArnaldo Carvalho de Melo * Returns the previously bound metrics set id, or a negative error code. 28840b3fca6aSArnaldo Carvalho de Melo * 28850b3fca6aSArnaldo Carvalho de Melo * This ioctl is available in perf revision 2. 28860b3fca6aSArnaldo Carvalho de Melo */ 28870b3fca6aSArnaldo Carvalho de Melo #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 28880b3fca6aSArnaldo Carvalho de Melo 28894a1cddeaSArnaldo Carvalho de Melo /* 2890c1737f2bSArnaldo Carvalho de Melo * Common to all i915 perf records 2891c1737f2bSArnaldo Carvalho de Melo */ 2892c1737f2bSArnaldo Carvalho de Melo struct drm_i915_perf_record_header { 2893c1737f2bSArnaldo Carvalho de Melo __u32 type; 2894c1737f2bSArnaldo Carvalho de Melo __u16 pad; 2895c1737f2bSArnaldo Carvalho de Melo __u16 size; 2896c1737f2bSArnaldo Carvalho de Melo }; 2897c1737f2bSArnaldo Carvalho de Melo 2898c1737f2bSArnaldo Carvalho de Melo enum drm_i915_perf_record_type { 2899c1737f2bSArnaldo Carvalho de Melo 2900c1737f2bSArnaldo Carvalho de Melo /** 2901c1737f2bSArnaldo Carvalho de Melo * Samples are the work horse record type whose contents are extensible 2902c1737f2bSArnaldo Carvalho de Melo * and defined when opening an i915 perf stream based on the given 2903c1737f2bSArnaldo Carvalho de Melo * properties. 2904c1737f2bSArnaldo Carvalho de Melo * 2905c1737f2bSArnaldo Carvalho de Melo * Boolean properties following the naming convention 2906c1737f2bSArnaldo Carvalho de Melo * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 2907c1737f2bSArnaldo Carvalho de Melo * every sample. 2908c1737f2bSArnaldo Carvalho de Melo * 2909c1737f2bSArnaldo Carvalho de Melo * The order of these sample properties given by userspace has no 2910c1737f2bSArnaldo Carvalho de Melo * affect on the ordering of data within a sample. The order is 2911c1737f2bSArnaldo Carvalho de Melo * documented here. 2912c1737f2bSArnaldo Carvalho de Melo * 2913c1737f2bSArnaldo Carvalho de Melo * struct { 2914c1737f2bSArnaldo Carvalho de Melo * struct drm_i915_perf_record_header header; 2915c1737f2bSArnaldo Carvalho de Melo * 2916c1737f2bSArnaldo Carvalho de Melo * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 2917c1737f2bSArnaldo Carvalho de Melo * }; 2918c1737f2bSArnaldo Carvalho de Melo */ 2919c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_SAMPLE = 1, 2920c1737f2bSArnaldo Carvalho de Melo 2921c1737f2bSArnaldo Carvalho de Melo /* 2922c1737f2bSArnaldo Carvalho de Melo * Indicates that one or more OA reports were not written by the 2923c1737f2bSArnaldo Carvalho de Melo * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 2924c1737f2bSArnaldo Carvalho de Melo * command collides with periodic sampling - which would be more likely 2925c1737f2bSArnaldo Carvalho de Melo * at higher sampling frequencies. 2926c1737f2bSArnaldo Carvalho de Melo */ 2927c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 2928c1737f2bSArnaldo Carvalho de Melo 2929c1737f2bSArnaldo Carvalho de Melo /** 2930c1737f2bSArnaldo Carvalho de Melo * An error occurred that resulted in all pending OA reports being lost. 2931c1737f2bSArnaldo Carvalho de Melo */ 2932c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 2933c1737f2bSArnaldo Carvalho de Melo 2934c1737f2bSArnaldo Carvalho de Melo DRM_I915_PERF_RECORD_MAX /* non-ABI */ 2935c1737f2bSArnaldo Carvalho de Melo }; 2936c1737f2bSArnaldo Carvalho de Melo 29370fdd435cSArnaldo Carvalho de Melo /** 29380fdd435cSArnaldo Carvalho de Melo * struct drm_i915_perf_oa_config 29390fdd435cSArnaldo Carvalho de Melo * 2940549a3976SIngo Molnar * Structure to upload perf dynamic configuration into the kernel. 2941549a3976SIngo Molnar */ 2942549a3976SIngo Molnar struct drm_i915_perf_oa_config { 29430fdd435cSArnaldo Carvalho de Melo /** 29440fdd435cSArnaldo Carvalho de Melo * @uuid: 29450fdd435cSArnaldo Carvalho de Melo * 29460fdd435cSArnaldo Carvalho de Melo * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" 29470fdd435cSArnaldo Carvalho de Melo */ 2948549a3976SIngo Molnar char uuid[36]; 2949549a3976SIngo Molnar 29500fdd435cSArnaldo Carvalho de Melo /** 29510fdd435cSArnaldo Carvalho de Melo * @n_mux_regs: 29520fdd435cSArnaldo Carvalho de Melo * 29530fdd435cSArnaldo Carvalho de Melo * Number of mux regs in &mux_regs_ptr. 29540fdd435cSArnaldo Carvalho de Melo */ 2955549a3976SIngo Molnar __u32 n_mux_regs; 29560fdd435cSArnaldo Carvalho de Melo 29570fdd435cSArnaldo Carvalho de Melo /** 29580fdd435cSArnaldo Carvalho de Melo * @n_boolean_regs: 29590fdd435cSArnaldo Carvalho de Melo * 29600fdd435cSArnaldo Carvalho de Melo * Number of boolean regs in &boolean_regs_ptr. 29610fdd435cSArnaldo Carvalho de Melo */ 2962549a3976SIngo Molnar __u32 n_boolean_regs; 29630fdd435cSArnaldo Carvalho de Melo 29640fdd435cSArnaldo Carvalho de Melo /** 29650fdd435cSArnaldo Carvalho de Melo * @n_flex_regs: 29660fdd435cSArnaldo Carvalho de Melo * 29670fdd435cSArnaldo Carvalho de Melo * Number of flex regs in &flex_regs_ptr. 29680fdd435cSArnaldo Carvalho de Melo */ 2969549a3976SIngo Molnar __u32 n_flex_regs; 2970549a3976SIngo Molnar 29710fdd435cSArnaldo Carvalho de Melo /** 29720fdd435cSArnaldo Carvalho de Melo * @mux_regs_ptr: 29730fdd435cSArnaldo Carvalho de Melo * 29740fdd435cSArnaldo Carvalho de Melo * Pointer to tuples of u32 values (register address, value) for mux 29750fdd435cSArnaldo Carvalho de Melo * registers. Expected length of buffer is (2 * sizeof(u32) * 29760fdd435cSArnaldo Carvalho de Melo * &n_mux_regs). 2977485be0cbSArnaldo Carvalho de Melo */ 2978485be0cbSArnaldo Carvalho de Melo __u64 mux_regs_ptr; 29790fdd435cSArnaldo Carvalho de Melo 29800fdd435cSArnaldo Carvalho de Melo /** 29810fdd435cSArnaldo Carvalho de Melo * @boolean_regs_ptr: 29820fdd435cSArnaldo Carvalho de Melo * 29830fdd435cSArnaldo Carvalho de Melo * Pointer to tuples of u32 values (register address, value) for mux 29840fdd435cSArnaldo Carvalho de Melo * registers. Expected length of buffer is (2 * sizeof(u32) * 29850fdd435cSArnaldo Carvalho de Melo * &n_boolean_regs). 29860fdd435cSArnaldo Carvalho de Melo */ 2987485be0cbSArnaldo Carvalho de Melo __u64 boolean_regs_ptr; 29880fdd435cSArnaldo Carvalho de Melo 29890fdd435cSArnaldo Carvalho de Melo /** 29900fdd435cSArnaldo Carvalho de Melo * @flex_regs_ptr: 29910fdd435cSArnaldo Carvalho de Melo * 29920fdd435cSArnaldo Carvalho de Melo * Pointer to tuples of u32 values (register address, value) for mux 29930fdd435cSArnaldo Carvalho de Melo * registers. Expected length of buffer is (2 * sizeof(u32) * 29940fdd435cSArnaldo Carvalho de Melo * &n_flex_regs). 29950fdd435cSArnaldo Carvalho de Melo */ 2996485be0cbSArnaldo Carvalho de Melo __u64 flex_regs_ptr; 2997549a3976SIngo Molnar }; 2998549a3976SIngo Molnar 29994a1cddeaSArnaldo Carvalho de Melo /** 30004a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_item - An individual query for the kernel to process. 30014a1cddeaSArnaldo Carvalho de Melo * 30024a1cddeaSArnaldo Carvalho de Melo * The behaviour is determined by the @query_id. Note that exactly what 30034a1cddeaSArnaldo Carvalho de Melo * @data_ptr is also depends on the specific @query_id. 30044a1cddeaSArnaldo Carvalho de Melo */ 300501f97511SArnaldo Carvalho de Melo struct drm_i915_query_item { 30060fdd435cSArnaldo Carvalho de Melo /** 30070fdd435cSArnaldo Carvalho de Melo * @query_id: 30080fdd435cSArnaldo Carvalho de Melo * 30090fdd435cSArnaldo Carvalho de Melo * The id for this query. Currently accepted query IDs are: 30100fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info) 30110fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info) 30120fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config) 30130fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) 30140fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) 30150fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) 30160fdd435cSArnaldo Carvalho de Melo */ 301701f97511SArnaldo Carvalho de Melo __u64 query_id; 301801f97511SArnaldo Carvalho de Melo #define DRM_I915_QUERY_TOPOLOGY_INFO 1 301995dc663aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_ENGINE_INFO 2 30200b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG 3 30214a1cddeaSArnaldo Carvalho de Melo #define DRM_I915_QUERY_MEMORY_REGIONS 4 30220fdd435cSArnaldo Carvalho de Melo #define DRM_I915_QUERY_HWCONFIG_BLOB 5 30230fdd435cSArnaldo Carvalho de Melo #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 3024e6aff9f8SArnaldo Carvalho de Melo /* Must be kept compact -- no holes and well documented */ 302501f97511SArnaldo Carvalho de Melo 30264a1cddeaSArnaldo Carvalho de Melo /** 30274a1cddeaSArnaldo Carvalho de Melo * @length: 30284a1cddeaSArnaldo Carvalho de Melo * 302901f97511SArnaldo Carvalho de Melo * When set to zero by userspace, this is filled with the size of the 30304a1cddeaSArnaldo Carvalho de Melo * data to be written at the @data_ptr pointer. The kernel sets this 303101f97511SArnaldo Carvalho de Melo * value to a negative value to signal an error on a particular query 303201f97511SArnaldo Carvalho de Melo * item. 303301f97511SArnaldo Carvalho de Melo */ 303401f97511SArnaldo Carvalho de Melo __s32 length; 303501f97511SArnaldo Carvalho de Melo 30364a1cddeaSArnaldo Carvalho de Melo /** 30374a1cddeaSArnaldo Carvalho de Melo * @flags: 30384a1cddeaSArnaldo Carvalho de Melo * 30390fdd435cSArnaldo Carvalho de Melo * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. 30400b3fca6aSArnaldo Carvalho de Melo * 30410fdd435cSArnaldo Carvalho de Melo * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the 30420b3fca6aSArnaldo Carvalho de Melo * following: 30434a1cddeaSArnaldo Carvalho de Melo * 30440fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_PERF_CONFIG_LIST 30450fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 30460fdd435cSArnaldo Carvalho de Melo * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID 30470fdd435cSArnaldo Carvalho de Melo * 30480fdd435cSArnaldo Carvalho de Melo * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain 30490fdd435cSArnaldo Carvalho de Melo * a struct i915_engine_class_instance that references a render engine. 305001f97511SArnaldo Carvalho de Melo */ 305101f97511SArnaldo Carvalho de Melo __u32 flags; 30520b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 30530b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 30540b3fca6aSArnaldo Carvalho de Melo #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 305501f97511SArnaldo Carvalho de Melo 30564a1cddeaSArnaldo Carvalho de Melo /** 30574a1cddeaSArnaldo Carvalho de Melo * @data_ptr: 30584a1cddeaSArnaldo Carvalho de Melo * 30594a1cddeaSArnaldo Carvalho de Melo * Data will be written at the location pointed by @data_ptr when the 30604a1cddeaSArnaldo Carvalho de Melo * value of @length matches the length of the data to be written by the 306101f97511SArnaldo Carvalho de Melo * kernel. 306201f97511SArnaldo Carvalho de Melo */ 306301f97511SArnaldo Carvalho de Melo __u64 data_ptr; 306401f97511SArnaldo Carvalho de Melo }; 306501f97511SArnaldo Carvalho de Melo 30664a1cddeaSArnaldo Carvalho de Melo /** 30674a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the 30684a1cddeaSArnaldo Carvalho de Melo * kernel to fill out. 30694a1cddeaSArnaldo Carvalho de Melo * 30704a1cddeaSArnaldo Carvalho de Melo * Note that this is generally a two step process for each struct 30714a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_item in the array: 30724a1cddeaSArnaldo Carvalho de Melo * 30734a1cddeaSArnaldo Carvalho de Melo * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct 30744a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The 30754a1cddeaSArnaldo Carvalho de Melo * kernel will then fill in the size, in bytes, which tells userspace how 30764a1cddeaSArnaldo Carvalho de Melo * memory it needs to allocate for the blob(say for an array of properties). 30774a1cddeaSArnaldo Carvalho de Melo * 30784a1cddeaSArnaldo Carvalho de Melo * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the 30794a1cddeaSArnaldo Carvalho de Melo * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that 30804a1cddeaSArnaldo Carvalho de Melo * the &drm_i915_query_item.length should still be the same as what the 30814a1cddeaSArnaldo Carvalho de Melo * kernel previously set. At this point the kernel can fill in the blob. 30824a1cddeaSArnaldo Carvalho de Melo * 30834a1cddeaSArnaldo Carvalho de Melo * Note that for some query items it can make sense for userspace to just pass 30844a1cddeaSArnaldo Carvalho de Melo * in a buffer/blob equal to or larger than the required size. In this case only 30854a1cddeaSArnaldo Carvalho de Melo * a single ioctl call is needed. For some smaller query items this can work 30864a1cddeaSArnaldo Carvalho de Melo * quite well. 30874a1cddeaSArnaldo Carvalho de Melo * 30884a1cddeaSArnaldo Carvalho de Melo */ 308901f97511SArnaldo Carvalho de Melo struct drm_i915_query { 30904a1cddeaSArnaldo Carvalho de Melo /** @num_items: The number of elements in the @items_ptr array */ 309101f97511SArnaldo Carvalho de Melo __u32 num_items; 309201f97511SArnaldo Carvalho de Melo 30934a1cddeaSArnaldo Carvalho de Melo /** 30944a1cddeaSArnaldo Carvalho de Melo * @flags: Unused for now. Must be cleared to zero. 309501f97511SArnaldo Carvalho de Melo */ 309601f97511SArnaldo Carvalho de Melo __u32 flags; 309701f97511SArnaldo Carvalho de Melo 30984a1cddeaSArnaldo Carvalho de Melo /** 30994a1cddeaSArnaldo Carvalho de Melo * @items_ptr: 31004a1cddeaSArnaldo Carvalho de Melo * 31014a1cddeaSArnaldo Carvalho de Melo * Pointer to an array of struct drm_i915_query_item. The number of 31024a1cddeaSArnaldo Carvalho de Melo * array elements is @num_items. 310301f97511SArnaldo Carvalho de Melo */ 310401f97511SArnaldo Carvalho de Melo __u64 items_ptr; 310501f97511SArnaldo Carvalho de Melo }; 310601f97511SArnaldo Carvalho de Melo 31070fdd435cSArnaldo Carvalho de Melo /** 31080fdd435cSArnaldo Carvalho de Melo * struct drm_i915_query_topology_info 310901f97511SArnaldo Carvalho de Melo * 31100fdd435cSArnaldo Carvalho de Melo * Describes slice/subslice/EU information queried by 31110fdd435cSArnaldo Carvalho de Melo * %DRM_I915_QUERY_TOPOLOGY_INFO 311201f97511SArnaldo Carvalho de Melo */ 311301f97511SArnaldo Carvalho de Melo struct drm_i915_query_topology_info { 31140fdd435cSArnaldo Carvalho de Melo /** 31150fdd435cSArnaldo Carvalho de Melo * @flags: 31160fdd435cSArnaldo Carvalho de Melo * 311701f97511SArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 311801f97511SArnaldo Carvalho de Melo */ 311901f97511SArnaldo Carvalho de Melo __u16 flags; 312001f97511SArnaldo Carvalho de Melo 31210fdd435cSArnaldo Carvalho de Melo /** 31220fdd435cSArnaldo Carvalho de Melo * @max_slices: 31230fdd435cSArnaldo Carvalho de Melo * 31240fdd435cSArnaldo Carvalho de Melo * The number of bits used to express the slice mask. 31250fdd435cSArnaldo Carvalho de Melo */ 312601f97511SArnaldo Carvalho de Melo __u16 max_slices; 31270fdd435cSArnaldo Carvalho de Melo 31280fdd435cSArnaldo Carvalho de Melo /** 31290fdd435cSArnaldo Carvalho de Melo * @max_subslices: 31300fdd435cSArnaldo Carvalho de Melo * 31310fdd435cSArnaldo Carvalho de Melo * The number of bits used to express the subslice mask. 31320fdd435cSArnaldo Carvalho de Melo */ 313301f97511SArnaldo Carvalho de Melo __u16 max_subslices; 31340fdd435cSArnaldo Carvalho de Melo 31350fdd435cSArnaldo Carvalho de Melo /** 31360fdd435cSArnaldo Carvalho de Melo * @max_eus_per_subslice: 31370fdd435cSArnaldo Carvalho de Melo * 31380fdd435cSArnaldo Carvalho de Melo * The number of bits in the EU mask that correspond to a single 31390fdd435cSArnaldo Carvalho de Melo * subslice's EUs. 31400fdd435cSArnaldo Carvalho de Melo */ 314101f97511SArnaldo Carvalho de Melo __u16 max_eus_per_subslice; 314201f97511SArnaldo Carvalho de Melo 31430fdd435cSArnaldo Carvalho de Melo /** 31440fdd435cSArnaldo Carvalho de Melo * @subslice_offset: 31450fdd435cSArnaldo Carvalho de Melo * 314601f97511SArnaldo Carvalho de Melo * Offset in data[] at which the subslice masks are stored. 314701f97511SArnaldo Carvalho de Melo */ 314801f97511SArnaldo Carvalho de Melo __u16 subslice_offset; 314901f97511SArnaldo Carvalho de Melo 31500fdd435cSArnaldo Carvalho de Melo /** 31510fdd435cSArnaldo Carvalho de Melo * @subslice_stride: 31520fdd435cSArnaldo Carvalho de Melo * 315301f97511SArnaldo Carvalho de Melo * Stride at which each of the subslice masks for each slice are 315401f97511SArnaldo Carvalho de Melo * stored. 315501f97511SArnaldo Carvalho de Melo */ 315601f97511SArnaldo Carvalho de Melo __u16 subslice_stride; 315701f97511SArnaldo Carvalho de Melo 31580fdd435cSArnaldo Carvalho de Melo /** 31590fdd435cSArnaldo Carvalho de Melo * @eu_offset: 31600fdd435cSArnaldo Carvalho de Melo * 316101f97511SArnaldo Carvalho de Melo * Offset in data[] at which the EU masks are stored. 316201f97511SArnaldo Carvalho de Melo */ 316301f97511SArnaldo Carvalho de Melo __u16 eu_offset; 316401f97511SArnaldo Carvalho de Melo 31650fdd435cSArnaldo Carvalho de Melo /** 31660fdd435cSArnaldo Carvalho de Melo * @eu_stride: 31670fdd435cSArnaldo Carvalho de Melo * 316801f97511SArnaldo Carvalho de Melo * Stride at which each of the EU masks for each subslice are stored. 316901f97511SArnaldo Carvalho de Melo */ 317001f97511SArnaldo Carvalho de Melo __u16 eu_stride; 317101f97511SArnaldo Carvalho de Melo 31720fdd435cSArnaldo Carvalho de Melo /** 31730fdd435cSArnaldo Carvalho de Melo * @data: 31740fdd435cSArnaldo Carvalho de Melo * 31750fdd435cSArnaldo Carvalho de Melo * Contains 3 pieces of information : 31760fdd435cSArnaldo Carvalho de Melo * 31770fdd435cSArnaldo Carvalho de Melo * - The slice mask with one bit per slice telling whether a slice is 31780fdd435cSArnaldo Carvalho de Melo * available. The availability of slice X can be queried with the 31790fdd435cSArnaldo Carvalho de Melo * following formula : 31800fdd435cSArnaldo Carvalho de Melo * 31810fdd435cSArnaldo Carvalho de Melo * .. code:: c 31820fdd435cSArnaldo Carvalho de Melo * 31830fdd435cSArnaldo Carvalho de Melo * (data[X / 8] >> (X % 8)) & 1 31840fdd435cSArnaldo Carvalho de Melo * 31850fdd435cSArnaldo Carvalho de Melo * Starting with Xe_HP platforms, Intel hardware no longer has 31860fdd435cSArnaldo Carvalho de Melo * traditional slices so i915 will always report a single slice 31870fdd435cSArnaldo Carvalho de Melo * (hardcoded slicemask = 0x1) which contains all of the platform's 31880fdd435cSArnaldo Carvalho de Melo * subslices. I.e., the mask here does not reflect any of the newer 31890fdd435cSArnaldo Carvalho de Melo * hardware concepts such as "gslices" or "cslices" since userspace 31900fdd435cSArnaldo Carvalho de Melo * is capable of inferring those from the subslice mask. 31910fdd435cSArnaldo Carvalho de Melo * 31920fdd435cSArnaldo Carvalho de Melo * - The subslice mask for each slice with one bit per subslice telling 31930fdd435cSArnaldo Carvalho de Melo * whether a subslice is available. Starting with Gen12 we use the 31940fdd435cSArnaldo Carvalho de Melo * term "subslice" to refer to what the hardware documentation 31950fdd435cSArnaldo Carvalho de Melo * describes as a "dual-subslices." The availability of subslice Y 31960fdd435cSArnaldo Carvalho de Melo * in slice X can be queried with the following formula : 31970fdd435cSArnaldo Carvalho de Melo * 31980fdd435cSArnaldo Carvalho de Melo * .. code:: c 31990fdd435cSArnaldo Carvalho de Melo * 32000fdd435cSArnaldo Carvalho de Melo * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 32010fdd435cSArnaldo Carvalho de Melo * 32020fdd435cSArnaldo Carvalho de Melo * - The EU mask for each subslice in each slice, with one bit per EU 32030fdd435cSArnaldo Carvalho de Melo * telling whether an EU is available. The availability of EU Z in 32040fdd435cSArnaldo Carvalho de Melo * subslice Y in slice X can be queried with the following formula : 32050fdd435cSArnaldo Carvalho de Melo * 32060fdd435cSArnaldo Carvalho de Melo * .. code:: c 32070fdd435cSArnaldo Carvalho de Melo * 32080fdd435cSArnaldo Carvalho de Melo * (data[eu_offset + 32090fdd435cSArnaldo Carvalho de Melo * (X * max_subslices + Y) * eu_stride + 32100fdd435cSArnaldo Carvalho de Melo * Z / 8 32110fdd435cSArnaldo Carvalho de Melo * ] >> (Z % 8)) & 1 32120fdd435cSArnaldo Carvalho de Melo */ 321301f97511SArnaldo Carvalho de Melo __u8 data[]; 321401f97511SArnaldo Carvalho de Melo }; 321501f97511SArnaldo Carvalho de Melo 321695dc663aSArnaldo Carvalho de Melo /** 32174dc24d7cSArnaldo Carvalho de Melo * DOC: Engine Discovery uAPI 32184dc24d7cSArnaldo Carvalho de Melo * 32194dc24d7cSArnaldo Carvalho de Melo * Engine discovery uAPI is a way of enumerating physical engines present in a 32204dc24d7cSArnaldo Carvalho de Melo * GPU associated with an open i915 DRM file descriptor. This supersedes the old 32214dc24d7cSArnaldo Carvalho de Melo * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like 32224dc24d7cSArnaldo Carvalho de Melo * `I915_PARAM_HAS_BLT`. 32234dc24d7cSArnaldo Carvalho de Melo * 32244dc24d7cSArnaldo Carvalho de Melo * The need for this interface came starting with Icelake and newer GPUs, which 32254dc24d7cSArnaldo Carvalho de Melo * started to establish a pattern of having multiple engines of a same class, 32264dc24d7cSArnaldo Carvalho de Melo * where not all instances were always completely functionally equivalent. 32274dc24d7cSArnaldo Carvalho de Melo * 32284dc24d7cSArnaldo Carvalho de Melo * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the 32294dc24d7cSArnaldo Carvalho de Melo * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. 32304dc24d7cSArnaldo Carvalho de Melo * 32314dc24d7cSArnaldo Carvalho de Melo * Example for getting the list of engines: 32324dc24d7cSArnaldo Carvalho de Melo * 32334dc24d7cSArnaldo Carvalho de Melo * .. code-block:: C 32344dc24d7cSArnaldo Carvalho de Melo * 32354dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query_engine_info *info; 32364dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query_item item = { 32374dc24d7cSArnaldo Carvalho de Melo * .query_id = DRM_I915_QUERY_ENGINE_INFO; 32384dc24d7cSArnaldo Carvalho de Melo * }; 32394dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_query query = { 32404dc24d7cSArnaldo Carvalho de Melo * .num_items = 1, 32414dc24d7cSArnaldo Carvalho de Melo * .items_ptr = (uintptr_t)&item, 32424dc24d7cSArnaldo Carvalho de Melo * }; 32434dc24d7cSArnaldo Carvalho de Melo * int err, i; 32444dc24d7cSArnaldo Carvalho de Melo * 32454dc24d7cSArnaldo Carvalho de Melo * // First query the size of the blob we need, this needs to be large 32464dc24d7cSArnaldo Carvalho de Melo * // enough to hold our array of engines. The kernel will fill out the 32474dc24d7cSArnaldo Carvalho de Melo * // item.length for us, which is the number of bytes we need. 32484dc24d7cSArnaldo Carvalho de Melo * // 32494dc24d7cSArnaldo Carvalho de Melo * // Alternatively a large buffer can be allocated straight away enabling 32504dc24d7cSArnaldo Carvalho de Melo * // querying in one pass, in which case item.length should contain the 32514dc24d7cSArnaldo Carvalho de Melo * // length of the provided buffer. 32524dc24d7cSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 32534dc24d7cSArnaldo Carvalho de Melo * if (err) ... 32544dc24d7cSArnaldo Carvalho de Melo * 32554dc24d7cSArnaldo Carvalho de Melo * info = calloc(1, item.length); 32564dc24d7cSArnaldo Carvalho de Melo * // Now that we allocated the required number of bytes, we call the ioctl 32574dc24d7cSArnaldo Carvalho de Melo * // again, this time with the data_ptr pointing to our newly allocated 32584dc24d7cSArnaldo Carvalho de Melo * // blob, which the kernel can then populate with info on all engines. 32594dc24d7cSArnaldo Carvalho de Melo * item.data_ptr = (uintptr_t)&info, 32604dc24d7cSArnaldo Carvalho de Melo * 32614dc24d7cSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 32624dc24d7cSArnaldo Carvalho de Melo * if (err) ... 32634dc24d7cSArnaldo Carvalho de Melo * 32644dc24d7cSArnaldo Carvalho de Melo * // We can now access each engine in the array 32654dc24d7cSArnaldo Carvalho de Melo * for (i = 0; i < info->num_engines; i++) { 32664dc24d7cSArnaldo Carvalho de Melo * struct drm_i915_engine_info einfo = info->engines[i]; 32674dc24d7cSArnaldo Carvalho de Melo * u16 class = einfo.engine.class; 32684dc24d7cSArnaldo Carvalho de Melo * u16 instance = einfo.engine.instance; 32694dc24d7cSArnaldo Carvalho de Melo * .... 32704dc24d7cSArnaldo Carvalho de Melo * } 32714dc24d7cSArnaldo Carvalho de Melo * 32724dc24d7cSArnaldo Carvalho de Melo * free(info); 32734dc24d7cSArnaldo Carvalho de Melo * 32744dc24d7cSArnaldo Carvalho de Melo * Each of the enumerated engines, apart from being defined by its class and 32754dc24d7cSArnaldo Carvalho de Melo * instance (see `struct i915_engine_class_instance`), also can have flags and 32764dc24d7cSArnaldo Carvalho de Melo * capabilities defined as documented in i915_drm.h. 32774dc24d7cSArnaldo Carvalho de Melo * 32784dc24d7cSArnaldo Carvalho de Melo * For instance video engines which support HEVC encoding will have the 32794dc24d7cSArnaldo Carvalho de Melo * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. 32804dc24d7cSArnaldo Carvalho de Melo * 32814dc24d7cSArnaldo Carvalho de Melo * Engine discovery only fully comes to its own when combined with the new way 32824dc24d7cSArnaldo Carvalho de Melo * of addressing engines when submitting batch buffers using contexts with 32834dc24d7cSArnaldo Carvalho de Melo * engine maps configured. 32844dc24d7cSArnaldo Carvalho de Melo */ 32854dc24d7cSArnaldo Carvalho de Melo 32864dc24d7cSArnaldo Carvalho de Melo /** 328795dc663aSArnaldo Carvalho de Melo * struct drm_i915_engine_info 328895dc663aSArnaldo Carvalho de Melo * 328995dc663aSArnaldo Carvalho de Melo * Describes one engine and it's capabilities as known to the driver. 329095dc663aSArnaldo Carvalho de Melo */ 329195dc663aSArnaldo Carvalho de Melo struct drm_i915_engine_info { 32924a1cddeaSArnaldo Carvalho de Melo /** @engine: Engine class and instance. */ 329395dc663aSArnaldo Carvalho de Melo struct i915_engine_class_instance engine; 329495dc663aSArnaldo Carvalho de Melo 32954a1cddeaSArnaldo Carvalho de Melo /** @rsvd0: Reserved field. */ 329695dc663aSArnaldo Carvalho de Melo __u32 rsvd0; 329795dc663aSArnaldo Carvalho de Melo 32984a1cddeaSArnaldo Carvalho de Melo /** @flags: Engine flags. */ 329995dc663aSArnaldo Carvalho de Melo __u64 flags; 330006cf00c4SArnaldo Carvalho de Melo #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) 330195dc663aSArnaldo Carvalho de Melo 33024a1cddeaSArnaldo Carvalho de Melo /** @capabilities: Capabilities of this engine. */ 330395dc663aSArnaldo Carvalho de Melo __u64 capabilities; 330495dc663aSArnaldo Carvalho de Melo #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 330595dc663aSArnaldo Carvalho de Melo #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 330695dc663aSArnaldo Carvalho de Melo 330706cf00c4SArnaldo Carvalho de Melo /** @logical_instance: Logical instance of engine */ 330806cf00c4SArnaldo Carvalho de Melo __u16 logical_instance; 330906cf00c4SArnaldo Carvalho de Melo 33104a1cddeaSArnaldo Carvalho de Melo /** @rsvd1: Reserved fields. */ 331106cf00c4SArnaldo Carvalho de Melo __u16 rsvd1[3]; 331206cf00c4SArnaldo Carvalho de Melo /** @rsvd2: Reserved fields. */ 331306cf00c4SArnaldo Carvalho de Melo __u64 rsvd2[3]; 331495dc663aSArnaldo Carvalho de Melo }; 331595dc663aSArnaldo Carvalho de Melo 331695dc663aSArnaldo Carvalho de Melo /** 331795dc663aSArnaldo Carvalho de Melo * struct drm_i915_query_engine_info 331895dc663aSArnaldo Carvalho de Melo * 331995dc663aSArnaldo Carvalho de Melo * Engine info query enumerates all engines known to the driver by filling in 332095dc663aSArnaldo Carvalho de Melo * an array of struct drm_i915_engine_info structures. 332195dc663aSArnaldo Carvalho de Melo */ 332295dc663aSArnaldo Carvalho de Melo struct drm_i915_query_engine_info { 33234a1cddeaSArnaldo Carvalho de Melo /** @num_engines: Number of struct drm_i915_engine_info structs following. */ 332495dc663aSArnaldo Carvalho de Melo __u32 num_engines; 332595dc663aSArnaldo Carvalho de Melo 33264a1cddeaSArnaldo Carvalho de Melo /** @rsvd: MBZ */ 332795dc663aSArnaldo Carvalho de Melo __u32 rsvd[3]; 332895dc663aSArnaldo Carvalho de Melo 33294a1cddeaSArnaldo Carvalho de Melo /** @engines: Marker for drm_i915_engine_info structures. */ 333095dc663aSArnaldo Carvalho de Melo struct drm_i915_engine_info engines[]; 333195dc663aSArnaldo Carvalho de Melo }; 333295dc663aSArnaldo Carvalho de Melo 33330fdd435cSArnaldo Carvalho de Melo /** 33340fdd435cSArnaldo Carvalho de Melo * struct drm_i915_query_perf_config 33350fdd435cSArnaldo Carvalho de Melo * 33360fdd435cSArnaldo Carvalho de Melo * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and 33370fdd435cSArnaldo Carvalho de Melo * %DRM_I915_QUERY_GEOMETRY_SUBSLICES. 33380b3fca6aSArnaldo Carvalho de Melo */ 33390b3fca6aSArnaldo Carvalho de Melo struct drm_i915_query_perf_config { 33400b3fca6aSArnaldo Carvalho de Melo union { 33410fdd435cSArnaldo Carvalho de Melo /** 33420fdd435cSArnaldo Carvalho de Melo * @n_configs: 33430fdd435cSArnaldo Carvalho de Melo * 33440fdd435cSArnaldo Carvalho de Melo * When &drm_i915_query_item.flags == 33450fdd435cSArnaldo Carvalho de Melo * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to 33460fdd435cSArnaldo Carvalho de Melo * the number of configurations available. 33470b3fca6aSArnaldo Carvalho de Melo */ 33480b3fca6aSArnaldo Carvalho de Melo __u64 n_configs; 33490b3fca6aSArnaldo Carvalho de Melo 33500fdd435cSArnaldo Carvalho de Melo /** 33510fdd435cSArnaldo Carvalho de Melo * @config: 33520fdd435cSArnaldo Carvalho de Melo * 33530fdd435cSArnaldo Carvalho de Melo * When &drm_i915_query_item.flags == 33540fdd435cSArnaldo Carvalho de Melo * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the 33550fdd435cSArnaldo Carvalho de Melo * value in this field as configuration identifier to decide 33560fdd435cSArnaldo Carvalho de Melo * what data to write into config_ptr. 33570b3fca6aSArnaldo Carvalho de Melo */ 33580b3fca6aSArnaldo Carvalho de Melo __u64 config; 33590b3fca6aSArnaldo Carvalho de Melo 33600fdd435cSArnaldo Carvalho de Melo /** 33610fdd435cSArnaldo Carvalho de Melo * @uuid: 33620fdd435cSArnaldo Carvalho de Melo * 33630fdd435cSArnaldo Carvalho de Melo * When &drm_i915_query_item.flags == 33640fdd435cSArnaldo Carvalho de Melo * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the 33650fdd435cSArnaldo Carvalho de Melo * value in this field as configuration identifier to decide 33660fdd435cSArnaldo Carvalho de Melo * what data to write into config_ptr. 33670b3fca6aSArnaldo Carvalho de Melo * 33680b3fca6aSArnaldo Carvalho de Melo * String formatted like "%08x-%04x-%04x-%04x-%012x" 33690b3fca6aSArnaldo Carvalho de Melo */ 33700b3fca6aSArnaldo Carvalho de Melo char uuid[36]; 33710b3fca6aSArnaldo Carvalho de Melo }; 33720b3fca6aSArnaldo Carvalho de Melo 33730fdd435cSArnaldo Carvalho de Melo /** 33740fdd435cSArnaldo Carvalho de Melo * @flags: 33750fdd435cSArnaldo Carvalho de Melo * 33760b3fca6aSArnaldo Carvalho de Melo * Unused for now. Must be cleared to zero. 33770b3fca6aSArnaldo Carvalho de Melo */ 33780b3fca6aSArnaldo Carvalho de Melo __u32 flags; 33790b3fca6aSArnaldo Carvalho de Melo 33800fdd435cSArnaldo Carvalho de Melo /** 33810fdd435cSArnaldo Carvalho de Melo * @data: 33820b3fca6aSArnaldo Carvalho de Melo * 33830fdd435cSArnaldo Carvalho de Melo * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST, 33840fdd435cSArnaldo Carvalho de Melo * i915 will write an array of __u64 of configuration identifiers. 33850fdd435cSArnaldo Carvalho de Melo * 33860fdd435cSArnaldo Carvalho de Melo * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA, 33870fdd435cSArnaldo Carvalho de Melo * i915 will write a struct drm_i915_perf_oa_config. If the following 33880fdd435cSArnaldo Carvalho de Melo * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will 33890fdd435cSArnaldo Carvalho de Melo * write into the associated pointers the values of submitted when the 33900b3fca6aSArnaldo Carvalho de Melo * configuration was created : 33910b3fca6aSArnaldo Carvalho de Melo * 33920fdd435cSArnaldo Carvalho de Melo * - &drm_i915_perf_oa_config.n_mux_regs 33930fdd435cSArnaldo Carvalho de Melo * - &drm_i915_perf_oa_config.n_boolean_regs 33940fdd435cSArnaldo Carvalho de Melo * - &drm_i915_perf_oa_config.n_flex_regs 33950b3fca6aSArnaldo Carvalho de Melo */ 33960b3fca6aSArnaldo Carvalho de Melo __u8 data[]; 33970b3fca6aSArnaldo Carvalho de Melo }; 33980b3fca6aSArnaldo Carvalho de Melo 33994a1cddeaSArnaldo Carvalho de Melo /** 34004a1cddeaSArnaldo Carvalho de Melo * enum drm_i915_gem_memory_class - Supported memory classes 34014a1cddeaSArnaldo Carvalho de Melo */ 34024a1cddeaSArnaldo Carvalho de Melo enum drm_i915_gem_memory_class { 34034a1cddeaSArnaldo Carvalho de Melo /** @I915_MEMORY_CLASS_SYSTEM: System memory */ 34044a1cddeaSArnaldo Carvalho de Melo I915_MEMORY_CLASS_SYSTEM = 0, 34054a1cddeaSArnaldo Carvalho de Melo /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ 34064a1cddeaSArnaldo Carvalho de Melo I915_MEMORY_CLASS_DEVICE, 34074a1cddeaSArnaldo Carvalho de Melo }; 34084a1cddeaSArnaldo Carvalho de Melo 34094a1cddeaSArnaldo Carvalho de Melo /** 34104a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_memory_class_instance - Identify particular memory region 34114a1cddeaSArnaldo Carvalho de Melo */ 34124a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_memory_class_instance { 34134a1cddeaSArnaldo Carvalho de Melo /** @memory_class: See enum drm_i915_gem_memory_class */ 34144a1cddeaSArnaldo Carvalho de Melo __u16 memory_class; 34154a1cddeaSArnaldo Carvalho de Melo 34164a1cddeaSArnaldo Carvalho de Melo /** @memory_instance: Which instance */ 34174a1cddeaSArnaldo Carvalho de Melo __u16 memory_instance; 34184a1cddeaSArnaldo Carvalho de Melo }; 34194a1cddeaSArnaldo Carvalho de Melo 34204a1cddeaSArnaldo Carvalho de Melo /** 34214a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_memory_region_info - Describes one region as known to the 34224a1cddeaSArnaldo Carvalho de Melo * driver. 34234a1cddeaSArnaldo Carvalho de Melo * 34244a1cddeaSArnaldo Carvalho de Melo * Note this is using both struct drm_i915_query_item and struct drm_i915_query. 34254a1cddeaSArnaldo Carvalho de Melo * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS 34264a1cddeaSArnaldo Carvalho de Melo * at &drm_i915_query_item.query_id. 34274a1cddeaSArnaldo Carvalho de Melo */ 34284a1cddeaSArnaldo Carvalho de Melo struct drm_i915_memory_region_info { 34294a1cddeaSArnaldo Carvalho de Melo /** @region: The class:instance pair encoding */ 34304a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_memory_class_instance region; 34314a1cddeaSArnaldo Carvalho de Melo 34324a1cddeaSArnaldo Carvalho de Melo /** @rsvd0: MBZ */ 34334a1cddeaSArnaldo Carvalho de Melo __u32 rsvd0; 34344a1cddeaSArnaldo Carvalho de Melo 343554cd4cdeSArnaldo Carvalho de Melo /** 343654cd4cdeSArnaldo Carvalho de Melo * @probed_size: Memory probed by the driver 343754cd4cdeSArnaldo Carvalho de Melo * 343854cd4cdeSArnaldo Carvalho de Melo * Note that it should not be possible to ever encounter a zero value 343954cd4cdeSArnaldo Carvalho de Melo * here, also note that no current region type will ever return -1 here. 344054cd4cdeSArnaldo Carvalho de Melo * Although for future region types, this might be a possibility. The 344154cd4cdeSArnaldo Carvalho de Melo * same applies to the other size fields. 344254cd4cdeSArnaldo Carvalho de Melo */ 34434a1cddeaSArnaldo Carvalho de Melo __u64 probed_size; 34444a1cddeaSArnaldo Carvalho de Melo 344554cd4cdeSArnaldo Carvalho de Melo /** 344654cd4cdeSArnaldo Carvalho de Melo * @unallocated_size: Estimate of memory remaining 344754cd4cdeSArnaldo Carvalho de Melo * 344854cd4cdeSArnaldo Carvalho de Melo * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. 344954cd4cdeSArnaldo Carvalho de Melo * Without this (or if this is an older kernel) the value here will 345054cd4cdeSArnaldo Carvalho de Melo * always equal the @probed_size. Note this is only currently tracked 345154cd4cdeSArnaldo Carvalho de Melo * for I915_MEMORY_CLASS_DEVICE regions (for other types the value here 345254cd4cdeSArnaldo Carvalho de Melo * will always equal the @probed_size). 345354cd4cdeSArnaldo Carvalho de Melo */ 34544a1cddeaSArnaldo Carvalho de Melo __u64 unallocated_size; 34554a1cddeaSArnaldo Carvalho de Melo 345654cd4cdeSArnaldo Carvalho de Melo union { 34574a1cddeaSArnaldo Carvalho de Melo /** @rsvd1: MBZ */ 34584a1cddeaSArnaldo Carvalho de Melo __u64 rsvd1[8]; 345954cd4cdeSArnaldo Carvalho de Melo struct { 346054cd4cdeSArnaldo Carvalho de Melo /** 346154cd4cdeSArnaldo Carvalho de Melo * @probed_cpu_visible_size: Memory probed by the driver 346254cd4cdeSArnaldo Carvalho de Melo * that is CPU accessible. 346354cd4cdeSArnaldo Carvalho de Melo * 346454cd4cdeSArnaldo Carvalho de Melo * This will be always be <= @probed_size, and the 346554cd4cdeSArnaldo Carvalho de Melo * remainder (if there is any) will not be CPU 346654cd4cdeSArnaldo Carvalho de Melo * accessible. 346754cd4cdeSArnaldo Carvalho de Melo * 346854cd4cdeSArnaldo Carvalho de Melo * On systems without small BAR, the @probed_size will 346954cd4cdeSArnaldo Carvalho de Melo * always equal the @probed_cpu_visible_size, since all 347054cd4cdeSArnaldo Carvalho de Melo * of it will be CPU accessible. 347154cd4cdeSArnaldo Carvalho de Melo * 347254cd4cdeSArnaldo Carvalho de Melo * Note this is only tracked for 347354cd4cdeSArnaldo Carvalho de Melo * I915_MEMORY_CLASS_DEVICE regions (for other types the 347454cd4cdeSArnaldo Carvalho de Melo * value here will always equal the @probed_size). 347554cd4cdeSArnaldo Carvalho de Melo * 347654cd4cdeSArnaldo Carvalho de Melo * Note that if the value returned here is zero, then 347754cd4cdeSArnaldo Carvalho de Melo * this must be an old kernel which lacks the relevant 347854cd4cdeSArnaldo Carvalho de Melo * small-bar uAPI support (including 347954cd4cdeSArnaldo Carvalho de Melo * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on 348054cd4cdeSArnaldo Carvalho de Melo * such systems we should never actually end up with a 348154cd4cdeSArnaldo Carvalho de Melo * small BAR configuration, assuming we are able to load 348254cd4cdeSArnaldo Carvalho de Melo * the kernel module. Hence it should be safe to treat 348354cd4cdeSArnaldo Carvalho de Melo * this the same as when @probed_cpu_visible_size == 348454cd4cdeSArnaldo Carvalho de Melo * @probed_size. 348554cd4cdeSArnaldo Carvalho de Melo */ 348654cd4cdeSArnaldo Carvalho de Melo __u64 probed_cpu_visible_size; 348754cd4cdeSArnaldo Carvalho de Melo 348854cd4cdeSArnaldo Carvalho de Melo /** 348954cd4cdeSArnaldo Carvalho de Melo * @unallocated_cpu_visible_size: Estimate of CPU 349054cd4cdeSArnaldo Carvalho de Melo * visible memory remaining. 349154cd4cdeSArnaldo Carvalho de Melo * 349254cd4cdeSArnaldo Carvalho de Melo * Note this is only tracked for 349354cd4cdeSArnaldo Carvalho de Melo * I915_MEMORY_CLASS_DEVICE regions (for other types the 349454cd4cdeSArnaldo Carvalho de Melo * value here will always equal the 349554cd4cdeSArnaldo Carvalho de Melo * @probed_cpu_visible_size). 349654cd4cdeSArnaldo Carvalho de Melo * 349754cd4cdeSArnaldo Carvalho de Melo * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 349854cd4cdeSArnaldo Carvalho de Melo * accounting. Without this the value here will always 349954cd4cdeSArnaldo Carvalho de Melo * equal the @probed_cpu_visible_size. Note this is only 350054cd4cdeSArnaldo Carvalho de Melo * currently tracked for I915_MEMORY_CLASS_DEVICE 350154cd4cdeSArnaldo Carvalho de Melo * regions (for other types the value here will also 350254cd4cdeSArnaldo Carvalho de Melo * always equal the @probed_cpu_visible_size). 350354cd4cdeSArnaldo Carvalho de Melo * 350454cd4cdeSArnaldo Carvalho de Melo * If this is an older kernel the value here will be 350554cd4cdeSArnaldo Carvalho de Melo * zero, see also @probed_cpu_visible_size. 350654cd4cdeSArnaldo Carvalho de Melo */ 350754cd4cdeSArnaldo Carvalho de Melo __u64 unallocated_cpu_visible_size; 350854cd4cdeSArnaldo Carvalho de Melo }; 350954cd4cdeSArnaldo Carvalho de Melo }; 35104a1cddeaSArnaldo Carvalho de Melo }; 35114a1cddeaSArnaldo Carvalho de Melo 35124a1cddeaSArnaldo Carvalho de Melo /** 35134a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_memory_regions 35144a1cddeaSArnaldo Carvalho de Melo * 35154a1cddeaSArnaldo Carvalho de Melo * The region info query enumerates all regions known to the driver by filling 35164a1cddeaSArnaldo Carvalho de Melo * in an array of struct drm_i915_memory_region_info structures. 35174a1cddeaSArnaldo Carvalho de Melo * 35184a1cddeaSArnaldo Carvalho de Melo * Example for getting the list of supported regions: 35194a1cddeaSArnaldo Carvalho de Melo * 35204a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 35214a1cddeaSArnaldo Carvalho de Melo * 35224a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_memory_regions *info; 35234a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query_item item = { 35244a1cddeaSArnaldo Carvalho de Melo * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; 35254a1cddeaSArnaldo Carvalho de Melo * }; 35264a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_query query = { 35274a1cddeaSArnaldo Carvalho de Melo * .num_items = 1, 35284a1cddeaSArnaldo Carvalho de Melo * .items_ptr = (uintptr_t)&item, 35294a1cddeaSArnaldo Carvalho de Melo * }; 35304a1cddeaSArnaldo Carvalho de Melo * int err, i; 35314a1cddeaSArnaldo Carvalho de Melo * 35324a1cddeaSArnaldo Carvalho de Melo * // First query the size of the blob we need, this needs to be large 35334a1cddeaSArnaldo Carvalho de Melo * // enough to hold our array of regions. The kernel will fill out the 35344a1cddeaSArnaldo Carvalho de Melo * // item.length for us, which is the number of bytes we need. 35354a1cddeaSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 35364a1cddeaSArnaldo Carvalho de Melo * if (err) ... 35374a1cddeaSArnaldo Carvalho de Melo * 35384a1cddeaSArnaldo Carvalho de Melo * info = calloc(1, item.length); 35394a1cddeaSArnaldo Carvalho de Melo * // Now that we allocated the required number of bytes, we call the ioctl 35404a1cddeaSArnaldo Carvalho de Melo * // again, this time with the data_ptr pointing to our newly allocated 35414a1cddeaSArnaldo Carvalho de Melo * // blob, which the kernel can then populate with the all the region info. 35424a1cddeaSArnaldo Carvalho de Melo * item.data_ptr = (uintptr_t)&info, 35434a1cddeaSArnaldo Carvalho de Melo * 35444a1cddeaSArnaldo Carvalho de Melo * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 35454a1cddeaSArnaldo Carvalho de Melo * if (err) ... 35464a1cddeaSArnaldo Carvalho de Melo * 35474a1cddeaSArnaldo Carvalho de Melo * // We can now access each region in the array 35484a1cddeaSArnaldo Carvalho de Melo * for (i = 0; i < info->num_regions; i++) { 35494a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_memory_region_info mr = info->regions[i]; 35504a1cddeaSArnaldo Carvalho de Melo * u16 class = mr.region.class; 35514a1cddeaSArnaldo Carvalho de Melo * u16 instance = mr.region.instance; 35524a1cddeaSArnaldo Carvalho de Melo * 35534a1cddeaSArnaldo Carvalho de Melo * .... 35544a1cddeaSArnaldo Carvalho de Melo * } 35554a1cddeaSArnaldo Carvalho de Melo * 35564a1cddeaSArnaldo Carvalho de Melo * free(info); 35574a1cddeaSArnaldo Carvalho de Melo */ 35584a1cddeaSArnaldo Carvalho de Melo struct drm_i915_query_memory_regions { 35594a1cddeaSArnaldo Carvalho de Melo /** @num_regions: Number of supported regions */ 35604a1cddeaSArnaldo Carvalho de Melo __u32 num_regions; 35614a1cddeaSArnaldo Carvalho de Melo 35624a1cddeaSArnaldo Carvalho de Melo /** @rsvd: MBZ */ 35634a1cddeaSArnaldo Carvalho de Melo __u32 rsvd[3]; 35644a1cddeaSArnaldo Carvalho de Melo 35654a1cddeaSArnaldo Carvalho de Melo /** @regions: Info about each supported region */ 35664a1cddeaSArnaldo Carvalho de Melo struct drm_i915_memory_region_info regions[]; 35674a1cddeaSArnaldo Carvalho de Melo }; 35684a1cddeaSArnaldo Carvalho de Melo 35694a1cddeaSArnaldo Carvalho de Melo /** 35700fdd435cSArnaldo Carvalho de Melo * DOC: GuC HWCONFIG blob uAPI 35710fdd435cSArnaldo Carvalho de Melo * 35720fdd435cSArnaldo Carvalho de Melo * The GuC produces a blob with information about the current device. 35730fdd435cSArnaldo Carvalho de Melo * i915 reads this blob from GuC and makes it available via this uAPI. 35740fdd435cSArnaldo Carvalho de Melo * 35750fdd435cSArnaldo Carvalho de Melo * The format and meaning of the blob content are documented in the 35760fdd435cSArnaldo Carvalho de Melo * Programmer's Reference Manual. 35770fdd435cSArnaldo Carvalho de Melo */ 35780fdd435cSArnaldo Carvalho de Melo 35790fdd435cSArnaldo Carvalho de Melo /** 35804a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added 35814a1cddeaSArnaldo Carvalho de Melo * extension support using struct i915_user_extension. 35824a1cddeaSArnaldo Carvalho de Melo * 358354cd4cdeSArnaldo Carvalho de Melo * Note that new buffer flags should be added here, at least for the stuff that 358454cd4cdeSArnaldo Carvalho de Melo * is immutable. Previously we would have two ioctls, one to create the object 358554cd4cdeSArnaldo Carvalho de Melo * with gem_create, and another to apply various parameters, however this 358654cd4cdeSArnaldo Carvalho de Melo * creates some ambiguity for the params which are considered immutable. Also in 358754cd4cdeSArnaldo Carvalho de Melo * general we're phasing out the various SET/GET ioctls. 35884a1cddeaSArnaldo Carvalho de Melo */ 35894a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_create_ext { 35904a1cddeaSArnaldo Carvalho de Melo /** 35914a1cddeaSArnaldo Carvalho de Melo * @size: Requested size for the object. 35924a1cddeaSArnaldo Carvalho de Melo * 35934a1cddeaSArnaldo Carvalho de Melo * The (page-aligned) allocated size for the object will be returned. 35944a1cddeaSArnaldo Carvalho de Melo * 3595eeac18e2SArnaldo Carvalho de Melo * On platforms like DG2/ATS the kernel will always use 64K or larger 3596eeac18e2SArnaldo Carvalho de Melo * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a 3597eeac18e2SArnaldo Carvalho de Melo * minimum of 64K GTT alignment for such objects. 3598f444b2d1SArnaldo Carvalho de Melo * 3599eeac18e2SArnaldo Carvalho de Melo * NOTE: Previously the ABI here required a minimum GTT alignment of 2M 3600eeac18e2SArnaldo Carvalho de Melo * on DG2/ATS, due to how the hardware implemented 64K GTT page support, 3601eeac18e2SArnaldo Carvalho de Melo * where we had the following complications: 3602f444b2d1SArnaldo Carvalho de Melo * 3603f444b2d1SArnaldo Carvalho de Melo * 1) The entire PDE (which covers a 2MB virtual address range), must 3604f444b2d1SArnaldo Carvalho de Melo * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same 3605f444b2d1SArnaldo Carvalho de Melo * PDE is forbidden by the hardware. 3606f444b2d1SArnaldo Carvalho de Melo * 3607f444b2d1SArnaldo Carvalho de Melo * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM 3608f444b2d1SArnaldo Carvalho de Melo * objects. 3609f444b2d1SArnaldo Carvalho de Melo * 3610eeac18e2SArnaldo Carvalho de Melo * However on actual production HW this was completely changed to now 3611eeac18e2SArnaldo Carvalho de Melo * allow setting a TLB hint at the PTE level (see PS64), which is a lot 3612eeac18e2SArnaldo Carvalho de Melo * more flexible than the above. With this the 2M restriction was 3613eeac18e2SArnaldo Carvalho de Melo * dropped where we now only require 64K. 36144a1cddeaSArnaldo Carvalho de Melo */ 36154a1cddeaSArnaldo Carvalho de Melo __u64 size; 361654cd4cdeSArnaldo Carvalho de Melo 36174a1cddeaSArnaldo Carvalho de Melo /** 36184a1cddeaSArnaldo Carvalho de Melo * @handle: Returned handle for the object. 36194a1cddeaSArnaldo Carvalho de Melo * 36204a1cddeaSArnaldo Carvalho de Melo * Object handles are nonzero. 36214a1cddeaSArnaldo Carvalho de Melo */ 36224a1cddeaSArnaldo Carvalho de Melo __u32 handle; 362354cd4cdeSArnaldo Carvalho de Melo 362454cd4cdeSArnaldo Carvalho de Melo /** 362554cd4cdeSArnaldo Carvalho de Melo * @flags: Optional flags. 362654cd4cdeSArnaldo Carvalho de Melo * 362754cd4cdeSArnaldo Carvalho de Melo * Supported values: 362854cd4cdeSArnaldo Carvalho de Melo * 362954cd4cdeSArnaldo Carvalho de Melo * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that 363054cd4cdeSArnaldo Carvalho de Melo * the object will need to be accessed via the CPU. 363154cd4cdeSArnaldo Carvalho de Melo * 363254cd4cdeSArnaldo Carvalho de Melo * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only 363354cd4cdeSArnaldo Carvalho de Melo * strictly required on configurations where some subset of the device 363454cd4cdeSArnaldo Carvalho de Melo * memory is directly visible/mappable through the CPU (which we also 363554cd4cdeSArnaldo Carvalho de Melo * call small BAR), like on some DG2+ systems. Note that this is quite 363654cd4cdeSArnaldo Carvalho de Melo * undesirable, but due to various factors like the client CPU, BIOS etc 363754cd4cdeSArnaldo Carvalho de Melo * it's something we can expect to see in the wild. See 363854cd4cdeSArnaldo Carvalho de Melo * &drm_i915_memory_region_info.probed_cpu_visible_size for how to 363954cd4cdeSArnaldo Carvalho de Melo * determine if this system applies. 364054cd4cdeSArnaldo Carvalho de Melo * 364154cd4cdeSArnaldo Carvalho de Melo * Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to 364254cd4cdeSArnaldo Carvalho de Melo * ensure the kernel can always spill the allocation to system memory, 364354cd4cdeSArnaldo Carvalho de Melo * if the object can't be allocated in the mappable part of 364454cd4cdeSArnaldo Carvalho de Melo * I915_MEMORY_CLASS_DEVICE. 364554cd4cdeSArnaldo Carvalho de Melo * 364654cd4cdeSArnaldo Carvalho de Melo * Also note that since the kernel only supports flat-CCS on objects 364754cd4cdeSArnaldo Carvalho de Melo * that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore 364854cd4cdeSArnaldo Carvalho de Melo * don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with 364954cd4cdeSArnaldo Carvalho de Melo * flat-CCS. 365054cd4cdeSArnaldo Carvalho de Melo * 365154cd4cdeSArnaldo Carvalho de Melo * Without this hint, the kernel will assume that non-mappable 365254cd4cdeSArnaldo Carvalho de Melo * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the 365354cd4cdeSArnaldo Carvalho de Melo * kernel can still migrate the object to the mappable part, as a last 365454cd4cdeSArnaldo Carvalho de Melo * resort, if userspace ever CPU faults this object, but this might be 365554cd4cdeSArnaldo Carvalho de Melo * expensive, and so ideally should be avoided. 365654cd4cdeSArnaldo Carvalho de Melo * 365754cd4cdeSArnaldo Carvalho de Melo * On older kernels which lack the relevant small-bar uAPI support (see 365854cd4cdeSArnaldo Carvalho de Melo * also &drm_i915_memory_region_info.probed_cpu_visible_size), 365954cd4cdeSArnaldo Carvalho de Melo * usage of the flag will result in an error, but it should NEVER be 366054cd4cdeSArnaldo Carvalho de Melo * possible to end up with a small BAR configuration, assuming we can 366154cd4cdeSArnaldo Carvalho de Melo * also successfully load the i915 kernel module. In such cases the 366254cd4cdeSArnaldo Carvalho de Melo * entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as 366354cd4cdeSArnaldo Carvalho de Melo * such there are zero restrictions on where the object can be placed. 366454cd4cdeSArnaldo Carvalho de Melo */ 366554cd4cdeSArnaldo Carvalho de Melo #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) 36664a1cddeaSArnaldo Carvalho de Melo __u32 flags; 366754cd4cdeSArnaldo Carvalho de Melo 36684a1cddeaSArnaldo Carvalho de Melo /** 36694a1cddeaSArnaldo Carvalho de Melo * @extensions: The chain of extensions to apply to this object. 36704a1cddeaSArnaldo Carvalho de Melo * 36714a1cddeaSArnaldo Carvalho de Melo * This will be useful in the future when we need to support several 36724a1cddeaSArnaldo Carvalho de Melo * different extensions, and we need to apply more than one when 36734a1cddeaSArnaldo Carvalho de Melo * creating the object. See struct i915_user_extension. 36744a1cddeaSArnaldo Carvalho de Melo * 36754a1cddeaSArnaldo Carvalho de Melo * If we don't supply any extensions then we get the same old gem_create 36764a1cddeaSArnaldo Carvalho de Melo * behaviour. 36774a1cddeaSArnaldo Carvalho de Melo * 36784a1cddeaSArnaldo Carvalho de Melo * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see 36794a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions. 368006cf00c4SArnaldo Carvalho de Melo * 368106cf00c4SArnaldo Carvalho de Melo * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see 368206cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_protected_content. 3683*142256d2SArnaldo Carvalho de Melo * 3684*142256d2SArnaldo Carvalho de Melo * For I915_GEM_CREATE_EXT_SET_PAT usage see 3685*142256d2SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_set_pat. 36864a1cddeaSArnaldo Carvalho de Melo */ 36874a1cddeaSArnaldo Carvalho de Melo #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 368806cf00c4SArnaldo Carvalho de Melo #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 3689*142256d2SArnaldo Carvalho de Melo #define I915_GEM_CREATE_EXT_SET_PAT 2 36904a1cddeaSArnaldo Carvalho de Melo __u64 extensions; 36914a1cddeaSArnaldo Carvalho de Melo }; 36924a1cddeaSArnaldo Carvalho de Melo 36934a1cddeaSArnaldo Carvalho de Melo /** 36944a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions - The 36954a1cddeaSArnaldo Carvalho de Melo * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. 36964a1cddeaSArnaldo Carvalho de Melo * 36974a1cddeaSArnaldo Carvalho de Melo * Set the object with the desired set of placements/regions in priority 36984a1cddeaSArnaldo Carvalho de Melo * order. Each entry must be unique and supported by the device. 36994a1cddeaSArnaldo Carvalho de Melo * 37004a1cddeaSArnaldo Carvalho de Melo * This is provided as an array of struct drm_i915_gem_memory_class_instance, or 37014a1cddeaSArnaldo Carvalho de Melo * an equivalent layout of class:instance pair encodings. See struct 37024a1cddeaSArnaldo Carvalho de Melo * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to 37034a1cddeaSArnaldo Carvalho de Melo * query the supported regions for a device. 37044a1cddeaSArnaldo Carvalho de Melo * 37054a1cddeaSArnaldo Carvalho de Melo * As an example, on discrete devices, if we wish to set the placement as 37064a1cddeaSArnaldo Carvalho de Melo * device local-memory we can do something like: 37074a1cddeaSArnaldo Carvalho de Melo * 37084a1cddeaSArnaldo Carvalho de Melo * .. code-block:: C 37094a1cddeaSArnaldo Carvalho de Melo * 37104a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_memory_class_instance region_lmem = { 37114a1cddeaSArnaldo Carvalho de Melo * .memory_class = I915_MEMORY_CLASS_DEVICE, 37124a1cddeaSArnaldo Carvalho de Melo * .memory_instance = 0, 37134a1cddeaSArnaldo Carvalho de Melo * }; 37144a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_memory_regions regions = { 37154a1cddeaSArnaldo Carvalho de Melo * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, 37164a1cddeaSArnaldo Carvalho de Melo * .regions = (uintptr_t)®ion_lmem, 37174a1cddeaSArnaldo Carvalho de Melo * .num_regions = 1, 37184a1cddeaSArnaldo Carvalho de Melo * }; 37194a1cddeaSArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext create_ext = { 37204a1cddeaSArnaldo Carvalho de Melo * .size = 16 * PAGE_SIZE, 37214a1cddeaSArnaldo Carvalho de Melo * .extensions = (uintptr_t)®ions, 37224a1cddeaSArnaldo Carvalho de Melo * }; 37234a1cddeaSArnaldo Carvalho de Melo * 37244a1cddeaSArnaldo Carvalho de Melo * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 37254a1cddeaSArnaldo Carvalho de Melo * if (err) ... 37264a1cddeaSArnaldo Carvalho de Melo * 37274a1cddeaSArnaldo Carvalho de Melo * At which point we get the object handle in &drm_i915_gem_create_ext.handle, 37284a1cddeaSArnaldo Carvalho de Melo * along with the final object size in &drm_i915_gem_create_ext.size, which 37294a1cddeaSArnaldo Carvalho de Melo * should account for any rounding up, if required. 373054cd4cdeSArnaldo Carvalho de Melo * 373154cd4cdeSArnaldo Carvalho de Melo * Note that userspace has no means of knowing the current backing region 373254cd4cdeSArnaldo Carvalho de Melo * for objects where @num_regions is larger than one. The kernel will only 373354cd4cdeSArnaldo Carvalho de Melo * ensure that the priority order of the @regions array is honoured, either 373454cd4cdeSArnaldo Carvalho de Melo * when initially placing the object, or when moving memory around due to 373554cd4cdeSArnaldo Carvalho de Melo * memory pressure 373654cd4cdeSArnaldo Carvalho de Melo * 373754cd4cdeSArnaldo Carvalho de Melo * On Flat-CCS capable HW, compression is supported for the objects residing 373854cd4cdeSArnaldo Carvalho de Melo * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other 373954cd4cdeSArnaldo Carvalho de Melo * memory class in @regions and migrated (by i915, due to memory 374054cd4cdeSArnaldo Carvalho de Melo * constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to 374154cd4cdeSArnaldo Carvalho de Melo * decompress the content. But i915 doesn't have the required information to 374254cd4cdeSArnaldo Carvalho de Melo * decompress the userspace compressed objects. 374354cd4cdeSArnaldo Carvalho de Melo * 374454cd4cdeSArnaldo Carvalho de Melo * So i915 supports Flat-CCS, on the objects which can reside only on 374554cd4cdeSArnaldo Carvalho de Melo * I915_MEMORY_CLASS_DEVICE regions. 37464a1cddeaSArnaldo Carvalho de Melo */ 37474a1cddeaSArnaldo Carvalho de Melo struct drm_i915_gem_create_ext_memory_regions { 37484a1cddeaSArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 37494a1cddeaSArnaldo Carvalho de Melo struct i915_user_extension base; 37504a1cddeaSArnaldo Carvalho de Melo 37514a1cddeaSArnaldo Carvalho de Melo /** @pad: MBZ */ 37524a1cddeaSArnaldo Carvalho de Melo __u32 pad; 37534a1cddeaSArnaldo Carvalho de Melo /** @num_regions: Number of elements in the @regions array. */ 37544a1cddeaSArnaldo Carvalho de Melo __u32 num_regions; 37554a1cddeaSArnaldo Carvalho de Melo /** 37564a1cddeaSArnaldo Carvalho de Melo * @regions: The regions/placements array. 37574a1cddeaSArnaldo Carvalho de Melo * 37584a1cddeaSArnaldo Carvalho de Melo * An array of struct drm_i915_gem_memory_class_instance. 37594a1cddeaSArnaldo Carvalho de Melo */ 37604a1cddeaSArnaldo Carvalho de Melo __u64 regions; 37614a1cddeaSArnaldo Carvalho de Melo }; 37624a1cddeaSArnaldo Carvalho de Melo 376306cf00c4SArnaldo Carvalho de Melo /** 376406cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_protected_content - The 376506cf00c4SArnaldo Carvalho de Melo * I915_OBJECT_PARAM_PROTECTED_CONTENT extension. 376606cf00c4SArnaldo Carvalho de Melo * 376706cf00c4SArnaldo Carvalho de Melo * If this extension is provided, buffer contents are expected to be protected 376806cf00c4SArnaldo Carvalho de Melo * by PXP encryption and require decryption for scan out and processing. This 376906cf00c4SArnaldo Carvalho de Melo * is only possible on platforms that have PXP enabled, on all other scenarios 377006cf00c4SArnaldo Carvalho de Melo * using this extension will cause the ioctl to fail and return -ENODEV. The 377106cf00c4SArnaldo Carvalho de Melo * flags parameter is reserved for future expansion and must currently be set 377206cf00c4SArnaldo Carvalho de Melo * to zero. 377306cf00c4SArnaldo Carvalho de Melo * 377406cf00c4SArnaldo Carvalho de Melo * The buffer contents are considered invalid after a PXP session teardown. 377506cf00c4SArnaldo Carvalho de Melo * 377606cf00c4SArnaldo Carvalho de Melo * The encryption is guaranteed to be processed correctly only if the object 377706cf00c4SArnaldo Carvalho de Melo * is submitted with a context created using the 377806cf00c4SArnaldo Carvalho de Melo * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks 377906cf00c4SArnaldo Carvalho de Melo * at submission time on the validity of the objects involved. 378006cf00c4SArnaldo Carvalho de Melo * 378106cf00c4SArnaldo Carvalho de Melo * Below is an example on how to create a protected object: 378206cf00c4SArnaldo Carvalho de Melo * 378306cf00c4SArnaldo Carvalho de Melo * .. code-block:: C 378406cf00c4SArnaldo Carvalho de Melo * 378506cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_protected_content protected_ext = { 378606cf00c4SArnaldo Carvalho de Melo * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, 378706cf00c4SArnaldo Carvalho de Melo * .flags = 0, 378806cf00c4SArnaldo Carvalho de Melo * }; 378906cf00c4SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext create_ext = { 379006cf00c4SArnaldo Carvalho de Melo * .size = PAGE_SIZE, 379106cf00c4SArnaldo Carvalho de Melo * .extensions = (uintptr_t)&protected_ext, 379206cf00c4SArnaldo Carvalho de Melo * }; 379306cf00c4SArnaldo Carvalho de Melo * 379406cf00c4SArnaldo Carvalho de Melo * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 379506cf00c4SArnaldo Carvalho de Melo * if (err) ... 379606cf00c4SArnaldo Carvalho de Melo */ 379706cf00c4SArnaldo Carvalho de Melo struct drm_i915_gem_create_ext_protected_content { 379806cf00c4SArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 379906cf00c4SArnaldo Carvalho de Melo struct i915_user_extension base; 380006cf00c4SArnaldo Carvalho de Melo /** @flags: reserved for future usage, currently MBZ */ 380106cf00c4SArnaldo Carvalho de Melo __u32 flags; 380206cf00c4SArnaldo Carvalho de Melo }; 380306cf00c4SArnaldo Carvalho de Melo 3804*142256d2SArnaldo Carvalho de Melo /** 3805*142256d2SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_set_pat - The 3806*142256d2SArnaldo Carvalho de Melo * I915_GEM_CREATE_EXT_SET_PAT extension. 3807*142256d2SArnaldo Carvalho de Melo * 3808*142256d2SArnaldo Carvalho de Melo * If this extension is provided, the specified caching policy (PAT index) is 3809*142256d2SArnaldo Carvalho de Melo * applied to the buffer object. 3810*142256d2SArnaldo Carvalho de Melo * 3811*142256d2SArnaldo Carvalho de Melo * Below is an example on how to create an object with specific caching policy: 3812*142256d2SArnaldo Carvalho de Melo * 3813*142256d2SArnaldo Carvalho de Melo * .. code-block:: C 3814*142256d2SArnaldo Carvalho de Melo * 3815*142256d2SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext_set_pat set_pat_ext = { 3816*142256d2SArnaldo Carvalho de Melo * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT }, 3817*142256d2SArnaldo Carvalho de Melo * .pat_index = 0, 3818*142256d2SArnaldo Carvalho de Melo * }; 3819*142256d2SArnaldo Carvalho de Melo * struct drm_i915_gem_create_ext create_ext = { 3820*142256d2SArnaldo Carvalho de Melo * .size = PAGE_SIZE, 3821*142256d2SArnaldo Carvalho de Melo * .extensions = (uintptr_t)&set_pat_ext, 3822*142256d2SArnaldo Carvalho de Melo * }; 3823*142256d2SArnaldo Carvalho de Melo * 3824*142256d2SArnaldo Carvalho de Melo * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 3825*142256d2SArnaldo Carvalho de Melo * if (err) ... 3826*142256d2SArnaldo Carvalho de Melo */ 3827*142256d2SArnaldo Carvalho de Melo struct drm_i915_gem_create_ext_set_pat { 3828*142256d2SArnaldo Carvalho de Melo /** @base: Extension link. See struct i915_user_extension. */ 3829*142256d2SArnaldo Carvalho de Melo struct i915_user_extension base; 3830*142256d2SArnaldo Carvalho de Melo /** 3831*142256d2SArnaldo Carvalho de Melo * @pat_index: PAT index to be set 3832*142256d2SArnaldo Carvalho de Melo * PAT index is a bit field in Page Table Entry to control caching 3833*142256d2SArnaldo Carvalho de Melo * behaviors for GPU accesses. The definition of PAT index is 3834*142256d2SArnaldo Carvalho de Melo * platform dependent and can be found in hardware specifications, 3835*142256d2SArnaldo Carvalho de Melo */ 3836*142256d2SArnaldo Carvalho de Melo __u32 pat_index; 3837*142256d2SArnaldo Carvalho de Melo /** @rsvd: reserved for future use */ 3838*142256d2SArnaldo Carvalho de Melo __u32 rsvd; 3839*142256d2SArnaldo Carvalho de Melo }; 3840*142256d2SArnaldo Carvalho de Melo 384106cf00c4SArnaldo Carvalho de Melo /* ID of the protected content session managed by i915 when PXP is active */ 384206cf00c4SArnaldo Carvalho de Melo #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf 384306cf00c4SArnaldo Carvalho de Melo 3844c1737f2bSArnaldo Carvalho de Melo #if defined(__cplusplus) 3845c1737f2bSArnaldo Carvalho de Melo } 3846c1737f2bSArnaldo Carvalho de Melo #endif 3847c1737f2bSArnaldo Carvalho de Melo 3848c1737f2bSArnaldo Carvalho de Melo #endif /* _UAPI_I915_DRM_H_ */ 3849