| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 1 BYPASS IOMMU PROPERTY
8 is not flexible. We introduce this bypass iommu property to support
14 determine whether the devices attached on the PCI host bridge will bypass
17 bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
22 The bypass iommu feature support PXB host bridge and default main host
26 on AArch64. Other machine types do not support bypass iommu for default
29 1. The following is the bypass iommu options:
34 (3) X86 default root bus bypass iommu:
46 - a default host bridge which bypass SMMUv3
48 - a pxb host bridge which bypass SMMUv3
[all …]
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| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
49 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
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| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | job_service.hpp | 14 Bypass, enumerator
21 {ValidationPolicy::Bypass, "Bypass"},
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| /openbmc/qemu/hw/virtio/ |
| H A D | virtio-iommu.c | 50 bool bypass; member
92 /* need to check bypass before system reset */ in virtio_iommu_device_bypassed()
94 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
100 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
102 bypassed = ep->domain->bypass; in virtio_iommu_device_bypassed()
355 bool bypass) in virtio_iommu_get_domain() argument
361 if (domain->bypass != bypass) { in virtio_iommu_get_domain()
371 domain->bypass = bypass; in virtio_iommu_get_domain()
440 * can have devices to share the same FlatView when in bypass in virtio_iommu_find_add_as()
456 * switch between iommu & bypass MRs by enable/disable in virtio_iommu_find_add_as()
[all …]
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| /openbmc/qemu/tests/qapi-schema/ |
| H A D | type-bypass-bad-gen.err | 1 type-bypass-bad-gen.json: In command 'foo':
2 type-bypass-bad-gen.json:2: flag 'gen' may only use false value
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/ |
| H A D | scp-firmware-juno.inc | 11 …install -D "${B}/${TYPE}/${FW_TARGETS}/bin/${SCP_PLATFORM}-bl1-bypass.bin" "${D}/firmware/${FW}_${…
12 …install -D "${B}/${TYPE}/${FW_TARGETS}/bin/${SCP_PLATFORM}-bl1-bypass.elf" "${D}/firmware/${FW}_${…
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32mp1.txt | 62 0x0: bypass (division by 1)
174 - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
175 - "st,digbypass" Configure the bypass mode as full-swing digital signal
189 st,bypass;
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | system.c | 41 * 1: FIMD Bypass in exynos4_set_system_display()
57 * 1: FIMD Bypass in exynos5_set_system_display()
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| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | lowlevel_init.S | 56 * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
61 * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
270 /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | PhysicalContext.json | 85 "ACMaintenanceBypassInput": "An AC electrical maintenance bypass input.",
87 "ACStaticBypassInput": "An AC electrical static bypass input.",
141 "ACUtilityInput": "This value shall indicate an electrical input, where the source is an electrical utility as opposed to a backup or locally-generated power source. This value is intended to differentiate multiple electrical inputs between utility, maintenance bypass, or static bypass values. For general purpose usage, the value of `ACInput` is preferred.",
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | PhysicalContext.json | 85 "ACMaintenanceBypassInput": "An AC electrical maintenance bypass input.",
87 "ACStaticBypassInput": "An AC electrical static bypass input.",
141 …entiate multiple electrical inputs between utility, maintenance bypass, or static bypass values. …
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| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | fu540-prci.c | 169 * @bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
170 * @no_bypass: fn ptr to code to not bypass the WRPLL (if applicable; else NULL)
173 * @bypass and @no_bypass are used for WRPLL instances that contain a separate
175 * bypass mux is not glitchless.
179 void (*bypass)(struct __prci_data *pd); member
437 if (pwd->bypass) in sifive_fu540_prci_wrpll_set_rate()
438 pwd->bypass(pd); in sifive_fu540_prci_wrpll_set_rate()
487 .bypass = __prci_coreclksel_use_hfclk,
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| H A D | analogbits-wrpll-cln28hpc.h | 30 * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
31 * programmed to enter bypass
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/User/ |
| H A D | TOTPAuthenticator.interface.yaml | 73 User level multi-factor authentication bypass settings. This interface
74 will be implemented by user D-bus object to support user's MFA bypass
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| /openbmc/u-boot/arch/arm/mach-uniphier/dram/ |
| H A D | ddrphy-regs.h | 30 #define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
31 #define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
32 #define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
33 #define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | st-pincfg.h | 43 * Bypass retime with optional delay parameter
45 #define BYPASS (0) macro
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| /openbmc/qemu/include/hw/vfio/ |
| H A D | vfio-platform.h | 38 EventNotifier *unmask; /* eventfd for unmask on QEMU bypass */
44 bool kvm_accel; /* set when QEMU bypass through KVM enabled */
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| /openbmc/u-boot/drivers/ram/aspeed/ |
| H A D | Kconfig | 41 bool "bypass self test during DRAM initialization"
44 Say Y here to bypass DRAM self test to speed up the boot time
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_gen5.c | 16 * function to write the bypass register which requires a poll of the
21 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
51 * Put all plls in bypass
63 * Take all pll's out of bypass
99 /* Put all plls in bypass */ in cm_basic_init()
231 * after locking, but before taking out of bypass in cm_basic_init()
292 /* Take all three PLLs out of bypass when safe mode is cleared. */ in cm_basic_init()
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| H A D | clock_manager_s10.c | 21 * function to write the bypass register which requires a poll of the
26 writel(val, &clock_manager_base->main_pll.bypass); in cm_write_bypass_mainpll()
32 writel(val, &clock_manager_base->per_pll.bypass); in cm_write_bypass_perpll()
53 /* Put all plls in bypass */ in cm_basic_init()
156 /* Take all PLLs out of bypass */ in cm_basic_init()
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| /openbmc/u-boot/drivers/power/ |
| H A D | palmas.c | 78 * LDO9 could be set to 'bypass' mode when required (e.g. for 3.3 V cards).
88 /* Put LDO9 in bypass */ in twl603x_mmc1_set_ldo9()
99 vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err); in twl603x_mmc1_set_ldo9()
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| /openbmc/openbmc/poky/meta/recipes-core/picolibc/picolibc/ |
| H A D | no-early-compiler-checks.cross | 1 # We need to explicitly bypass mesons sanity check to avoid early compiler errors
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| /openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | stream_id_lsch3.h | 51 * BMT[17] 8 // bypass translation
61 #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
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| /openbmc/openbmc/meta-ampere/meta-jade/recipes-ampere/platform/ampere-utils/ |
| H A D | ampere_firmware_upgrade.sh | 9 echo "Bypass fru update as no ampere_fru_upgrade available"
23 echo "Bypass SCP firmware update as no ampere_eeprom_prog available"
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager_s10.h | 76 u32 bypass; member
104 u32 bypass; member
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