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/openbmc/qemu/include/qemu/
H A Dthrottle-options.h7 * See the COPYING file in the top-level directory for details.
13 #define QEMU_OPT_IOPS_TOTAL "iops-total"
14 #define QEMU_OPT_IOPS_TOTAL_MAX "iops-total-max"
15 #define QEMU_OPT_IOPS_TOTAL_MAX_LENGTH "iops-total-max-length"
16 #define QEMU_OPT_IOPS_READ "iops-read"
17 #define QEMU_OPT_IOPS_READ_MAX "iops-read-max"
18 #define QEMU_OPT_IOPS_READ_MAX_LENGTH "iops-read-max-length"
19 #define QEMU_OPT_IOPS_WRITE "iops-write"
20 #define QEMU_OPT_IOPS_WRITE_MAX "iops-write-max"
21 #define QEMU_OPT_IOPS_WRITE_MAX_LENGTH "iops-write-max-length"
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,etop-xway.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
14 pattern: "^ethernet@[0-9a-f]+$"
17 const: lantiq,etop-xway
24 - description: TX interrupt
25 - description: RX interrupt
27 interrupt-names:
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H A Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
18 This is an integer and represents allowable DMA bursts when fixed burst.
19 Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
[all …]
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dstmmac.txt4 - compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
5 For backwards compatibility: "st,spear600-gmac" is also supported.
6 - reg: Address and length of the register set for the device
7 - interrupt-parent: Should be the phandle for the interrupt controller
9 - interrupts: Should contain the STMMAC interrupts
10 - interrupt-names: Should contain the interrupt names "macirq"
13 - phy-mode: See ethernet.txt file in the same directory.
14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
16 - snps,reset-delays-us is triplet of delays
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H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/drivers/video/fbdev/
H A Docfb.c12 #include <linux/dma-mapping.h>
36 #define OCFB_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
41 #define OCFB_CTRL_VBL1 0x00000000 /* Burst Length 1 */
42 #define OCFB_CTRL_VBL2 0x00000080 /* Burst Length 2 */
43 #define OCFB_CTRL_VBL4 0x00000100 /* Burst Length 4 */
44 #define OCFB_CTRL_VBL8 0x00000180 /* Burst Length 8 */
89 if (fbdev->little_endian) in ocfb_readreg()
90 return ioread32(fbdev->regs + offset); in ocfb_readreg()
92 return ioread32be(fbdev->regs + offset); in ocfb_readreg()
97 if (fbdev->little_endian) in ocfb_writereg()
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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H A Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
28 - description: Address range of the DMAC registers
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H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
[all …]
H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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/openbmc/linux/drivers/dma/qcom/
H A Dqcom_adm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
29 /* ADM registers - calculated from channel number and security domain */
99 #define ADM_MAX_XFER (SZ_64K - 1)
100 #define ADM_MAX_ROWS (SZ_64K - 1)
123 size_t length; member
177 * adm_free_chan - Frees dma resources associated with the specific channel
190 * adm_get_blksize - Get block size from burst value
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/openbmc/qemu/util/
H A Dthrottle.c4 * Copyright (C) Nodalink, EURL. 2013-2014
41 leak = (bkt->avg * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
44 bkt->level = MAX(bkt->level - leak, 0); in throttle_leak_bucket()
47 * keep track of bkt->burst_level so the bkt->max goal per second in throttle_leak_bucket()
49 if (bkt->burst_length > 1) { in throttle_leak_bucket()
50 leak = (bkt->max * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
51 bkt->burst_level = MAX(bkt->burst_level - leak, 0); in throttle_leak_bucket()
62 int64_t delta_ns = now - ts->previous_leak; in throttle_do_leak()
65 ts->previous_leak = now; in throttle_do_leak()
73 throttle_leak_bucket(&ts->cfg.buckets[i], delta_ns); in throttle_do_leak()
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/openbmc/linux/drivers/dma/
H A Didma64.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for the Intel integrated DMA 64-bit
16 #include <linux/io-64-nonatomic-lo-hi.h>
18 #include "virt-dma.h"
46 #define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */
48 #define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
49 #define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
54 #define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1)
59 #define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
60 #define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
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/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
108 u32 mask = (1 << size) - 1; in ipu_ch_param_write_field()
113 val = readl(&base->word[word].data[i]); in ipu_ch_param_write_field()
116 writel(val, &base->word[word].data[i]); in ipu_ch_param_write_field()
118 if ((bit + size - 1) / 32 > i) { in ipu_ch_param_write_field()
119 val = readl(&base->word[word].data[i + 1]); in ipu_ch_param_write_field()
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/openbmc/linux/Documentation/scheduler/
H A Dsched-bwc.rst7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
25 Burst feature
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
40 The burst feature observes that a workload doesn't always executes the full
62 The interferenece when using burst is valued by the possibilities for
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
69 ----------
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/openbmc/linux/arch/mips/lantiq/xway/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
44 #define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
47 #define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
48 #define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
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/openbmc/qemu/hw/ssi/
H A Dimx_spi.c4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
77 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; in imx_spi_txfifo_reset()
78 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; in imx_spi_txfifo_reset()
83 fifo32_reset(&s->rx_fifo); in imx_spi_rxfifo_reset()
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; in imx_spi_rxfifo_reset()
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; in imx_spi_rxfifo_reset()
86 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; in imx_spi_rxfifo_reset()
93 if (fifo32_is_empty(&s->rx_fifo)) { in imx_spi_update_irq()
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
23 uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
66 #define MACCR_LOOPBACK (1 << 3) /* loop-back */
83 /* Tx Cycle Length */
90 /* Rx Cycle Length */
105 /* Tx Cycle Length */
110 /* Rx Cycle Length */
121 #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
127 #define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
41 * length according to the BLEN programmed (by default all BLEN are in dwmac1000_dma_axi()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
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