Searched +full:bsc9132 +full:- +full:memory +full:- +full:controller (Results 1 – 6 of 6) sorted by relevance
2 * BSC9132 Silicon/SoC Device Tree Source (post include)36 #address-cells = <2>;37 #size-cells = <1>;38 compatible = "fsl,ifc", "simple-bus";43 /* controller at 0xa000 */45 compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";47 #size-cells = <2>;48 #address-cells = <3>;49 bus-range = <0 255>;54 #interrupt-cells = <1>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Freescale DDR memory controller10 - Borislav Petkov <bp@alien8.de>11 - York Sun <york.sun@nxp.com>15 pattern: "^memory-controller@[0-9a-f]+$"19 - items:20 - enum:[all …]
2 --------3 The BSC9132 is a highly integrated device that targets the evolving4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.6 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC38507 core technologies with MAPLE-B2P baseband acceleration processing elements14 The BSC9132 SoC includes the following function and features:15 - Power Architecture subsystem including two e500 processors with16 512-Kbyte shared L2 cache17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L219 - 32 Kbyte of shared M3 memory[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */7 * BSC9132 QDS board configuration file33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"60 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */68 * Memory space is mapped 1-1, but I/O space must start from 0.70 /* controller 1, Slot 1, tgtid 1, Base address a000 */[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Copyright 2007-2012 Freescale Semiconductor, Inc.6 * Copyright 2008-2009 MontaVista Software, Inc.11 * Roy Zang <tie-fei.zang@freescale.com>12 * MPC83xx PCI-Express support:34 #include <asm/pci-bridge.h>35 #include <asm/ppc-pci.h>39 #include <asm/ppc-opcode.h>60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_fsl_pcie_early()72 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { in fsl_pcie_check_link()[all …]
... d) ERROR with allocation of kernel bd clocks_in_mhz reserved-memory ERROR: reserving fdt memory region failed (addr ...