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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Drockchip,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml#
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
21 - items:
[all …]
H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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H A Dnvidia-tegra20-nand.txt4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
14 - reset-names: Must include the following entries:
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H A Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
26 - description: Core Clock
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H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
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H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
25 -- Additional SoC-specific NAND controller properties --
33 interesting ways, sometimes with registers that lump multiple NAND-related
42 - items:
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig9 This option, if enabled, provides more flexible and linux-like
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
88 of OOB area before last ECC sector data starts. This is potentially
[all …]
H A Dfsmc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
24 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
62 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
97 * ECC placement definitions in oobfree type format
98 * There are 13 bytes of ecc for every 512 byte block and it has to be read
101 * Managing the ecc bytes in the following way makes it easier for software to
102 * read ecc bytes consecutive to data bytes. This way is similar to
103 * oobfree structure maintained already in u-boot nand driver
171 IO_ADDR_W = (ulong)this->IO_ADDR_W; in fsmc_nand_hwcontrol()
180 writel(readl(&fsmc_regs_p->pc) | in fsmc_nand_hwcontrol()
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/openbmc/linux/drivers/mtd/nand/raw/
H A Drockchip-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
5 * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
10 #include <linux/dma-mapping.h>
23 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
24 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
30 * nand_chip->oob_poi data layout:
31 * 4Bytes sys data + .... + 4Bytes sys data + ECC data.
62 #define DMA_INC_NUM (9) /* 1 - 16 */
93 * struct rk_ecc_cnt_status: represent a ecc status data.
95 * @low: ECC count low bit index at register.
[all …]
/openbmc/linux/drivers/mtd/nand/raw/atmel/
H A Dpmecc.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
33 * ECC algorithm is left to the software. The hardware/software repartition
37 * sub-section.
41 * to expose the needed lib/bch.c helpers/functions and re-use them here.
75 #define PMECC_CFG_NSECTORS(x) ((fls(x) - 1) << 8)
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H A Dpmecc.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
39 #define ATMEL_PMECC_OOBOFFSET_AUTO -1
45 int strength; member
50 } ecc; member
63 void *data, void *ecc);
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a-mk808.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
20 stdout-path = "serial2:115200n8";
28 adc-keys {
29 compatible = "adc-keys";
30 io-channels = <&saradc 1>;
31 io-channel-names = "buttons";
32 keyup-threshold-microvolt = <2500000>;
33 poll-interval = <100>;
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/openbmc/u-boot/arch/mips/dts/
H A Dci20.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
18 stdout-path = "serial4:115200n8";
29 clock-frequency = <48000000>;
51 nandc: nand-controller@1 {
52 compatible = "ingenic,jz4780-nand";
55 #address-cells = <1>;
56 #size-cells = <0>;
58 ingenic,bch-controller = <&bch>;
60 ingenic,nemc-tAS = <10>;
[all …]
/openbmc/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
26 * struct bch_geometry - BCH geometry description.
28 * @ecc_strength: A number that describes the strength of the ECC
33 * @ecc0_chunk_size: The size, in bytes, of a first ECC chunk.
34 * @eccn_chunk_size: The size, in bytes, of a single ECC chunk after
36 * @ecc_chunk_count: The number of ECC chunks in the page,
40 * the ECC status appears.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
37 arm,parity-enable;
38 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
[all …]
H A Darmada-398-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include "armada-398.dtsi"
15 compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
18 stdout-path = "serial0:115200n8";
30 internal-regs {
32 pinctrl-0 = <&i2c0_pins>;
33 pinctrl-names = "default";
35 clock-frequency = <100000>;
[all …]
H A Darmada-390-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6920)
11 /dts-v1/;
12 #include "armada-390.dtsi"
16 compatible = "marvell,a390-db", "marvell,armada390";
19 stdout-path = "serial0:115200n8";
31 internal-regs {
34 clock-frequency = <100000>;
81 pinctrl-0 = <&spi1_pins>;
82 pinctrl-names = "default";
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5cm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
16 clock-frequency = <32768>;
20 clock-frequency = <12000000>;
28 compatible = "atmel,tcb-timer";
33 compatible = "atmel,tcb-timer";
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
54 pinctrl-names = "default";
57 nand_controller: nand-controller {
[all …]
H A Dat91-cosino.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-cosino.dtsi - Device Tree file for Cosino core module
5 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
29 clock-frequency = <32768>;
33 clock-frequency = <12000000>;
39 atmel,adc-ts-wires = <4>;
40 atmel,adc-ts-pressure-threshold = <10000>;
49 pinctrl-0 = <&pinctrl_ebi_addr_nand
51 pinctrl-names = "default";
54 nand-controller {
[all …]
H A Dat91-som60.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-som60.dtsi - Device Tree file for the SOM60 module
16 stdout-path = &dbgu;
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
107 bus-width = <8>;
115 bus-width = <4>;
120 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
124 atmel,use-dma-rx;
125 atmel,use-dma-tx;
[all …]
H A Dat91-wb45n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb45n.dtsi - Device Tree file for WB45NBT board
12 model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
17 stdout-path = "serial0:115200n8";
26 atheros,board-id = "SD32";
31 compatible = "atmel,sama5d3-rstc";
35 atmel,wakeup-mode = "low";
39 clock-frequency = <32768>;
43 clock-frequency = <12000000>;
48 nand_controller: nand-controller {
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064-rb3011.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-ipq8064.dtsi"
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/leds/common.h>
7 model = "MikroTik RB3011UiAS-RM";
14 mdio-gpio0 = &mdio0;
15 mdio-gpio1 = &mdio1;
20 stdout-path = "serial0:115200n8";
28 mdio0: mdio-0 {
30 compatible = "virtual,mdio-gpio";
[all …]
H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x0>;
23 stdout-path = "serial0:921600n8";
26 reserved-memory {
27 #address-cells = <1>;
[all …]
H A Dqcom-sdx55-t55.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-t55", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x4>;
23 stdout-path = "serial0:115200n8";
26 reserved-memory {
27 #address-cells = <1>;
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