/openbmc/linux/drivers/pinctrl/tegra/ |
H A D | pinctrl-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 10 * Copyright (C) 2009-2011 ST-Ericsson AB 27 #include "../pinctrl-utils.h" 28 #include "pinctrl-tegra.h" 30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) in pmx_readl() argument 32 return readl(pmx->regs[bank] + reg); in pmx_readl() 35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) in pmx_writel() argument 37 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel() 39 pmx_readl(pmx, bank, reg); in pmx_writel() [all …]
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/openbmc/u-boot/doc/device-tree-bindings/mtd/ |
H A D | mtd-physmap.txt | 1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 6 - compatible : should contain the specific model of mtd chip(s) 7 used, if known, followed by either "cfi-flash", "jedec-flash", 8 "mtd-ram" or "mtd-rom". 9 - reg : Address range(s) of the mtd chip(s) 11 non-identical chips can be described in one node. 12 - bank-width : Width (in bytes) of the bank. Equal to the 13 device width times the number of interleaved chips. 14 - device-width : (optional) Width of a single mtd chip. If 15 omitted, assumed to be equal to 'bank-width'. [all …]
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | media5200.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 12 &gpt0 { fsl,has-wdt; }; 24 stdout-path = &console; 29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 30 bus-frequency = <132000000>; // 132 MHz 31 clock-frequency = <396000000>; // 396 MHz 40 bus-frequency = <132000000>;// 132 MHz 64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 68 phy-handle = <&phy0>; 72 phy0: ethernet-phy@0 { [all …]
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H A D | pdm360ng.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2009 - 2010 DENX Software Engineering. 17 #address-cells = <1>; 18 #size-cells = <1>; 19 interrupt-parent = <&ipic>; 27 bank-width = <0x1>; 41 compatible = "amd,s29gl01gp", "cfi-flash"; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 bank-width = <4>; [all …]
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H A D | pcm032.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source 5 * Copyright (C) 2006-2009 Pengutronix 11 &gpt0 { fsl,has-wdt; }; 12 &gpt2 { gpio-controller; }; 13 &gpt3 { gpio-controller; }; 14 &gpt4 { gpio-controller; }; 15 &gpt5 { gpio-controller; }; 16 &gpt6 { gpio-controller; }; 17 &gpt7 { gpio-controller; }; [all …]
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/openbmc/linux/drivers/gpio/ |
H A D | gpio-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2015-2017 Broadcom 26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument 27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument 28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument 29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument 30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument 31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument 32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument 33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument [all …]
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H A D | gpio-omap.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2003-2005 Nokia Corporation 9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 27 #include <linux/platform_data/gpio-omap.h> 75 u32 width; member 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument 109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument 112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction() 118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument [all …]
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/openbmc/u-boot/doc/device-tree-bindings/gpio/ |
H A D | altera_pio.txt | 4 - compatible: 5 - "altr,pio-1.0" 6 - reg: Physical base address and length of the controller's registers. 9 - altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the 10 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not 12 - gpio-bank-name: bank name attached to this device. 17 compatible = "altr,pio-1.0"; 20 altr,gpio-bank-width = <8>; 21 #gpio-cells = <2>; 22 gpio-controller; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mtd/ |
H A D | mtd-physmap.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 10 - Rob Herring <robh@kernel.org> 17 - $ref: mtd.yaml# 18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 23 - items: 24 - enum: [all …]
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H A D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" 6 - reg : Address range of the mtd chip 7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" 10 - bank-width : Width (in bytes) of the device. If not present, the width 12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped 13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes 20 kept in Hi-Z (tristate) after the start of a write access. 32 - bank: default NAND bank to use (0-3 are valid, 0 is the default). 33 - nand-ecc-mode : see nand-controller.yaml 34 - nand-ecc-strength : see nand-controller.yaml [all …]
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/openbmc/u-boot/arch/arm/mach-mvebu/ |
H A D | dram.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 49 * mvebu_sdram_bar - reads SDRAM Base Address Register 51 u32 mvebu_sdram_bar(enum memory_bank bank) in mvebu_sdram_bar() argument 56 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); in mvebu_sdram_bar() 58 if ((!enable) || (bank > BANK3)) in mvebu_sdram_bar() 61 result = readl(&base->sdram_bank[bank].win_bar); in mvebu_sdram_bar() 66 * mvebu_sdram_bs_set - writes SDRAM Bank size 68 static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size) in mvebu_sdram_bs_set() argument 73 u32 reg = readl(&base->sdram_bank[bank].win_sz); in mvebu_sdram_bs_set() [all …]
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/openbmc/linux/drivers/memory/samsung/ |
H A D | exynos-srom.c | 1 // SPDX-License-Identifier: GPL-2.0 6 // Exynos - SROM Controller support 17 #include "exynos-srom.h" 70 u32 bank, width, pmc = 0; in exynos_srom_configure_bank() local 74 if (of_property_read_u32(np, "reg", &bank)) in exynos_srom_configure_bank() 75 return -EINVAL; in exynos_srom_configure_bank() 76 if (of_property_read_u32(np, "reg-io-width", &width)) in exynos_srom_configure_bank() 77 width = 1; in exynos_srom_configure_bank() 78 if (of_property_read_bool(np, "samsung,srom-page-mode")) in exynos_srom_configure_bank() 80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | exynos-srom.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 19 - const: samsung,exynos4210-srom 24 "#address-cells": 27 "#size-cells": 34 Reflects the memory layout with four integer values per bank. Format: 35 <bank-number> 0 <parent address of bank> <size> [all …]
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H A D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Peripheral-specific properties for a Memory Controller bus. 13 to be defined in the peripheral node because they are per-peripheral 20 - Marek Vasut <marex@denx.de> 24 description: Bank number, base address and size of the device. 26 bank-width: 28 description: Bank width of the device, in bytes. [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap-zoom-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 #include "omap-gpmc-smsc911x.dtsi" 20 bank-width = <2>; 21 reg-shift = <1>; 22 reg-io-width = <1>; 23 interrupt-parent = <&gpio4>; 25 clock-frequency = <1843200>; 26 current-speed = <115200>; 27 gpmc,mux-add-data = <0>; 28 gpmc,device-width = <1>; [all …]
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/openbmc/linux/drivers/pinctrl/renesas/ |
H A D | sh_pfc.h | 1 /* SPDX-License-Identifier: GPL-2.0 12 #include <linux/pinctrl/pinconf-generic.h> 106 u16 nr_enum_ids; /* for variable width regs only */ 118 * Describe a config register consisting of several fields of the same width 119 * - name: Register name (unused, for documentation purposes only) 120 * - r: Physical register address 121 * - r_width: Width of the register (in bits) 122 * - f_width: Width of the fixed-width register fields (in bits) 123 * - ids: For each register field (from left to right, i.e. MSB to LSB), 137 * - name: Register name (unused, for documentation purposes only) [all …]
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/openbmc/u-boot/arch/nios2/dts/ |
H A D | 3c120_devboard.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 8 /dts-v1/; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "altr,nios2-1.0"; 24 interrupt-controller; 25 #interrupt-cells = <1>; 26 clock-frequency = <125000000>; [all …]
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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
H A D | sromc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 13 #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 14 /* 1-> Byte base address*/ 18 #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ 19 #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ 33 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 49 u8 bank; /* srom bank number */ member 50 u8 width; /* bus width in bytes */ member
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/openbmc/u-boot/drivers/pinctrl/renesas/ |
H A D | sh_pfc.h | 104 * Describe a config register consisting of several fields of the same width 105 * - name: Register name (unused, for documentation purposes only) 106 * - r: Physical register address 107 * - r_width: Width of the register (in bits) 108 * - f_width: Width of the fixed-width register fields (in bits) 119 * - name: Register name (unused, for documentation purposes only) 120 * - r: Physical register address 121 * - r_width: Width of the register (in bits) 122 * - var_fw0, var_fwn...: List of widths of the register fields (in bits), 150 u32 puen; /* Pull-enable or pull-up control register */ [all …]
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/openbmc/linux/drivers/clk/qcom/ |
H A D | clk-rcg.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/clk-provider.h> 15 #include "clk-rcg.h" 20 ns >>= s->src_sel_shift; in ns_to_src() 30 mask <<= s->src_sel_shift; in src_to_ns() 33 ns |= src << s->src_sel_shift; in src_to_ns() 44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent() 47 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent() 49 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent() 58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument [all …]
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/openbmc/linux/drivers/edac/ |
H A D | synopsys_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2012 - 2014 Xilinx, Inc. 143 /* DDR Control Register width definitions */ 268 * struct ecc_error_info - ECC error log information. 271 * @bank: Bank number. 274 * @bankgrpnr: Bank group number. 280 u32 bank; member 288 * struct synps_ecc_status - ECC status information to report. 302 * struct synps_edac_priv - DDR memory controller private instance data. 313 * @bank_shift: Bit shifts for bank bit. [all …]
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/openbmc/u-boot/board/samsung/common/ |
H A D | board.c | 1 // SPDX-License-Identifier: GPL-2.0+ 27 #include <dwc3-uboot.h> 80 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init() 82 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { in board_init() 84 return -1; in board_init() 92 gd->ram_size -= size; in board_init() 93 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; in board_init() 105 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); in dram_init() 119 gd->bd->bi_dram[i].start = addr; in dram_init_banksize() 120 gd->bd->bi_dram[i].size = size; in dram_init_banksize() [all …]
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/openbmc/linux/arch/powerpc/sysdev/ |
H A D | fsl_lbc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright © 2007-2008 MontaVista Software, Inc. 10 * Author: Roy Zang <tie-fei.zang@freescale.com> 36 * fsl_lbc_addr - convert the base address 37 * @addr_base: base address of the memory bank 46 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node; in fsl_lbc_addr() 57 * fsl_lbc_find - find Localbus bank 58 * @addr_base: base address of the memory bank 62 * function returns bank number (starting with 0), otherwise it returns 70 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_lbc_find() [all …]
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/openbmc/linux/drivers/memory/ |
H A D | jz4780-nemc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Author: Alex Smith <alex@alex-smith.me.uk> 20 #include <linux/jz4780-nemc.h> 22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4)) 42 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1) 43 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) 44 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) 61 * jz4780_nemc_num_banks() - count the number of banks referenced by a device 65 * child device. Unique here means that a device that references the same bank 71 unsigned int bank, count = 0; in jz4780_nemc_num_banks() local [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr() 139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr() 144 return bit + port * priv->bitcount; in sgpio_addr_to_pin() 149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr() 150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr() 159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl() 171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel() 181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits() 187 int width = priv->bitcount - 1; in sgpio_configure_bitstream() local [all …]
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