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/openbmc/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c37 #include "hw/char/serial-mm.h"
38 #include "hw/qdev-properties.h"
39 #include "exec/address-spaces.h"
49 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
72 ram_addr_t ram_size = machine->ram_size; in petalogix_ml605_init()
90 object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); in petalogix_ml605_init()
91 object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, in petalogix_ml605_init()
93 object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort); in petalogix_ml605_init()
106 /* 5th parameter 2 means bank-width in petalogix_ml605_init()
107 * 10th parameter 0 means little-endian */ in petalogix_ml605_init()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
42 - description: Ethernet core interrupt
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/openbmc/qemu/hw/dma/
H A Dxilinx_axidma.c2 * QEMU model of Xilinx AXI-DMA block.
32 #include "hw/qdev-properties.h"
43 #define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
44 #define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
45 #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
97 SDESC_CTRL_LEN_MASK = (1 << 23) - 1
152 return d->control & SDESC_CTRL_SOF; in stream_desc_sof()
157 return d->control & SDESC_CTRL_EOF; in stream_desc_eof()
162 return !!(s->regs[R_DMACR] & DMACR_RESET); in stream_resetting()
167 return s->regs[R_DMACR] & DMACR_RUNSTOP; in stream_running()
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/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
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/openbmc/qemu/hw/net/
H A Dxilinx_axienet.c2 * QEMU model of Xilinx AXI-Ethernet.
35 #include "hw/qdev-properties.h"
41 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
42 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
43 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
55 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
56 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
57 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
81 if (!phy->link) { in tdk_read()
99 r |= phy->regs[4] & (15 << 5); in tdk_read()
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/openbmc/u-boot/drivers/net/
H A Dxilinx_axi_emac.c1 // SPDX-License-Identifier: GPL-2.0+
118 /* Static BDs - driver uses only one BD */
150 * 0x0008: Auto-negotiation support
159 while (timeout && (!(readl(&regs->mdio_mcr) in mdio_wait()
161 timeout--; in mdio_wait()
172 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
190 struct axi_regs *regs = priv->iobase; in phyread()
203 writel(mdioctrlreg, &regs->mdio_mcr); in phyread()
209 *val = readl(&regs->mdio_mrd); in phyread()
216 struct axi_regs *regs = priv->iobase; in phywrite()
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/openbmc/qemu/pc-bios/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
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/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
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/openbmc/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
30 * Xilinx IP that provides high-bandwidth direct memory access between
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