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/openbmc/linux/Documentation/arch/arm64/
H A Damu.rst9 Date: 2019-09-10
16 ---------------------
24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
32 - Instructions retired: increments with every architecturally executed
34 - Memory stall cycles: counts instruction dispatch stall cycles caused by
44 64-bit event counters.
50 -------------
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
21 number is defined at design time, the maximum of each defined in the DEVID
25 programmable channels, usually 4, but again implementation defined and
31 are implementation defined, except when the CTI is connected to an ARM v8
36 architecturally connected CTI an additional compatible string is used to
37 indicate this feature (arm,coresight-cti-v8-arch).
51 and usages. These can be defined along with the signal indexes with the
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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/openbmc/linux/arch/arm/include/asm/
H A Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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/openbmc/linux/arch/parisc/kernel/
H A Dvmlinux.lds.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
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/openbmc/linux/Documentation/arch/x86/
H A Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to common_interrupt()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A Dpipeline.json96 …architecturally defined event. This event counts the number of retired branch instructions that we…
104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
113 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
122 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
131 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
140 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
169 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
184 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
192 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
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/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/openbmc/qemu/target/arm/tcg/
H A Dpsci.c2 * Copyright (C) 2014 - Linaro
21 #include "exec/helper-proto.h"
22 #include "kvm-consts.h"
23 #include "qemu/main-loop.h"
26 #include "arm-powerctl.h"
34 * whether we should treat it as a PSCI call or with the architecturally in arm_is_psci_call()
35 * defined behaviour for an SMC or HVC (which might be UNDEF or trap in arm_is_psci_call()
41 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) { in arm_is_psci_call()
46 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { in arm_is_psci_call()
67 CPUARMState *env = &cpu->env; in arm_handle_psci_call()
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/openbmc/linux/arch/x86/lib/
H A Dretpoline.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <asm/asm-offsets.h>
10 #include <asm/nospec-branch.h>
64 #include <asm/GEN-for-each-reg.h>
71 #include <asm/GEN-for-each-reg.h>
93 #include <asm/GEN-for-each-reg.h>
100 #include <asm/GEN-for-each-reg.h>
119 #include <asm/GEN-for-each-reg.h>
126 #include <asm/GEN-for-each-reg.h>
140 * - srso_alias_untrain_ret() is 2M aligned
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/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h13 #include "target/arm/cpu-qom.h"
27 /* Exception priorities can range from -3 to 255; only the unmodifiable
54 * Entries in sec_vectors[] for non-banked exception numbers are unused.
66 * - vectpending
67 * - vectpending_is_secure
68 * - exception_prio
69 * - vectpending_prio
91 * @secure: false for non-banked exceptions or for the nonsecure
97 * of architecturally banked exceptions.
104 * @secure: false for non-banked exceptions or for the nonsecure
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/openbmc/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
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/openbmc/linux/arch/x86/mm/
H A Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
39 return -EINVAL; in setup_userpte()
48 return -EINVAL; in setup_userpte()
66 * NOTE! For PAE, any changes to the top page-directory-pointer-table in ___pmd_free_tlb()
70 tlb->need_flush_all = 1; in ___pmd_free_tlb()
97 list_add(&ptdesc->pt_list, &pgd_list); in pgd_list_add()
104 list_del(&ptdesc->pt_list); in pgd_list_del()
115 virt_to_ptdesc(pgd)->pt_mm = mm; in pgd_set_mm()
120 return page_ptdesc(page)->pt_mm; in pgd_page_get_mm()
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/openbmc/linux/arch/arm64/kvm/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
79 return -EINVAL; in kvm_vcpu_enable_sve()
81 vcpu->arch.sve_max_vl = kvm_sve_max_vl; in kvm_vcpu_enable_sve()
95 * vcpu->arch.sve_state as necessary.
104 vl = vcpu->arch.sve_max_vl; in kvm_vcpu_finalize_sve()
109 * set_sve_vls(). Double-check here just to be sure: in kvm_vcpu_finalize_sve()
113 return -EIO; in kvm_vcpu_finalize_sve()
118 return -ENOMEM; in kvm_vcpu_finalize_sve()
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/openbmc/linux/drivers/clocksource/
H A Darc_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
75 * defined in arch/arc/kernel/mcip.c in arc_read_gfrc()
110 pr_warn("Global-64-bit-Ctr clocksource not detected\n"); in arc_cs_setup_gfrc()
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/openbmc/qemu/linux-headers/asm-arm64/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
61 * Supported CPU Targets - Adding a new target type is not recommended,
129 * Although the control registers are architecturally defined as 32
152 * Architecture specific defines for kvm_guest_debug->control
163 /* Bits for run->s.regs.device_irq_level */
268 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
277 /* KVM-as-firmware specific pseudo-registers */
289 * - NOT_REQUIRED: the guest doesn't need to do anything
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/openbmc/linux/tools/arch/arm64/include/uapi/asm/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
63 * Supported CPU Targets - Adding a new target type is not recommended,
131 * Although the control registers are architecturally defined as 32
154 * Architecture specific defines for kvm_guest_debug->control
265 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
274 /* KVM-as-firmware specific pseudo-registers */
286 * - NOT_REQUIRED: the guest doesn't need to do anything
287 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
[all …]
/openbmc/linux/arch/arm64/include/uapi/asm/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
63 * Supported CPU Targets - Adding a new target type is not recommended,
131 * Although the control registers are architecturally defined as 32
154 * Architecture specific defines for kvm_guest_debug->control
265 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
274 /* KVM-as-firmware specific pseudo-registers */
286 * - NOT_REQUIRED: the guest doesn't need to do anything
287 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
[all …]
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/irqchip/arm-gic-v3.h>
62 u64 mask = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); in get_restricted_features_unsigned()
99 const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm); in get_pvm_id_aa64pfr1()
141 * No support for implementation defined features, therefore, hyp has no in get_pvm_id_aa64afr0()
151 * No support for implementation defined features, therefore, hyp has no in get_pvm_id_aa64afr1()
253 if (!p->is_write) in pvm_access_raz_wi()
254 p->regval = 0; in pvm_access_raz_wi()
269 if (p->is_write) { in pvm_access_id_aarch32()
295 if (p->is_write) { in pvm_access_id_aarch64()
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dmce.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* AMD-specific bits */
56 * - Deferred error interrupt type is specifiable by bank.
57 * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
59 * - TCC bit is present in MCx_STATUS.
67 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
70 * of uncorrected errors - so the F bit is deliberately skipped
75 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
76 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
92 #define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
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/openbmc/linux/arch/arm64/include/asm/
H A Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
58 /* AArch32-specific ptrace requests */
91 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
113 * a syscall -- i.e., its most recent entry into the kernel from
116 * This must have the value -1, for ABI compatibility with ptrace etc.
118 #define NO_SYSCALL (-1)
127 /* Architecturally defined mapping between AArch32 and AArch64 registers */
208 return regs->syscallno != NO_SYSCALL; in in_syscall()
213 regs->syscallno = NO_SYSCALL; in forget_syscall()
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* str_pc_offset is architecturally defined from ARMv7 onwards */
32 /* We need a run-time check to determine str_pc_offset */
41 long cpsr = regs->ARM_cpsr; in bx_write_pc()
49 regs->ARM_cpsr = cpsr; in bx_write_pc()
50 regs->ARM_pc = pcv; in bx_write_pc()
62 /* We need run-time testing to determine if load_write_pc() should interwork. */
73 regs->ARM_pc = pcv; in load_write_pc()
90 /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
101 regs->ARM_pc = pcv; in alu_write_pc()
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