Home
last modified time | relevance | path

Searched full:architected (Results 1 – 25 of 110) sorted by relevance

12345

/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml7 title: ARM architected timer
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
17 The per-core architected timer is attached to a GIC to deliver its
95 supported for 32-bit systems which follow the ARMv7 architected reset
H A Darm,arch_timer_mmio.yaml7 title: ARM memory mapped architected timer
14 ARM cores may have a memory mapped architected timer, which provides up to 8
52 supported for 32-bit systems which follow the ARMv7 architected reset
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_64.h200 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
203 .cpu_name = "POWER6 (architected)",
211 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
214 .cpu_name = "POWER7 (architected)",
226 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
229 .cpu_name = "POWER8 (architected)",
241 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
244 .cpu_name = "POWER9 (architected)",
255 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
258 .cpu_name = "POWER10 (architected)",
/openbmc/linux/arch/arm/mach-bcm/
H A DKconfig10 comment "IPROC architected SoCs"
24 This enables support for systems based on Broadcom IPROC architected SoCs.
87 comment "KONA architected SoCs"
/openbmc/linux/Documentation/arch/arm64/
H A Damu.rst39 The Activity Monitors architecture provides space for up to 16 architected
41 implement additional architected event counters.
H A Dbooting.rst185 System caches which respect the architected cache maintenance by VA
187 System caches which do not respect architected cache maintenance by VA
190 - Architected timers
206 All writable architected system registers at or below the exception
414 The requirements described above for CPU mode, caches, MMUs, architected
H A Delf_hwcaps.rst15 architected discovery mechanism available to userspace code at EL0. The
46 which are described by architected ID registers inaccessible to
/openbmc/linux/arch/ia64/kernel/
H A Dsigframe.h18 * End of architected state.
/openbmc/linux/arch/arm/kernel/
H A Darch_timer.c26 /* Use the architected timer for the delay loop. */ in arch_timer_delay_timer_register()
/openbmc/phosphor-host-ipmid/xyz/openbmc_project/Ipmi/Internal/
H A DSoftPowerOff.interface.yaml5 sends 'ReadEvent' command and BMC responds with an architected packet
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dcache.json483 …licDescription": "This event counts load uops with locked access retired to the architected path.",
493 …"PublicDescription": "This event counts line-splitted load uops retired to the architected path. A…
503 …"PublicDescription": "This event counts line-splitted store uops retired to the architected path. …
513 …tion": "This event counts load uops with true STLB miss retired to the architected path. True STLB…
523 …ion": "This event counts store uops with true STLB miss retired to the architected path. True STLB…
/openbmc/u-boot/include/configs/
H A Dqemu-arm.h20 /* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
H A Dtegra-common.h19 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
/openbmc/linux/arch/alpha/include/asm/
H A Dhwrpb.h9 * These values are architected.
31 * These values are architected.
/openbmc/phosphor-post-code-manager/
H A DREADME.md32 phosphor-post-code-manager is architected to look for the property changed
/openbmc/linux/drivers/parisc/
H A Dgsc.h18 /* PA I/O Architected devices support at least 5 bits in the EIM register. */
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Darm,smmu-v3-pmcg.yaml16 architected and IMPLEMENTATION DEFINED event counters.
/openbmc/linux/arch/arm/mach-rockchip/
H A Drockchip.c29 * which is needed for the architected timer to work. in rockchip_timer_init()
/openbmc/linux/arch/arm64/kernel/
H A Dtime.c66 panic("Unable to initialise architected timer.\n"); in time_init()
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dcache.json483 …licDescription": "This event counts load uops with locked access retired to the architected path.",
493 …"PublicDescription": "This event counts line-splitted load uops retired to the architected path. A…
503 …"PublicDescription": "This event counts line-splitted store uops retired to the architected path. …
513 …tion": "This event counts load uops with true STLB miss retired to the architected path. True STLB…
523 …ion": "This event counts store uops with true STLB miss retired to the architected path. True STLB…
/openbmc/qemu/target/arm/
H A Darm-powerctl.h82 * CPU reset process. The CPU will start in the way it is architected
/openbmc/linux/arch/powerpc/include/asm/
H A Dcputhreads.h70 * architected, is not something a hypervisor could emulate and a future
/openbmc/docs/designs/
H A Dpower-systems-memory-preserving-reboot.md152 Each SBE collects the architected states and stores it into a pre-defined
165 Once SBE is started, it starts hostboot, hostboot copies the architected states
/openbmc/webui-vue/
H A DREADME.md23 strong documentation. It has been architected to allow organizations to easily
/openbmc/u-boot/doc/
H A DREADME.qemu-arm19 - An ARMv7/ARMv8 architected timer

12345