1*e4624435SJonathan Corbet===================== 2*e4624435SJonathan CorbetBooting AArch64 Linux 3*e4624435SJonathan Corbet===================== 4*e4624435SJonathan Corbet 5*e4624435SJonathan CorbetAuthor: Will Deacon <will.deacon@arm.com> 6*e4624435SJonathan Corbet 7*e4624435SJonathan CorbetDate : 07 September 2012 8*e4624435SJonathan Corbet 9*e4624435SJonathan CorbetThis document is based on the ARM booting document by Russell King and 10*e4624435SJonathan Corbetis relevant to all public releases of the AArch64 Linux kernel. 11*e4624435SJonathan Corbet 12*e4624435SJonathan CorbetThe AArch64 exception model is made up of a number of exception levels 13*e4624435SJonathan Corbet(EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure 14*e4624435SJonathan Corbetcounterpart. EL2 is the hypervisor level, EL3 is the highest priority 15*e4624435SJonathan Corbetlevel and exists only in secure mode. Both are architecturally optional. 16*e4624435SJonathan Corbet 17*e4624435SJonathan CorbetFor the purposes of this document, we will use the term `boot loader` 18*e4624435SJonathan Corbetsimply to define all software that executes on the CPU(s) before control 19*e4624435SJonathan Corbetis passed to the Linux kernel. This may include secure monitor and 20*e4624435SJonathan Corbethypervisor code, or it may just be a handful of instructions for 21*e4624435SJonathan Corbetpreparing a minimal boot environment. 22*e4624435SJonathan Corbet 23*e4624435SJonathan CorbetEssentially, the boot loader should provide (as a minimum) the 24*e4624435SJonathan Corbetfollowing: 25*e4624435SJonathan Corbet 26*e4624435SJonathan Corbet1. Setup and initialise the RAM 27*e4624435SJonathan Corbet2. Setup the device tree 28*e4624435SJonathan Corbet3. Decompress the kernel image 29*e4624435SJonathan Corbet4. Call the kernel image 30*e4624435SJonathan Corbet 31*e4624435SJonathan Corbet 32*e4624435SJonathan Corbet1. Setup and initialise RAM 33*e4624435SJonathan Corbet--------------------------- 34*e4624435SJonathan Corbet 35*e4624435SJonathan CorbetRequirement: MANDATORY 36*e4624435SJonathan Corbet 37*e4624435SJonathan CorbetThe boot loader is expected to find and initialise all RAM that the 38*e4624435SJonathan Corbetkernel will use for volatile data storage in the system. It performs 39*e4624435SJonathan Corbetthis in a machine dependent manner. (It may use internal algorithms 40*e4624435SJonathan Corbetto automatically locate and size all RAM, or it may use knowledge of 41*e4624435SJonathan Corbetthe RAM in the machine, or any other method the boot loader designer 42*e4624435SJonathan Corbetsees fit.) 43*e4624435SJonathan Corbet 44*e4624435SJonathan Corbet 45*e4624435SJonathan Corbet2. Setup the device tree 46*e4624435SJonathan Corbet------------------------- 47*e4624435SJonathan Corbet 48*e4624435SJonathan CorbetRequirement: MANDATORY 49*e4624435SJonathan Corbet 50*e4624435SJonathan CorbetThe device tree blob (dtb) must be placed on an 8-byte boundary and must 51*e4624435SJonathan Corbetnot exceed 2 megabytes in size. Since the dtb will be mapped cacheable 52*e4624435SJonathan Corbetusing blocks of up to 2 megabytes in size, it must not be placed within 53*e4624435SJonathan Corbetany 2M region which must be mapped with any specific attributes. 54*e4624435SJonathan Corbet 55*e4624435SJonathan CorbetNOTE: versions prior to v4.2 also require that the DTB be placed within 56*e4624435SJonathan Corbetthe 512 MB region starting at text_offset bytes below the kernel Image. 57*e4624435SJonathan Corbet 58*e4624435SJonathan Corbet3. Decompress the kernel image 59*e4624435SJonathan Corbet------------------------------ 60*e4624435SJonathan Corbet 61*e4624435SJonathan CorbetRequirement: OPTIONAL 62*e4624435SJonathan Corbet 63*e4624435SJonathan CorbetThe AArch64 kernel does not currently provide a decompressor and 64*e4624435SJonathan Corbettherefore requires decompression (gzip etc.) to be performed by the boot 65*e4624435SJonathan Corbetloader if a compressed Image target (e.g. Image.gz) is used. For 66*e4624435SJonathan Corbetbootloaders that do not implement this requirement, the uncompressed 67*e4624435SJonathan CorbetImage target is available instead. 68*e4624435SJonathan Corbet 69*e4624435SJonathan Corbet 70*e4624435SJonathan Corbet4. Call the kernel image 71*e4624435SJonathan Corbet------------------------ 72*e4624435SJonathan Corbet 73*e4624435SJonathan CorbetRequirement: MANDATORY 74*e4624435SJonathan Corbet 75*e4624435SJonathan CorbetThe decompressed kernel image contains a 64-byte header as follows:: 76*e4624435SJonathan Corbet 77*e4624435SJonathan Corbet u32 code0; /* Executable code */ 78*e4624435SJonathan Corbet u32 code1; /* Executable code */ 79*e4624435SJonathan Corbet u64 text_offset; /* Image load offset, little endian */ 80*e4624435SJonathan Corbet u64 image_size; /* Effective Image size, little endian */ 81*e4624435SJonathan Corbet u64 flags; /* kernel flags, little endian */ 82*e4624435SJonathan Corbet u64 res2 = 0; /* reserved */ 83*e4624435SJonathan Corbet u64 res3 = 0; /* reserved */ 84*e4624435SJonathan Corbet u64 res4 = 0; /* reserved */ 85*e4624435SJonathan Corbet u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */ 86*e4624435SJonathan Corbet u32 res5; /* reserved (used for PE COFF offset) */ 87*e4624435SJonathan Corbet 88*e4624435SJonathan Corbet 89*e4624435SJonathan CorbetHeader notes: 90*e4624435SJonathan Corbet 91*e4624435SJonathan Corbet- As of v3.17, all fields are little endian unless stated otherwise. 92*e4624435SJonathan Corbet 93*e4624435SJonathan Corbet- code0/code1 are responsible for branching to stext. 94*e4624435SJonathan Corbet 95*e4624435SJonathan Corbet- when booting through EFI, code0/code1 are initially skipped. 96*e4624435SJonathan Corbet res5 is an offset to the PE header and the PE header has the EFI 97*e4624435SJonathan Corbet entry point (efi_stub_entry). When the stub has done its work, it 98*e4624435SJonathan Corbet jumps to code0 to resume the normal boot process. 99*e4624435SJonathan Corbet 100*e4624435SJonathan Corbet- Prior to v3.17, the endianness of text_offset was not specified. In 101*e4624435SJonathan Corbet these cases image_size is zero and text_offset is 0x80000 in the 102*e4624435SJonathan Corbet endianness of the kernel. Where image_size is non-zero image_size is 103*e4624435SJonathan Corbet little-endian and must be respected. Where image_size is zero, 104*e4624435SJonathan Corbet text_offset can be assumed to be 0x80000. 105*e4624435SJonathan Corbet 106*e4624435SJonathan Corbet- The flags field (introduced in v3.17) is a little-endian 64-bit field 107*e4624435SJonathan Corbet composed as follows: 108*e4624435SJonathan Corbet 109*e4624435SJonathan Corbet ============= =============================================================== 110*e4624435SJonathan Corbet Bit 0 Kernel endianness. 1 if BE, 0 if LE. 111*e4624435SJonathan Corbet Bit 1-2 Kernel Page size. 112*e4624435SJonathan Corbet 113*e4624435SJonathan Corbet * 0 - Unspecified. 114*e4624435SJonathan Corbet * 1 - 4K 115*e4624435SJonathan Corbet * 2 - 16K 116*e4624435SJonathan Corbet * 3 - 64K 117*e4624435SJonathan Corbet Bit 3 Kernel physical placement 118*e4624435SJonathan Corbet 119*e4624435SJonathan Corbet 0 120*e4624435SJonathan Corbet 2MB aligned base should be as close as possible 121*e4624435SJonathan Corbet to the base of DRAM, since memory below it is not 122*e4624435SJonathan Corbet accessible via the linear mapping 123*e4624435SJonathan Corbet 1 124*e4624435SJonathan Corbet 2MB aligned base such that all image_size bytes 125*e4624435SJonathan Corbet counted from the start of the image are within 126*e4624435SJonathan Corbet the 48-bit addressable range of physical memory 127*e4624435SJonathan Corbet Bits 4-63 Reserved. 128*e4624435SJonathan Corbet ============= =============================================================== 129*e4624435SJonathan Corbet 130*e4624435SJonathan Corbet- When image_size is zero, a bootloader should attempt to keep as much 131*e4624435SJonathan Corbet memory as possible free for use by the kernel immediately after the 132*e4624435SJonathan Corbet end of the kernel image. The amount of space required will vary 133*e4624435SJonathan Corbet depending on selected features, and is effectively unbound. 134*e4624435SJonathan Corbet 135*e4624435SJonathan CorbetThe Image must be placed text_offset bytes from a 2MB aligned base 136*e4624435SJonathan Corbetaddress anywhere in usable system RAM and called there. The region 137*e4624435SJonathan Corbetbetween the 2 MB aligned base address and the start of the image has no 138*e4624435SJonathan Corbetspecial significance to the kernel, and may be used for other purposes. 139*e4624435SJonathan CorbetAt least image_size bytes from the start of the image must be free for 140*e4624435SJonathan Corbetuse by the kernel. 141*e4624435SJonathan CorbetNOTE: versions prior to v4.6 cannot make use of memory below the 142*e4624435SJonathan Corbetphysical offset of the Image so it is recommended that the Image be 143*e4624435SJonathan Corbetplaced as close as possible to the start of system RAM. 144*e4624435SJonathan Corbet 145*e4624435SJonathan CorbetIf an initrd/initramfs is passed to the kernel at boot, it must reside 146*e4624435SJonathan Corbetentirely within a 1 GB aligned physical memory window of up to 32 GB in 147*e4624435SJonathan Corbetsize that fully covers the kernel Image as well. 148*e4624435SJonathan Corbet 149*e4624435SJonathan CorbetAny memory described to the kernel (even that below the start of the 150*e4624435SJonathan Corbetimage) which is not marked as reserved from the kernel (e.g., with a 151*e4624435SJonathan Corbetmemreserve region in the device tree) will be considered as available to 152*e4624435SJonathan Corbetthe kernel. 153*e4624435SJonathan Corbet 154*e4624435SJonathan CorbetBefore jumping into the kernel, the following conditions must be met: 155*e4624435SJonathan Corbet 156*e4624435SJonathan Corbet- Quiesce all DMA capable devices so that memory does not get 157*e4624435SJonathan Corbet corrupted by bogus network packets or disk data. This will save 158*e4624435SJonathan Corbet you many hours of debug. 159*e4624435SJonathan Corbet 160*e4624435SJonathan Corbet- Primary CPU general-purpose register settings: 161*e4624435SJonathan Corbet 162*e4624435SJonathan Corbet - x0 = physical address of device tree blob (dtb) in system RAM. 163*e4624435SJonathan Corbet - x1 = 0 (reserved for future use) 164*e4624435SJonathan Corbet - x2 = 0 (reserved for future use) 165*e4624435SJonathan Corbet - x3 = 0 (reserved for future use) 166*e4624435SJonathan Corbet 167*e4624435SJonathan Corbet- CPU mode 168*e4624435SJonathan Corbet 169*e4624435SJonathan Corbet All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, 170*e4624435SJonathan Corbet IRQ and FIQ). 171*e4624435SJonathan Corbet The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order 172*e4624435SJonathan Corbet to have access to the virtualisation extensions), or in EL1. 173*e4624435SJonathan Corbet 174*e4624435SJonathan Corbet- Caches, MMUs 175*e4624435SJonathan Corbet 176*e4624435SJonathan Corbet The MMU must be off. 177*e4624435SJonathan Corbet 178*e4624435SJonathan Corbet The instruction cache may be on or off, and must not hold any stale 179*e4624435SJonathan Corbet entries corresponding to the loaded kernel image. 180*e4624435SJonathan Corbet 181*e4624435SJonathan Corbet The address range corresponding to the loaded kernel image must be 182*e4624435SJonathan Corbet cleaned to the PoC. In the presence of a system cache or other 183*e4624435SJonathan Corbet coherent masters with caches enabled, this will typically require 184*e4624435SJonathan Corbet cache maintenance by VA rather than set/way operations. 185*e4624435SJonathan Corbet System caches which respect the architected cache maintenance by VA 186*e4624435SJonathan Corbet operations must be configured and may be enabled. 187*e4624435SJonathan Corbet System caches which do not respect architected cache maintenance by VA 188*e4624435SJonathan Corbet operations (not recommended) must be configured and disabled. 189*e4624435SJonathan Corbet 190*e4624435SJonathan Corbet- Architected timers 191*e4624435SJonathan Corbet 192*e4624435SJonathan Corbet CNTFRQ must be programmed with the timer frequency and CNTVOFF must 193*e4624435SJonathan Corbet be programmed with a consistent value on all CPUs. If entering the 194*e4624435SJonathan Corbet kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where 195*e4624435SJonathan Corbet available. 196*e4624435SJonathan Corbet 197*e4624435SJonathan Corbet- Coherency 198*e4624435SJonathan Corbet 199*e4624435SJonathan Corbet All CPUs to be booted by the kernel must be part of the same coherency 200*e4624435SJonathan Corbet domain on entry to the kernel. This may require IMPLEMENTATION DEFINED 201*e4624435SJonathan Corbet initialisation to enable the receiving of maintenance operations on 202*e4624435SJonathan Corbet each CPU. 203*e4624435SJonathan Corbet 204*e4624435SJonathan Corbet- System registers 205*e4624435SJonathan Corbet 206*e4624435SJonathan Corbet All writable architected system registers at or below the exception 207*e4624435SJonathan Corbet level where the kernel image will be entered must be initialised by 208*e4624435SJonathan Corbet software at a higher exception level to prevent execution in an UNKNOWN 209*e4624435SJonathan Corbet state. 210*e4624435SJonathan Corbet 211*e4624435SJonathan Corbet For all systems: 212*e4624435SJonathan Corbet - If EL3 is present: 213*e4624435SJonathan Corbet 214*e4624435SJonathan Corbet - SCR_EL3.FIQ must have the same value across all CPUs the kernel is 215*e4624435SJonathan Corbet executing on. 216*e4624435SJonathan Corbet - The value of SCR_EL3.FIQ must be the same as the one present at boot 217*e4624435SJonathan Corbet time whenever the kernel is executing. 218*e4624435SJonathan Corbet 219*e4624435SJonathan Corbet - If EL3 is present and the kernel is entered at EL2: 220*e4624435SJonathan Corbet 221*e4624435SJonathan Corbet - SCR_EL3.HCE (bit 8) must be initialised to 0b1. 222*e4624435SJonathan Corbet 223*e4624435SJonathan Corbet For systems with a GICv3 interrupt controller to be used in v3 mode: 224*e4624435SJonathan Corbet - If EL3 is present: 225*e4624435SJonathan Corbet 226*e4624435SJonathan Corbet - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1. 227*e4624435SJonathan Corbet - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. 228*e4624435SJonathan Corbet - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across 229*e4624435SJonathan Corbet all CPUs the kernel is executing on, and must stay constant 230*e4624435SJonathan Corbet for the lifetime of the kernel. 231*e4624435SJonathan Corbet 232*e4624435SJonathan Corbet - If the kernel is entered at EL1: 233*e4624435SJonathan Corbet 234*e4624435SJonathan Corbet - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 235*e4624435SJonathan Corbet - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. 236*e4624435SJonathan Corbet 237*e4624435SJonathan Corbet - The DT or ACPI tables must describe a GICv3 interrupt controller. 238*e4624435SJonathan Corbet 239*e4624435SJonathan Corbet For systems with a GICv3 interrupt controller to be used in 240*e4624435SJonathan Corbet compatibility (v2) mode: 241*e4624435SJonathan Corbet 242*e4624435SJonathan Corbet - If EL3 is present: 243*e4624435SJonathan Corbet 244*e4624435SJonathan Corbet ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0. 245*e4624435SJonathan Corbet 246*e4624435SJonathan Corbet - If the kernel is entered at EL1: 247*e4624435SJonathan Corbet 248*e4624435SJonathan Corbet ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. 249*e4624435SJonathan Corbet 250*e4624435SJonathan Corbet - The DT or ACPI tables must describe a GICv2 interrupt controller. 251*e4624435SJonathan Corbet 252*e4624435SJonathan Corbet For CPUs with pointer authentication functionality: 253*e4624435SJonathan Corbet 254*e4624435SJonathan Corbet - If EL3 is present: 255*e4624435SJonathan Corbet 256*e4624435SJonathan Corbet - SCR_EL3.APK (bit 16) must be initialised to 0b1 257*e4624435SJonathan Corbet - SCR_EL3.API (bit 17) must be initialised to 0b1 258*e4624435SJonathan Corbet 259*e4624435SJonathan Corbet - If the kernel is entered at EL1: 260*e4624435SJonathan Corbet 261*e4624435SJonathan Corbet - HCR_EL2.APK (bit 40) must be initialised to 0b1 262*e4624435SJonathan Corbet - HCR_EL2.API (bit 41) must be initialised to 0b1 263*e4624435SJonathan Corbet 264*e4624435SJonathan Corbet For CPUs with Activity Monitors Unit v1 (AMUv1) extension present: 265*e4624435SJonathan Corbet 266*e4624435SJonathan Corbet - If EL3 is present: 267*e4624435SJonathan Corbet 268*e4624435SJonathan Corbet - CPTR_EL3.TAM (bit 30) must be initialised to 0b0 269*e4624435SJonathan Corbet - CPTR_EL2.TAM (bit 30) must be initialised to 0b0 270*e4624435SJonathan Corbet - AMCNTENSET0_EL0 must be initialised to 0b1111 271*e4624435SJonathan Corbet - AMCNTENSET1_EL0 must be initialised to a platform specific value 272*e4624435SJonathan Corbet having 0b1 set for the corresponding bit for each of the auxiliary 273*e4624435SJonathan Corbet counters present. 274*e4624435SJonathan Corbet 275*e4624435SJonathan Corbet - If the kernel is entered at EL1: 276*e4624435SJonathan Corbet 277*e4624435SJonathan Corbet - AMCNTENSET0_EL0 must be initialised to 0b1111 278*e4624435SJonathan Corbet - AMCNTENSET1_EL0 must be initialised to a platform specific value 279*e4624435SJonathan Corbet having 0b1 set for the corresponding bit for each of the auxiliary 280*e4624435SJonathan Corbet counters present. 281*e4624435SJonathan Corbet 282*e4624435SJonathan Corbet For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: 283*e4624435SJonathan Corbet 284*e4624435SJonathan Corbet - If EL3 is present and the kernel is entered at EL2: 285*e4624435SJonathan Corbet 286*e4624435SJonathan Corbet - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. 287*e4624435SJonathan Corbet 288*e4624435SJonathan Corbet For CPUs with support for HCRX_EL2 (FEAT_HCX) present: 289*e4624435SJonathan Corbet 290*e4624435SJonathan Corbet - If EL3 is present and the kernel is entered at EL2: 291*e4624435SJonathan Corbet 292*e4624435SJonathan Corbet - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. 293*e4624435SJonathan Corbet 294*e4624435SJonathan Corbet For CPUs with Advanced SIMD and floating point support: 295*e4624435SJonathan Corbet 296*e4624435SJonathan Corbet - If EL3 is present: 297*e4624435SJonathan Corbet 298*e4624435SJonathan Corbet - CPTR_EL3.TFP (bit 10) must be initialised to 0b0. 299*e4624435SJonathan Corbet 300*e4624435SJonathan Corbet - If EL2 is present and the kernel is entered at EL1: 301*e4624435SJonathan Corbet 302*e4624435SJonathan Corbet - CPTR_EL2.TFP (bit 10) must be initialised to 0b0. 303*e4624435SJonathan Corbet 304*e4624435SJonathan Corbet For CPUs with the Scalable Vector Extension (FEAT_SVE) present: 305*e4624435SJonathan Corbet 306*e4624435SJonathan Corbet - if EL3 is present: 307*e4624435SJonathan Corbet 308*e4624435SJonathan Corbet - CPTR_EL3.EZ (bit 8) must be initialised to 0b1. 309*e4624435SJonathan Corbet 310*e4624435SJonathan Corbet - ZCR_EL3.LEN must be initialised to the same value for all CPUs the 311*e4624435SJonathan Corbet kernel is executed on. 312*e4624435SJonathan Corbet 313*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 314*e4624435SJonathan Corbet 315*e4624435SJonathan Corbet - CPTR_EL2.TZ (bit 8) must be initialised to 0b0. 316*e4624435SJonathan Corbet 317*e4624435SJonathan Corbet - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11. 318*e4624435SJonathan Corbet 319*e4624435SJonathan Corbet - ZCR_EL2.LEN must be initialised to the same value for all CPUs the 320*e4624435SJonathan Corbet kernel will execute on. 321*e4624435SJonathan Corbet 322*e4624435SJonathan Corbet For CPUs with the Scalable Matrix Extension (FEAT_SME): 323*e4624435SJonathan Corbet 324*e4624435SJonathan Corbet - If EL3 is present: 325*e4624435SJonathan Corbet 326*e4624435SJonathan Corbet - CPTR_EL3.ESM (bit 12) must be initialised to 0b1. 327*e4624435SJonathan Corbet 328*e4624435SJonathan Corbet - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1. 329*e4624435SJonathan Corbet 330*e4624435SJonathan Corbet - SMCR_EL3.LEN must be initialised to the same value for all CPUs the 331*e4624435SJonathan Corbet kernel will execute on. 332*e4624435SJonathan Corbet 333*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 334*e4624435SJonathan Corbet 335*e4624435SJonathan Corbet - CPTR_EL2.TSM (bit 12) must be initialised to 0b0. 336*e4624435SJonathan Corbet 337*e4624435SJonathan Corbet - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11. 338*e4624435SJonathan Corbet 339*e4624435SJonathan Corbet - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1. 340*e4624435SJonathan Corbet 341*e4624435SJonathan Corbet - SMCR_EL2.LEN must be initialised to the same value for all CPUs the 342*e4624435SJonathan Corbet kernel will execute on. 343*e4624435SJonathan Corbet 344*e4624435SJonathan Corbet - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. 345*e4624435SJonathan Corbet 346*e4624435SJonathan Corbet - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. 347*e4624435SJonathan Corbet 348*e4624435SJonathan Corbet - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. 349*e4624435SJonathan Corbet 350*e4624435SJonathan Corbet - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. 351*e4624435SJonathan Corbet 352*e4624435SJonathan Corbet For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64): 353*e4624435SJonathan Corbet 354*e4624435SJonathan Corbet - If EL3 is present: 355*e4624435SJonathan Corbet 356*e4624435SJonathan Corbet - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1. 357*e4624435SJonathan Corbet 358*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 359*e4624435SJonathan Corbet 360*e4624435SJonathan Corbet - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1. 361*e4624435SJonathan Corbet 362*e4624435SJonathan Corbet For CPUs with the Memory Tagging Extension feature (FEAT_MTE2): 363*e4624435SJonathan Corbet 364*e4624435SJonathan Corbet - If EL3 is present: 365*e4624435SJonathan Corbet 366*e4624435SJonathan Corbet - SCR_EL3.ATA (bit 26) must be initialised to 0b1. 367*e4624435SJonathan Corbet 368*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 369*e4624435SJonathan Corbet 370*e4624435SJonathan Corbet - HCR_EL2.ATA (bit 56) must be initialised to 0b1. 371*e4624435SJonathan Corbet 372*e4624435SJonathan Corbet For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2): 373*e4624435SJonathan Corbet 374*e4624435SJonathan Corbet - If EL3 is present: 375*e4624435SJonathan Corbet 376*e4624435SJonathan Corbet - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. 377*e4624435SJonathan Corbet 378*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 379*e4624435SJonathan Corbet 380*e4624435SJonathan Corbet - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. 381*e4624435SJonathan Corbet 382*e4624435SJonathan Corbet For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): 383*e4624435SJonathan Corbet 384*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 385*e4624435SJonathan Corbet 386*e4624435SJonathan Corbet - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. 387*e4624435SJonathan Corbet 388*e4624435SJonathan Corbet For CPUs with the Extended Translation Control Register feature (FEAT_TCR2): 389*e4624435SJonathan Corbet 390*e4624435SJonathan Corbet - If EL3 is present: 391*e4624435SJonathan Corbet 392*e4624435SJonathan Corbet - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1. 393*e4624435SJonathan Corbet 394*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 395*e4624435SJonathan Corbet 396*e4624435SJonathan Corbet - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1. 397*e4624435SJonathan Corbet 398*e4624435SJonathan Corbet For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE): 399*e4624435SJonathan Corbet 400*e4624435SJonathan Corbet - If EL3 is present: 401*e4624435SJonathan Corbet 402*e4624435SJonathan Corbet - SCR_EL3.PIEn (bit 45) must be initialised to 0b1. 403*e4624435SJonathan Corbet 404*e4624435SJonathan Corbet - If the kernel is entered at EL1 and EL2 is present: 405*e4624435SJonathan Corbet 406*e4624435SJonathan Corbet - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. 407*e4624435SJonathan Corbet 408*e4624435SJonathan Corbet - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. 409*e4624435SJonathan Corbet 410*e4624435SJonathan Corbet - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. 411*e4624435SJonathan Corbet 412*e4624435SJonathan Corbet - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. 413*e4624435SJonathan Corbet 414*e4624435SJonathan CorbetThe requirements described above for CPU mode, caches, MMUs, architected 415*e4624435SJonathan Corbettimers, coherency and system registers apply to all CPUs. All CPUs must 416*e4624435SJonathan Corbetenter the kernel in the same exception level. Where the values documented 417*e4624435SJonathan Corbetdisable traps it is permissible for these traps to be enabled so long as 418*e4624435SJonathan Corbetthose traps are handled transparently by higher exception levels as though 419*e4624435SJonathan Corbetthe values documented were set. 420*e4624435SJonathan Corbet 421*e4624435SJonathan CorbetThe boot loader is expected to enter the kernel on each CPU in the 422*e4624435SJonathan Corbetfollowing manner: 423*e4624435SJonathan Corbet 424*e4624435SJonathan Corbet- The primary CPU must jump directly to the first instruction of the 425*e4624435SJonathan Corbet kernel image. The device tree blob passed by this CPU must contain 426*e4624435SJonathan Corbet an 'enable-method' property for each cpu node. The supported 427*e4624435SJonathan Corbet enable-methods are described below. 428*e4624435SJonathan Corbet 429*e4624435SJonathan Corbet It is expected that the bootloader will generate these device tree 430*e4624435SJonathan Corbet properties and insert them into the blob prior to kernel entry. 431*e4624435SJonathan Corbet 432- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr' 433 property in their cpu node. This property identifies a 434 naturally-aligned 64-bit zero-initalised memory location. 435 436 These CPUs should spin outside of the kernel in a reserved area of 437 memory (communicated to the kernel by a /memreserve/ region in the 438 device tree) polling their cpu-release-addr location, which must be 439 contained in the reserved region. A wfe instruction may be inserted 440 to reduce the overhead of the busy-loop and a sev will be issued by 441 the primary CPU. When a read of the location pointed to by the 442 cpu-release-addr returns a non-zero value, the CPU must jump to this 443 value. The value will be written as a single 64-bit little-endian 444 value, so CPUs must convert the read value to their native endianness 445 before jumping to it. 446 447- CPUs with a "psci" enable method should remain outside of 448 the kernel (i.e. outside of the regions of memory described to the 449 kernel in the memory node, or in a reserved area of memory described 450 to the kernel by a /memreserve/ region in the device tree). The 451 kernel will issue CPU_ON calls as described in ARM document number ARM 452 DEN 0022A ("Power State Coordination Interface System Software on ARM 453 processors") to bring CPUs into the kernel. 454 455 The device tree should contain a 'psci' node, as described in 456 Documentation/devicetree/bindings/arm/psci.yaml. 457 458- Secondary CPU general-purpose register settings 459 460 - x0 = 0 (reserved for future use) 461 - x1 = 0 (reserved for future use) 462 - x2 = 0 (reserved for future use) 463 - x3 = 0 (reserved for future use) 464