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/openbmc/u-boot/include/
H A Dstm32_rcc.h51 APB2, enumerator
69 u32 apb2rstr; /* RCC APB2 peripheral reset */
76 u32 apb2enr; /* RCC APB2 peripheral clock enable */
83 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun50i-h6-r.c71 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
91 static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
93 static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
95 static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2",
H A Dccu-sun6i-a31.c242 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
339 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
341 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
343 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
345 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
347 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
349 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
351 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
353 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
355 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
[all …]
H A Dccu-sun50i-a100-r.c75 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
107 static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
110 static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
113 static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
H A Dccu-sun8i-r40.c308 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
433 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
435 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
437 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
439 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
445 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
447 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
449 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
451 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
453 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
[all …]
H A Dccu-sun8i-a23.c214 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
275 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
277 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
279 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
281 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
283 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
285 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
287 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
289 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
H A Dccu-sun8i-a33.c224 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
295 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
297 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
299 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
301 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
303 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
H A Dccu-sun50i-h616.c271 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
446 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
447 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
448 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
449 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
450 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
451 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
453 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
[all …]
H A Dccu-sun50i-a64.c268 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
369 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
371 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
373 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
375 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
377 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
379 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
381 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
383 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
385 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
H A Dccu-sun8i-a83t.c269 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
360 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
362 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
364 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
366 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
368 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
370 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
372 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
374 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
H A Dccu-sun50i-h6.c260 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
453 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
456 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
458 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
459 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
460 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
461 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
463 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
[all …]
H A Dccu-sun8i-h3.c189 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
298 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
300 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
302 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
304 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
306 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
308 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
310 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
312 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
314 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
H A Dccu-sun50i-a100.c298 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
461 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
462 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
463 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
464 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
465 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
467 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
468 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
469 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
470 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
H A Dccu-sun8i-v3s.c185 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
254 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
256 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
258 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
260 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
262 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun8i-bus-gates.c22 static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" }; in sun8i_h3_bus_gates_init()
23 enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent; in sun8i_h3_bus_gates_init() enumerator
70 clk_parent = APB2; in sun8i_h3_bus_gates_init()
H A Dclk-simple-gates.c111 CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
121 CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h36 u32 apb2_div; /* 0x58 APB2 divide ratio */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */
129 /* apb2 bit field */
142 /* apb2 gate field */
292 /* apb2 reset */
H A Dclock_sun6i.h36 u32 apb2_div; /* 0x58 APB2 divide ratio */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating */
164 u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
171 /* apb2 bit field */
184 /* apb2 gate field */
491 /* apb2 reset */
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun8i-h3-bus-gates-clk.yaml61 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
62 clock-names = "ahb1", "ahb2", "apb1", "apb2";
H A Dallwinner,sun4i-a10-gates-clk.yaml48 - const: allwinner,sun6i-a31-apb2-gates-clk
49 - const: allwinner,sun8i-a23-apb2-gates-clk
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32h7.c160 u32 apb2rstr; /* 0x98 APB2 Clock Register */
176 u32 apb2enr; /* 0xf0 APB2 Clock Register */
342 APB2, enumerator
579 } else { /* APB2 */ in stm32_get_apb_psc()
581 /* get D2 domain APB2 prescaler */ in stm32_get_apb_psc()
756 return stm32_get_timer_rate(priv, sysclk, APB2); in stm32_clk_get_rate()
759 debug("%s system clock: freq after APB2 prescaler = %ld\n", in stm32_clk_get_rate()
762 return (sysclk / stm32_get_apb_psc(regs, APB2)); in stm32_clk_get_rate()
H A Dclk_stm32f.c356 else /* APB2 */ in stm32_get_apb_shift()
442 /* APB2 CLOCK */ in stm32_clk_get_rate()
476 return stm32_get_timer_rate(priv, sysclk, APB2); in stm32_clk_get_rate()
488 return (sysclk >> stm32_get_apb_shift(regs, APB2)); in stm32_clk_get_rate()
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt32 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
121 1 /*APB2*/
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5.h20 * AHB, APB1 and APB2 prescalers are set to 1 at reset.
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson6.dtsi31 apb2: bus@d0000000 { label

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