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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Anatop Voltage Regulators
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
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/openbmc/linux/drivers/regulator/
H A Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
92 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Danatop.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
35 static struct regmap *anatop; variable
37 static void imx_anatop_enable_weak2p5(bool enable) in imx_anatop_enable_weak2p5() argument
41 regmap_read(anatop, ANADIG_ANA_MISC0, &val); in imx_anatop_enable_weak2p5()
45 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? in imx_anatop_enable_weak2p5()
47 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); in imx_anatop_enable_weak2p5()
50 static void imx_anatop_enable_fet_odrive(bool enable) in imx_anatop_enable_fet_odrive() argument
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
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H A Dmach-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
45 * as they are used for slots1-7 PERST#
54 if (dev->devfn != 0) in ventana_pciesw_early_fixup()
58 dw |= 0xaaa8; // GPIO1-7 outputs in ventana_pciesw_early_fixup()
62 dw |= 0xfe; // GPIO1-7 output high in ventana_pciesw_early_fixup()
87 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); in imx6q_1588_init()
95 * clk-imx6q.c will do needed configuration. in imx6q_1588_init()
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
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H A Dimx6sl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
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H A Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
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H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
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H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
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/openbmc/u-boot/arch/arm/dts/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
16 * Also for U-Boot there must be a pre-existing /memory node.
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <32768>;
[all …]
H A Dimx6ul.dtsi9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
54 #address-cells = <1>;
55 #size-cells = <0>;
58 compatible = "arm,cortex-a7";
61 clock-latency = <61036>; /* two CLK32 periods */
62 operating-points = <
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H A Dimx6ull.dtsi2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ull-pinfunc.h"
14 #include "imx6ull-pinfunc-snvs.h"
52 #address-cells = <1>;
53 #size-cells = <0>;
56 compatible = "arm,cortex-a7";
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H A Dimx6sll.dtsi9 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sll-pinfunc.h"
43 #address-cells = <1>;
44 #size-cells = <0>;
47 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 operating-points = <
58 fsl,soc-operating-points = <
[all …]
H A Dimx7s.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/power/imx7-power.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include "imx7d-pinfunc.h"
52 #address-cells = <1>;
53 #size-cells = <1>;
56 * pre-existing /chosen node to be available to insert the
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/openbmc/linux/drivers/usb/phy/
H A Dphy-mxs-usb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012-2014 Freescale Semiconductor, Inc.
47 #define BM_USBPHY_CTRL_SFTRST BIT(31)
48 #define BM_USBPHY_CTRL_CLKGATE BIT(30)
49 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
50 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
51 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
52 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
53 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
54 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
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/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
27 void enable_ocotp_clk(unsigned char enable) in enable_ocotp_clk() argument
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
32 if (enable) in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
44 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
54 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
[all …]
H A Dsoc.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
63 return readl(&scu->config) & 3; in get_nr_cpus()
68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in get_cpu_rev() local
69 u32 reg = readl(&anatop->digprog_sololite); in get_cpu_rev()
74 reg = readl(&anatop->digprog); in get_cpu_rev()
76 cfg = readl(&scu->config) & 3; in get_cpu_rev()
[all …]
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dimx8mq_evk.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm-generic/gpio.h>
18 #include <asm/mach-imx/gpio.h>
19 #include <asm/mach-imx/mxc_i2c.h>
57 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; in dram_init()
59 gd->ram_size = PHYS_SDRAM_SIZE; in dram_init()
88 /* Use 125M anatop REF_CLK1 for ENET1, not from external */ in setup_fec()
89 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); in setup_fec()
95 /* enable rgmii rxc skew and phy mode select to RGMII copper */ in board_phy_config()
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/openbmc/u-boot/board/k+p/kp_imx6q_tpc/
H A Dkp_imx6q_tpc.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
29 #include <usb/ehci-ci.h>
71 gd->ram_size = imx_ddr_size(); in dram_init()
77 * Use always serial for U-Boot console
120 /* set gpr1[21] to select anatop clock */ in setup_fec_clock()
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/openbmc/u-boot/board/dhelectronics/dh_imx6/
H A Ddh_imx6.c1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
12 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/sata.h>
32 #include <usb/ehci-ci.h>
124 gd->ram_size = imx_ddr_size(); in dram_init()
[all …]
/openbmc/u-boot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/mxc_i2c.h>
69 gd->ram_size = imx_ddr_size(); in dram_init()
187 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */ in setup_fec()
188 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], in setup_fec()
199 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ in board_phy_config()
215 if (phydev->drv->config) in board_phy_config()
[all …]
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dcl-som-imx7.c1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot board functions for CompuLab CL-SOM-iMX7 module
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/arch-mx7/mx7-pins.h>
21 #include <asm/arch-mx7/sys_proto.h>
22 #include <asm/arch-mx7/clock.h>
54 * cl_som_imx7_setup_i2c() - I2C pinmux configuration.
66 gd->ram_size = imx_ddr_size(); in dram_init()
85 * (U-boot device node) (Physical Port) in board_mmc_init()
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/openbmc/u-boot/board/freescale/mx7dsabresd/
H A Dmx7dsabresd.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/mx7-pins.h>
11 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h>
56 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; in board_spi_cs_gpio()
67 gd->ram_size = PHYS_SDRAM_SIZE; in dram_init()
204 devno--; in board_mmc_get_env_dev()
226 return -ENODEV; in board_eth_init()
230 if (ret && ret != -EBUSY) { in board_eth_init()
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/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
14 #include <dt-bindings/clock/imx6sl-clock.h>
19 #define BM_CCSR_PLL1_SW_CLK_SEL BIT(2)
22 #define BM_CDHIPR_ARM_PODF_BUSY BIT(16)
29 #define BM_PLL_ARM_POWERDOWN BIT(12)
30 #define BM_PLL_ARM_ENABLE BIT(13)
31 #define BM_PLL_ARM_LOCK BIT(31)
123 * 396MHz -> 132MHz;
124 * 792MHz -> 158.4MHz;
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