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/openbmc/u-boot/drivers/adc/
H A Dstm32-adc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
10 #include <adc.h>
13 #include "stm32-adc-core.h"
15 /* STM32H7 - Registers for each ADC instance */
26 /* STM32H7_ADC_ISR - bit fields */
31 /* STM32H7_ADC_CR - bit fields */
43 /* STM32H7_ADC_SQR1 - bit fields */
46 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
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H A Dstm32-adc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
12 #include "stm32-adc-core.h"
14 /* STM32H7 - common registers for all ADC instances */
17 /* STM32H7_ADC_CCR - bit fields */
27 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
28 * @ckmode: ADC clock mode, Async or sync with prescaler.
58 static int stm32h7_adc_clk_sel(struct udevice *dev, in stm32h7_adc_clk_sel() argument
65 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ in stm32h7_adc_clk_sel()
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H A Dexynos-adc.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <adc.h>
10 #include <asm/arch/adc.h>
17 int exynos_adc_channel_data(struct udevice *dev, int channel, in exynos_adc_channel_data() argument
20 struct exynos_adc_priv *priv = dev_get_priv(dev); in exynos_adc_channel_data()
21 struct exynos_adc_v2 *regs = priv->regs; in exynos_adc_channel_data()
23 if (channel != priv->active_channel) { in exynos_adc_channel_data()
25 return -EINVAL; in exynos_adc_channel_data()
28 if (ADC_V2_GET_STATUS_FLAG(readl(&regs->status)) != FLAG_CONV_END) in exynos_adc_channel_data()
29 return -EBUSY; in exynos_adc_channel_data()
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H A Dsandbox.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <adc.h>
10 #include <sandbox-adc.h>
13 * struct sandbox_adc_priv - sandbox ADC device's operation status and data
15 * @conversion_status - conversion status: ACTIVE (started) / INACTIVE (stopped)
16 * @conversion_mode - conversion mode: single or multi-channel
17 * @active_channel - active channel number, valid for single channel mode
18 * data[] - channels data
27 int sandbox_adc_start_channel(struct udevice *dev, int channel) in sandbox_adc_start_channel() argument
29 struct sandbox_adc_priv *priv = dev_get_priv(dev); in sandbox_adc_start_channel()
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H A Dadc-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device-internal.h>
13 #include <dm/uclass-internal.h>
14 #include <adc.h>
28 static int check_channel(struct udevice *dev, int value, bool number_or_mask, in check_channel() argument
31 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); in check_channel()
34 /* For the real ADC hardware, some ADC channels can be inactive. in check_channel()
36 * 1-st and 3-rd are valid, then channel mask is: 0b1010, so request in check_channel()
39 if ((uc_pdata->channel_mask >= mask) && (uc_pdata->channel_mask & mask)) in check_channel()
43 __FILE__, caller_function, dev->name); in check_channel()
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H A Drockchip-saradc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Rockchip SARADC driver for U-Boot
9 #include <adc.h>
41 int rockchip_saradc_channel_data(struct udevice *dev, int channel, in rockchip_saradc_channel_data() argument
44 struct rockchip_saradc_priv *priv = dev_get_priv(dev); in rockchip_saradc_channel_data()
45 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); in rockchip_saradc_channel_data()
47 if (channel != priv->active_channel) { in rockchip_saradc_channel_data()
49 return -EINVAL; in rockchip_saradc_channel_data()
52 if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != in rockchip_saradc_channel_data()
54 return -EBUSY; in rockchip_saradc_channel_data()
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H A Dmeson-saradc.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <adc.h>
91 (8 + (((_chan) - 2) * 3))
149 * and u-boot source served as reference). These only seem to be relevant on
185 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); in meson_saradc_get_fifo_count()
194 /* prevent BL30 from using the SAR ADC while we are using it */ in meson_saradc_lock()
195 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_saradc_lock()
200 * wait until BL30 releases it's lock (so we can use the SAR ADC) in meson_saradc_lock()
204 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); in meson_saradc_lock()
205 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); in meson_saradc_lock()
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/openbmc/u-boot/include/
H A Dadc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 /* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */
13 /* The last possible selected channel with 32-bit mask */
17 * adc_data_format: define the ADC output data format, can be useful when
19 * - ADC_DATA_FORMAT_BIN - binary offset
20 * - ADC_DATA_FORMAT_2S - two's complement
31 * struct adc_channel - structure to hold channel conversion data.
32 * Useful to keep the result of a multi-channel conversion output.
34 * @id - channel id
35 * @data - channel conversion data
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/openbmc/u-boot/cmd/
H A Dadc.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <adc.h>
14 struct udevice *dev; in do_adc_list() local
17 ret = uclass_first_device_err(UCLASS_ADC, &dev); in do_adc_list()
19 printf("No available ADC device\n"); in do_adc_list()
24 printf("- %s\n", dev->name); in do_adc_list()
26 ret = uclass_next_device(&dev); in do_adc_list()
29 } while (dev); in do_adc_list()
37 struct udevice *dev; in do_adc_info() local
44 ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], &dev); in do_adc_info()
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/openbmc/u-boot/test/dm/
H A Dadc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Tests for the driver model ADC API
10 #include <adc.h>
19 #include <sandbox-adc.h>
24 struct udevice *dev; in dm_test_adc_bind() local
27 ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); in dm_test_adc_bind()
28 ut_asserteq_str(SANDBOX_ADC_DEVNAME, dev->name); in dm_test_adc_bind()
30 ut_assertok(adc_channel_mask(dev, &channel_mask)); in dm_test_adc_bind()
31 ut_asserteq((1 << SANDBOX_ADC_CHANNELS) - 1, channel_mask); in dm_test_adc_bind()
39 struct udevice *dev; in dm_test_adc_wrong_channel_selection() local
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/openbmc/u-boot/board/samsung/universal_c210/
H A Duniversal.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/adc.h>
25 #include <asm/mach-types.h>
49 struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); in get_adc_value() local
54 writel(channel & 0xF, &adc->adcmux); in get_adc_value()
55 writel((1 << 14) | (49 << 6), &adc->adccon); in get_adc_value()
56 writel(1000 & 0xffff, &adc->adcdly); in get_adc_value()
57 writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ in get_adc_value()
59 writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ in get_adc_value()
64 reg = readl(&adc->adccon); in get_adc_value()
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/openbmc/u-boot/board/samsung/common/
H A Dexynos5-dt-types.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <adc.h>
15 #include <samsung/exynos5-dt-types.h>
30 * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
34 * 0.6 1309 XU4-HC1 0.1
35 * 0.7 1470 XU4-HC1+ 0.1 (HC2)
36 * Use +1% for ADC value tolerance in the array below, the code loops until
37 * the measured ADC value is lower than then ADCmax from the array.
53 if (odroid_info[i].board_type == gd->board_type) in odroid_get_rev()
61 * Read ADC at least twice and check the resuls. If regulator providing voltage
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/openbmc/qemu/hw/arm/
H A Dstm32f205_soc.c29 #include "system/address-spaces.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/qdev-clock.h"
55 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f205_soc_initfn()
57 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); in stm32f205_soc_initfn()
60 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f205_soc_initfn()
65 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f205_soc_initfn()
69 object_initialize_child(obj, "adc-irq-orgate", &s->adc_irqs, TYPE_OR_IRQ); in stm32f205_soc_initfn()
72 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f205_soc_initfn()
76 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f205_soc_initfn()
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H A Dstm32f405_soc.c27 #include "system/address-spaces.h"
30 #include "hw/qdev-clock.h"
61 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f405_soc_initfn()
63 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC); in stm32f405_soc_initfn()
65 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG); in stm32f405_soc_initfn()
68 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f405_soc_initfn()
73 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f405_soc_initfn()
78 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f405_soc_initfn()
82 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f405_soc_initfn()
85 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); in stm32f405_soc_initfn()
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H A Dstellaris.c13 #include "hw/core/split-irq.h"
23 #include "system/address-spaces.h"
29 #include "hw/watchdog/cmsdk-apb-watchdog.h"
32 #include "hw/timer/stellaris-gptm.h"
33 #include "hw/qdev-clock.h"
76 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)
92 #define TYPE_STELLARIS_SYS "stellaris-sys"
113 /* Properties (all read-only registers) */
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
178 uint32_t did0 = s->did0; in ssys_board_class()
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H A Dnpcm8xx.c23 #include "hw/char/serial-mm.h"
27 #include "hw/qdev-clock.h"
28 #include "hw/qdev-properties.h"
54 /* ADC Module */
84 * Interrupt lines going into the GIC. This does not include internal Cortex-A35
175 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
178 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)
198 /* Direct memory-mapped access to SPI0 CS0-1. */
204 /* Direct memory-mapped access to SPI1 CS0-3. */
212 /* Direct memory-mapped access to SPI3 CS0-3. */
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H A Dnpcm7xx.c21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
55 /* ADC Module */
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
171 /* Direct memory-mapped access to SPI0 CS0-1. */
177 /* Direct memory-mapped access to SPI3 CS0-3. */
203 /* Direct memory-mapped access to each SMBus Module. */
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/openbmc/qemu/hw/adc/
H A Dstm32f2xx_adc.c2 * STM32F2XX ADC
30 #include "hw/adc/stm32f2xx_adc.h"
44 static void stm32f2xx_adc_reset(DeviceState *dev) in stm32f2xx_adc_reset() argument
46 STM32F2XXADCState *s = STM32F2XX_ADC(dev); in stm32f2xx_adc_reset()
48 s->adc_sr = 0x00000000; in stm32f2xx_adc_reset()
49 s->adc_cr1 = 0x00000000; in stm32f2xx_adc_reset()
50 s->adc_cr2 = 0x00000000; in stm32f2xx_adc_reset()
51 s->adc_smpr1 = 0x00000000; in stm32f2xx_adc_reset()
52 s->adc_smpr2 = 0x00000000; in stm32f2xx_adc_reset()
53 s->adc_jofr[0] = 0x00000000; in stm32f2xx_adc_reset()
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H A Daspeed_adc.c2 * Aspeed ADC
4 * Copyright 2017-2021 IBM Corp.
8 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
17 #include "hw/adc/aspeed_adc.h"
34 #define ASPEED_ADC_L_MASK ((1 << 10) - 1)
38 #define LOWER_CHANNEL_MASK ((1 << 10) - 1)
72 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in breaks_threshold()
74 int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2; in breaks_threshold()
76 uint32_t a_and_b = s->regs[reg]; in breaks_threshold()
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/openbmc/qemu/hw/input/
H A Dadb-mouse.c30 #include "adb-internal.h"
58 static void adb_mouse_handle_event(DeviceState *dev, QemuConsole *src, in adb_mouse_handle_event() argument
61 MouseState *s = (MouseState *)dev; in adb_mouse_handle_event()
69 switch (evt->type) { in adb_mouse_handle_event()
71 move = evt->u.rel.data; in adb_mouse_handle_event()
72 if (move->axis == INPUT_AXIS_X) { in adb_mouse_handle_event()
73 s->dx += move->value; in adb_mouse_handle_event()
74 } else if (move->axis == INPUT_AXIS_Y) { in adb_mouse_handle_event()
75 s->dy += move->value; in adb_mouse_handle_event()
80 btn = evt->u.btn.data; in adb_mouse_handle_event()
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H A Dadb.c27 #include "hw/qdev-properties.h"
31 #include "adb-internal.h"
35 #define ADB_RET_NOTPRESENT (-2)
53 ADBDeviceClass *adc; in do_adb_request() local
58 for (i = 0; i < s->nb_devices; i++) { in do_adb_request()
59 d = s->devices[i]; in do_adb_request()
62 s->status = 0; in do_adb_request()
66 s->pending = 0; in do_adb_request()
67 for (i = 0; i < s->nb_devices; i++) { in do_adb_request()
68 d = s->devices[i]; in do_adb_request()
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H A Dadb-kbd.c30 #include "hw/input/adb-keys.h"
31 #include "adb-internal.h"
182 if (s->count < sizeof(s->data)) { in adb_kbd_put_keycode()
183 s->data[s->wptr] = keycode; in adb_kbd_put_keycode()
184 if (++s->wptr == sizeof(s->data)) { in adb_kbd_put_keycode()
185 s->wptr = 0; in adb_kbd_put_keycode()
187 s->count++; in adb_kbd_put_keycode()
196 if (s->count == 0) { in adb_kbd_poll()
199 keycode = s->data[s->rptr]; in adb_kbd_poll()
200 s->rptr++; in adb_kbd_poll()
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/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5ek.dtsi2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
12 model = "Atmel AT91SAM9X5-EK";
16 bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 stdout-path = "serial0:115200n8";
18 u-boot,dm-pre-reloc;
24 pinctrl-0 = <
31 bus-width = <4>;
32 cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
37 pinctrl-0 = <
44 bus-width = <4>;
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/openbmc/qemu/tests/qtest/
H A Dac97-test.c7 * See the COPYING file in the top-level directory.
20 QPCIDevice dev; member
27 if (!g_strcmp0(interface, "pci-device")) { in ac97_get_driver()
28 return &ac97->dev; in ac97_get_driver()
40 qpci_device_init(&ac97->dev, bus, addr); in ac97_create()
41 ac97->obj.get_driver = ac97_get_driver; in ac97_create()
42 return &ac97->obj; in ac97_create()
53 QPCIDevice *dev = &ac97->dev; in ac97_playback_upsample() local
56 qpci_device_enable(dev); in ac97_playback_upsample()
57 bar0 = qpci_iomap(dev, 0, NULL); in ac97_playback_upsample()
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/openbmc/u-boot/board/amlogic/odroid-c2/
H A DREADME.odroid-c21 U-Boot for ODROID-C2
4 ODROID-C2 is a single board computer manufactured by Hardkernel
7 - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
8 - ARM Mali 450 GPU
9 - 2GB DDR3 SDRAM
10 - Gigabit Ethernet
11 - HDMI 2.0 4K/60Hz display
12 - 40-pin GPIO header
13 - 4 x USB 2.0 Host, 1 x USB OTG
14 - eMMC, microSD
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