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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A DMakefile3 zynq-cc108.dtb \
4 zynq-ebaz4205.dtb \
5 zynq-microzed.dtb \
6 zynq-parallella.dtb \
7 zynq-zc702.dtb \
8 zynq-zc706.dtb \
9 zynq-zc770-xm010.dtb \
10 zynq-zc770-xm011.dtb \
11 zynq-zc770-xm012.dtb \
12 zynq-zc770-xm013.dtb \
[all …]
H A Dzynq-zturn-v5.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board V5";
8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
H A Dzynq-zturn.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board";
8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
H A Dzynq-7000.dtsi9 compatible = "xlnx,zynq-7000";
103 compatible = "xlnx,zynq-xadc-1.00.a";
111 compatible = "xlnx,zynq-can-1.0";
123 compatible = "xlnx,zynq-can-1.0";
135 compatible = "xlnx,zynq-gpio-1.0";
189 compatible = "xlnx,zynq-ddrc-a05";
212 compatible = "xlnx,zynq-spi-r1p6";
224 compatible = "xlnx,zynq-spi-r1p6";
236 compatible = "xlnx,zynq-qspi-1.0";
248 compatible = "xlnx,zynq-gem", "cdns,gem";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
23 - digilent,zynq-zybo
24 - digilent,zynq-zybo-z7
26 - myir,zynq-zturn-v5
27 - myir,zynq-zturn
28 - xlnx,zynq-cc108
29 - xlnx,zynq-zc702
30 - xlnx,zynq-zc706
31 - xlnx,zynq-zc770-xm010
[all …]
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c2 * Xilinx Zynq Baseboard System emulation.
28 #include "hw/adc/zynq-xadc.h"
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
237 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, in zynq_init()
244 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, in zynq_init()
378 * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and in zynq_init()
379 * the zynq-7000.dtsi. Add placeholders for unimplemented devices. in zynq_init()
381 create_unimplemented_device("zynq.i2c0", 0xE0004000, 4 * KiB); in zynq_init()
382 create_unimplemented_device("zynq.i2c1", 0xE0005000, 4 * KiB); in zynq_init()
383 create_unimplemented_device("zynq.can0", 0xE0008000, 4 * KiB); in zynq_init()
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
3 The Zynq 7000 family is based on the AMD SoC architecture. These products
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
18 - Zynq SLCR
36 $ qemu-system-aarch64 -M xilinx-zynq-a9 \
37 -dtb zynq-zc702.dtb -serial null -serial mon:stdio \
/openbmc/u-boot/doc/
H A DREADME.zynq3 # Xilinx ZYNQ U-Boot
9 This document describes the information about Xilinx Zynq U-Boot -
12 2. Zynq boards
14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
36 Zynq has a facility to read the bootmode from the slcr bootmode register
57 - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
58 - Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
59 - Added zynq drivers:
68 - Added basic FDT support for zynq boards
79 [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
/openbmc/u-boot/board/xilinx/
H A DKconfig8 string "Zynq/ZynqMP PS init file(s) location"
10 On Zynq and ZynqMP U-Boot SPL (or U-Boot proper if
14 psu_init_gpl.c on ZynqMP, ps7_init_gpl.c for Zynq-7000)
30 board/xilinx/zynq/$(CONFIG_DEFAULT_DEVICE_TREE)/ps7_init_gpl.c
31 for Zynq-7000, or
36 board/xilinx/zynq/ps7_init_gpl.c for Zynq-7000, or
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
12 compatible = "xlnx,zynq-7000";
74 compatible = "xlnx,zynq-xadc-1.00.a";
82 compatible = "xlnx,zynq-can-1.0";
94 compatible = "xlnx,zynq-can-1.0";
106 compatible = "xlnx,zynq-gpio-1.0";
158 compatible = "xlnx,zynq-ddrc-a05";
181 compatible = "xlnx,zynq-spi-r1p6";
193 compatible = "xlnx,zynq-spi-r1p6";
[all …]
H A Dzynq-microzed.dts8 #include "zynq-7000.dtsi"
11 model = "Zynq MicroZED Board";
12 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
H A DMakefile182 zynq-cc108.dtb \
183 zynq-cse-nand.dtb \
184 zynq-cse-nor.dtb \
185 zynq-cse-qspi-single.dtb \
186 zynq-dlc20-rev1.0.dtb \
187 zynq-microzed.dtb \
188 zynq-minized.dtb \
189 zynq-picozed.dtb \
190 zynq-syzygy-hub.dtb \
191 zynq-topic-miami.dtb \
[all …]
H A Dzynq-picozed.dts8 #include "zynq-7000.dtsi"
11 model = "Zynq PicoZed Board";
12 compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
H A Dzynq-cse-nor.dts8 #include "zynq-7000.dtsi"
13 model = "Zynq CSE NOR Board";
14 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
53 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
/openbmc/u-boot/board/xilinx/zynq/
H A DKconfig8 bool "Enable Zynq specific commands"
11 Enables Zynq specific commands.
14 bool "Enable zynq aes command for decryption of encrypted images"
22 bool "Enable zynq rsa command for loading secure images"
27 Enabling this will support zynq secure image verification.
H A DMAINTAINERS1 ZYNQ BOARD
4 F: arch/arm/dts/zynq-*
5 F: board/xilinx/zynq/
6 F: include/configs/zynq*.h
/openbmc/linux/drivers/net/can/ctucanfd/
H A DKconfig7 The core integration to Xilinx Zynq system as platform driver
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
30 modified to be CAN FD frames tolerant on MicroZed Zynq based
32 company. FPGA design https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top.
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
7 title: Zynq A05 DDR Memory Controller
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
/openbmc/u-boot/arch/arm/mach-zynq/
H A DKconfig4 default "arch/arm/mach-zynq/u-boot-spl.lds"
31 bool "Zynq DDRC initialization"
40 default "zynq"
47 default "zynq"
51 default "zynq-common"
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dxlnx,zynq-qspi.yaml4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
19 (usually 33 MHz oscillators are used for Zynq platforms)
/openbmc/u-boot/include/configs/
H A Dzynq_cse.h5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
16 #include <configs/zynq-common.h>
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
7 title: Xilinx Zynq GPIO controller
15 - xlnx,zynq-gpio-1.0
63 - xlnx,zynq-gpio-1.0
108 compatible = "xlnx,zynq-gpio-1.0";
/openbmc/u-boot/configs/
H A Dtopic_miamiplus_defconfig10 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
16 CONFIG_SYS_PROMPT="zynq-uboot> "
29 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"

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