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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dxor_regs.h10 * For controllers that have two XOR units, then chans 2 & 3 will be
19 /* XOR Engine Control Register Map */
26 /* XOR Engine Interrupt Register Map */
32 /* XOR Engine Descriptor Register Map */
40 /* XOR Engine ECC/Mem_init Register Map */
51 /* XOR Engine Debug Register Map */
54 /* XOR register fileds */
56 /* XOR Engine Channel Arbiter Register */
60 /* XOR Engine [0..1] Configuration Registers */
82 /* XOR Engine [0..1] Activation Registers */
[all …]
H A Dxor.h11 #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
36 * This enumerator describes the type of functionality the XOR channel
40 MV_XOR, /* XOR channel functions as XOR accelerator */
41 MV_DMA, /* XOR channel functions as IDMA channel */
42 MV_CRC32 /* XOR channel functions as CRC 32 calculator */
54 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
H A Dxor.c110 * mv_xor_hal_init - Initialize XOR engine
113 * This function initialize XOR unit.
127 /* Abort any XOR activity & set default configuration */ in mv_xor_hal_init()
137 * mv_xor_ctrl_set - Set XOR channel control registers
155 /* update the XOR Engine [0..1] Configuration Registers (XEx_c_r) */ in mv_xor_ctrl_set()
191 * update the start_ptr field in XOR Engine [0..1] Destination Pointer in mv_xor_mem_init()
197 * update the Block_size field in the XOR Engine[0..1] Block Size in mv_xor_mem_init()
204 * update the field Init_val_l in the XOR Engine Initial Value Register in mv_xor_mem_init()
210 * update the field Init_val_h in the XOR Engine Initial Value Register in mv_xor_mem_init()
223 * mv_xor_state_get - Get XOR channel state.
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dxor.c13 #include "xor.h"
98 * mv_xor_hal_init - Initialize XOR engine
101 * This function initialize XOR unit.
115 /* Abort any XOR activity & set default configuration */ in mv_xor_hal_init()
125 * mv_xor_ctrl_set - Set XOR channel control registers
144 /* Update the XOR Engine [0..1] Configuration Registers (XExCR) */ in mv_xor_ctrl_set()
177 * Update the start_ptr field in XOR Engine [0..1] Destination Pointer in mv_xor_mem_init()
183 * Update the BlockSize field in the XOR Engine[0..1] Block Size in mv_xor_mem_init()
190 * Update the field InitValL in the XOR Engine Initial Value Register in mv_xor_mem_init()
196 * Update the field InitValH in the XOR Engine Initial Value Register in mv_xor_mem_init()
[all …]
H A Dxor.h14 * This enumerator describes the type of functionality the XOR channel
18 MV_XOR, /* XOR channel functions as XOR accelerator */
19 MV_DMA, /* XOR channel functions as IDMA channel */
20 MV_CRC32 /* XOR channel functions as CRC 32 calculator */
25 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
50 /* XOR descriptor structure for CRC and DMA descriptor */
H A Dxor_regs.h10 * For controllers that have two XOR units, then chans 2 & 3 will be mapped
19 /* XOR Engine Control Register Map */
24 /* XOR Engine Interrupt Register Map */
30 /* XOR Engine Descriptor Register Map */
43 /* XOR register fileds */
45 /* XOR Engine [0..1] Configuration Registers (XExCR) */
67 /* XOR Engine [0..1] Activation Registers (XExACTR) */
82 /* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */
89 /* XOR Engine[0..1] Block Size Registers (XExBSR) */
95 /* XOR Engine Address Decoding Register Map */
/openbmc/qemu/pc-bios/optionrom/
H A Dlinuxboot.S63 xor %ax, %ax
67 xor %eax, %eax
68 xor %ebx, %ebx
69 xor %ecx, %ecx
70 xor %edx, %edx
71 xor %edi, %edi
72 xor %ebp, %ebp
83 xor %edi, %edi
96 xor %es:0x22c, %eax // if it matches es:0x22c
105 xor %cx, %cx
[all …]
H A Dlinuxboot_dma.c205 "xor %%ebx, %%ebx\n" in load_kernel()
206 "xor %%ecx, %%ecx\n" in load_kernel()
207 "xor %%edx, %%edx\n" in load_kernel()
208 "xor %%edi, %%edi\n" in load_kernel()
209 "xor %%ebp, %%ebp\n" in load_kernel()
H A Dmultiboot.S67 xor %eax, %eax
91 xor %ebx, %ebx
93 xor %edi, %edi
128 xor %di, %di
154 xor %di, %di
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_rst0.S31 test xor
36 xor a5, a2, a4
38 xor a2, a2, a4
40 xor a3, a4, a3
/openbmc/u-boot/arch/arm/dts/
H A Darmada-ap806.dtsi180 xor@400000 {
181 compatible = "marvell,mv-xor-v2";
188 xor@420000 {
189 compatible = "marvell,mv-xor-v2";
196 xor@440000 {
197 compatible = "marvell,mv-xor-v2";
204 xor@460000 {
205 compatible = "marvell,mv-xor-v2";
H A Darmada-xp.dtsi212 xor@60900 {
213 compatible = "marvell,orion-xor";
222 dmacap,xor;
227 dmacap,xor;
240 xor@f0900 {
241 compatible = "marvell,orion-xor";
250 dmacap,xor;
255 dmacap,xor;
H A Dkirkwood.dtsi273 dma0: xor@60800 {
274 compatible = "marvell,orion-xor";
283 dmacap,xor;
288 dmacap,xor;
293 dma1: xor@60900 {
294 compatible = "marvell,orion-xor";
303 dmacap,xor;
308 dmacap,xor;
H A Darmada-cp110-slave.dtsi114 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
186 cps_xor0: xor@6a0000 {
187 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
195 cps_xor1: xor@6c0000 {
196 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
H A Darmada-38x.dtsi448 xor0: xor@60800 {
449 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
458 dmacap,xor;
463 dmacap,xor;
468 xor1: xor@60900 {
469 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
478 dmacap,xor;
483 dmacap,xor;
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Network/Experimental/
H A DBond.interface.yaml25 balance-xor, 802.3ad, and tlb modes.
42 - name: XOR
67 This policy uses XOR of hardware MAC addresses and packet type
/openbmc/u-boot/arch/arm/mach-mvebu/
H A DMakefile24 obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
25 obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
26 obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dethernet_interface.hpp47 XOR, enumerator
99 {TeamMode::XOR, "XOR"},
/openbmc/qemu/tests/tcg/riscv64/
H A Dtest-aes.c31 "xor %0,%0,%4\n\t" in test_SB_SR_MC_AK()
32 "xor %1,%1,%5" in test_SB_SR_MC_AK()
76 "xor %0,%0,%4\n\t" in test_ISB_ISR_IMC_AK()
77 "xor %1,%1,%5" in test_ISB_ISR_IMC_AK()
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386-code16.S19 xor %eax, %eax
35 xor %bx, %bx
/openbmc/u-boot/post/drivers/
H A Dmemory.c86 * xor the address with a '1' bit to flip one address line. For each
243 ulong xor; in memory_post_addrline() local
247 xor = 0; in memory_post_addrline()
248 for(xor = sizeof(ulong); xor > 0; xor <<= 1) { in memory_post_addrline()
249 target = (ulong *)((ulong)testaddr ^ xor); in memory_post_addrline()
255 if(xor == 0x00008000) { in memory_post_addrline()
261 "XOR value %08x !\n", in memory_post_addrline()
262 testaddr, target, xor); in memory_post_addrline()
/openbmc/qemu/tests/tcg/openrisc/
H A Dtest_and_or.c45 ("l.xor %0, %1, %2\n\t" in main()
50 printf("xor error\n"); in main()
/openbmc/u-boot/test/lib/
H A Dstring.c18 /* Xor mask used for marking memory regions */
28 * The buffer is filled with incrementing values xor'ed with the mask.
31 * @mask: xor mask
102 * @mask: xor mask used to initialize source buffer
/openbmc/u-boot/drivers/mtd/ubi/
H A Dcrc32.c12 * Some xor at the end with ~0. The generic crc32() function takes
13 * seed as an argument, and doesn't xor at the end. Then individual
15 * drivers/net/smc9194.c uses seed ~0, doesn't xor with ~0.
16 * fs/jffs2 uses seed 0, doesn't xor with ~0.
17 * fs/partitions/efi.c uses seed ~0, xor's with ~0.
103 /* load data 32 bits wide, xor data 32 bits wide. */ in crc32_le()
201 /* load data 32 bits wide, xor data 32 bits wide. */ in crc32_be()
264 * subtract, we just xor. Thus, we tend to get a bit sloppy about
286 * XOR cancel, it's just a copy of bit 32 of the remainder.
346 * If the input is a multiple of 32 bits, you can even XOR in a 32-bit
[all …]
/openbmc/qemu/linux-user/x86_64/
H A Dvdso.S55 xor %ecx, %ecx /* rdtscp w/ tsc_aux = 0 */
70 2: xor %eax, %eax

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