1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _XOR_REGS_h 7f1df9364SStefan Roese #define _XOR_REGS_h 8f1df9364SStefan Roese 9f1df9364SStefan Roese /* 10f1df9364SStefan Roese * For controllers that have two XOR units, then chans 2 & 3 will be 11f1df9364SStefan Roese * mapped to channels 0 & 1 of unit 1 12f1df9364SStefan Roese */ 13f1df9364SStefan Roese #define XOR_UNIT(chan) ((chan) >> 1) 14f1df9364SStefan Roese #define XOR_CHAN(chan) ((chan) & 1) 15f1df9364SStefan Roese 16f1df9364SStefan Roese #define MV_XOR_REGS_OFFSET(unit) (0x60900) 17f1df9364SStefan Roese #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) 18f1df9364SStefan Roese 19f1df9364SStefan Roese /* XOR Engine Control Register Map */ 20f1df9364SStefan Roese #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) 21f1df9364SStefan Roese #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 22f1df9364SStefan Roese (0x10 + ((chan) * 4))) 23f1df9364SStefan Roese #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 24f1df9364SStefan Roese (0x20 + ((chan) * 4))) 25f1df9364SStefan Roese 26f1df9364SStefan Roese /* XOR Engine Interrupt Register Map */ 27f1df9364SStefan Roese #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x30)) 28f1df9364SStefan Roese #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x40)) 29f1df9364SStefan Roese #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x50)) 30f1df9364SStefan Roese #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x60)) 31f1df9364SStefan Roese 32f1df9364SStefan Roese /* XOR Engine Descriptor Register Map */ 33f1df9364SStefan Roese #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 34f1df9364SStefan Roese (0x200 + ((chan) * 4))) 35f1df9364SStefan Roese #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 36f1df9364SStefan Roese (0x210 + ((chan) * 4))) 37f1df9364SStefan Roese #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 38f1df9364SStefan Roese (0x220 + ((chan) * 4))) 39f1df9364SStefan Roese 40f1df9364SStefan Roese /* XOR Engine ECC/Mem_init Register Map */ 41f1df9364SStefan Roese #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 42f1df9364SStefan Roese (0x2b0 + ((chan) * 4))) 43f1df9364SStefan Roese #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 44f1df9364SStefan Roese (0x2c0 + ((chan) * 4))) 45f1df9364SStefan Roese #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d0)) 46f1df9364SStefan Roese #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d4)) 47f1df9364SStefan Roese #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d8)) 48f1df9364SStefan Roese #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e0)) 49f1df9364SStefan Roese #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e4)) 50f1df9364SStefan Roese 51f1df9364SStefan Roese /* XOR Engine Debug Register Map */ 52f1df9364SStefan Roese #define XOR_DEBUG_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x70)) 53f1df9364SStefan Roese 54f1df9364SStefan Roese /* XOR register fileds */ 55f1df9364SStefan Roese 56f1df9364SStefan Roese /* XOR Engine Channel Arbiter Register */ 57f1df9364SStefan Roese #define XECAR_SLICE_OFFS(slice_num) (slice_num) 58f1df9364SStefan Roese #define XECAR_SLICE_MASK(slice_num) (1 << (XECAR_SLICE_OFFS(slice_num))) 59f1df9364SStefan Roese 60f1df9364SStefan Roese /* XOR Engine [0..1] Configuration Registers */ 61f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_OFFS (0) 62f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) 63f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) 64f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) 65f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) 66f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) 67f1df9364SStefan Roese #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) 68f1df9364SStefan Roese 69f1df9364SStefan Roese #define XEXCR_SRC_BURST_LIMIT_OFFS (4) 70f1df9364SStefan Roese #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) 71f1df9364SStefan Roese #define XEXCR_DST_BURST_LIMIT_OFFS (8) 72f1df9364SStefan Roese #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) 73f1df9364SStefan Roese #define XEXCR_DRD_RES_SWP_OFFS (12) 74f1df9364SStefan Roese #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) 75f1df9364SStefan Roese #define XEXCR_DWR_REQ_SWP_OFFS (13) 76f1df9364SStefan Roese #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) 77f1df9364SStefan Roese #define XEXCR_DES_SWP_OFFS (14) 78f1df9364SStefan Roese #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) 79f1df9364SStefan Roese #define XEXCR_REG_ACC_PROTECT_OFFS (15) 80f1df9364SStefan Roese #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) 81f1df9364SStefan Roese 82f1df9364SStefan Roese /* XOR Engine [0..1] Activation Registers */ 83f1df9364SStefan Roese #define XEXACTR_XESTART_OFFS (0) 84f1df9364SStefan Roese #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) 85f1df9364SStefan Roese #define XEXACTR_XESTOP_OFFS (1) 86f1df9364SStefan Roese #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) 87f1df9364SStefan Roese #define XEXACTR_XEPAUSE_OFFS (2) 88f1df9364SStefan Roese #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) 89f1df9364SStefan Roese #define XEXACTR_XERESTART_OFFS (3) 90f1df9364SStefan Roese #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) 91f1df9364SStefan Roese #define XEXACTR_XESTATUS_OFFS (4) 92f1df9364SStefan Roese #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) 93f1df9364SStefan Roese #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) 94f1df9364SStefan Roese #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) 95f1df9364SStefan Roese #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) 96f1df9364SStefan Roese 97f1df9364SStefan Roese /* XOR Engine Interrupt Cause Register (XEICR) */ 98f1df9364SStefan Roese #define XEICR_CHAN_OFFS 16 99f1df9364SStefan Roese #define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS) 100f1df9364SStefan Roese #define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan))) 101f1df9364SStefan Roese #define XEICR_COMP_MASK_ALL 0x000f000f 102f1df9364SStefan Roese #define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan)) 103f1df9364SStefan Roese #define XEICR_ERR_MASK 0x03800380 104f1df9364SStefan Roese 105f1df9364SStefan Roese /* XOR Engine Error Cause Register (XEECR) */ 106f1df9364SStefan Roese #define XEECR_ERR_TYPE_OFFS 0 107f1df9364SStefan Roese #define XEECR_ERR_TYPE_MASK (0x1f << XEECR_ERR_TYPE_OFFS) 108f1df9364SStefan Roese 109f1df9364SStefan Roese /* XOR Engine Error Address Register (XEEAR) */ 110f1df9364SStefan Roese #define XEEAR_ERR_ADDR_OFFS (0) 111f1df9364SStefan Roese #define XEEAR_ERR_ADDR_MASK (0xffffffff << XEEAR_ERR_ADDR_OFFS) 112f1df9364SStefan Roese 113f1df9364SStefan Roese /* XOR Engine [0..1] Next Descriptor Pointer Register */ 114f1df9364SStefan Roese #define XEXNDPR_NEXT_DESC_PTR_OFFS (0) 115f1df9364SStefan Roese #define XEXNDPR_NEXT_DESC_PTR_MASK (0xffffffff << \ 116f1df9364SStefan Roese XEXNDPR_NEXT_DESC_PTR_OFFS) 117f1df9364SStefan Roese 118f1df9364SStefan Roese /* XOR Engine [0..1] Current Descriptor Pointer Register */ 119f1df9364SStefan Roese #define XEXCDPR_CURRENT_DESC_PTR_OFFS (0) 120f1df9364SStefan Roese #define XEXCDPR_CURRENT_DESC_PTR_MASK (0xffffffff << \ 121f1df9364SStefan Roese XEXCDPR_CURRENT_DESC_PTR_OFFS) 122f1df9364SStefan Roese 123f1df9364SStefan Roese /* XOR Engine [0..1] Byte Count Register */ 124f1df9364SStefan Roese #define XEXBCR_BYTE_CNT_OFFS (0) 125f1df9364SStefan Roese #define XEXBCR_BYTE_CNT_MASK (0xffffffff << XEXBCR_BYTE_CNT_OFFS) 126f1df9364SStefan Roese 127f1df9364SStefan Roese /* XOR Engine [0..1] Destination Pointer Register */ 128f1df9364SStefan Roese #define XEXDPR_DST_PTR_OFFS (0) 129f1df9364SStefan Roese #define XEXDPR_DST_PTR_MASK (0xffffffff << XEXDPR_DST_PTR_OFFS) 130f1df9364SStefan Roese #define XEXDPR_DST_PTR_XOR_MASK (0x3f) 131f1df9364SStefan Roese #define XEXDPR_DST_PTR_DMA_MASK (0x1f) 132f1df9364SStefan Roese #define XEXDPR_DST_PTR_CRC_MASK (0x1f) 133f1df9364SStefan Roese 134f1df9364SStefan Roese /* XOR Engine[0..1] Block Size Registers */ 135f1df9364SStefan Roese #define XEXBSR_BLOCK_SIZE_OFFS (0) 136f1df9364SStefan Roese #define XEXBSR_BLOCK_SIZE_MASK (0xffffffff << XEXBSR_BLOCK_SIZE_OFFS) 137f1df9364SStefan Roese #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) 138f1df9364SStefan Roese #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xffffffff) 139f1df9364SStefan Roese 140f1df9364SStefan Roese /* XOR Engine Timer Mode Control Register (XETMCR) */ 141f1df9364SStefan Roese #define XETMCR_TIMER_EN_OFFS (0) 142f1df9364SStefan Roese #define XETMCR_TIMER_EN_MASK (1 << XETMCR_TIMER_EN_OFFS) 143f1df9364SStefan Roese #define XETMCR_TIMER_EN_ENABLE (1 << XETMCR_TIMER_EN_OFFS) 144f1df9364SStefan Roese #define XETMCR_TIMER_EN_DISABLE (0 << XETMCR_TIMER_EN_OFFS) 145f1df9364SStefan Roese #define XETMCR_SECTION_SIZE_CTRL_OFFS (8) 146f1df9364SStefan Roese #define XETMCR_SECTION_SIZE_CTRL_MASK (0x1f << XETMCR_SECTION_SIZE_CTRL_OFFS) 147f1df9364SStefan Roese #define XETMCR_SECTION_SIZE_MIN_VALUE (7) 148f1df9364SStefan Roese #define XETMCR_SECTION_SIZE_MAX_VALUE (31) 149f1df9364SStefan Roese 150f1df9364SStefan Roese /* XOR Engine Timer Mode Initial Value Register (XETMIVR) */ 151f1df9364SStefan Roese #define XETMIVR_TIMER_INIT_VAL_OFFS (0) 152f1df9364SStefan Roese #define XETMIVR_TIMER_INIT_VAL_MASK (0xffffffff << \ 153f1df9364SStefan Roese XETMIVR_TIMER_INIT_VAL_OFFS) 154f1df9364SStefan Roese 155f1df9364SStefan Roese /* XOR Engine Timer Mode Current Value Register (XETMCVR) */ 156f1df9364SStefan Roese #define XETMCVR_TIMER_CRNT_VAL_OFFS (0) 157f1df9364SStefan Roese #define XETMCVR_TIMER_CRNT_VAL_MASK (0xffffffff << \ 158f1df9364SStefan Roese XETMCVR_TIMER_CRNT_VAL_OFFS) 159f1df9364SStefan Roese 160f1df9364SStefan Roese /* XOR Engine Initial Value Register Low (XEIVRL) */ 161f1df9364SStefan Roese #define XEIVRL_INIT_VAL_L_OFFS (0) 162f1df9364SStefan Roese #define XEIVRL_INIT_VAL_L_MASK (0xffffffff << XEIVRL_INIT_VAL_L_OFFS) 163f1df9364SStefan Roese 164f1df9364SStefan Roese /* XOR Engine Initial Value Register High (XEIVRH) */ 165f1df9364SStefan Roese #define XEIVRH_INIT_VAL_H_OFFS (0) 166f1df9364SStefan Roese #define XEIVRH_INIT_VAL_H_MASK (0xffffffff << XEIVRH_INIT_VAL_H_OFFS) 167f1df9364SStefan Roese 168f1df9364SStefan Roese /* XOR Engine Debug Register (XEDBR) */ 169f1df9364SStefan Roese #define XEDBR_PARITY_ERR_INSR_OFFS (0) 170f1df9364SStefan Roese #define XEDBR_PARITY_ERR_INSR_MASK (1 << XEDBR_PARITY_ERR_INSR_OFFS) 171f1df9364SStefan Roese #define XEDBR_XBAR_ERR_INSR_OFFS (1) 172f1df9364SStefan Roese #define XEDBR_XBAR_ERR_INSR_MASK (1 << XEDBR_XBAR_ERR_INSR_OFFS) 173f1df9364SStefan Roese 174f1df9364SStefan Roese /* XOR Engine address decode registers. */ 175f1df9364SStefan Roese /* Maximum address decode windows */ 176f1df9364SStefan Roese #define XOR_MAX_ADDR_DEC_WIN 8 177f1df9364SStefan Roese /* Maximum address arbiter windows */ 178f1df9364SStefan Roese #define XOR_MAX_REMAP_WIN 4 179f1df9364SStefan Roese 180f1df9364SStefan Roese /* XOR Engine Address Decoding Register Map */ 181f1df9364SStefan Roese #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 182f1df9364SStefan Roese (0x240 + ((chan) * 4))) 183f1df9364SStefan Roese #define XOR_BASE_ADDR_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 184f1df9364SStefan Roese (0x250 + ((win_num) * 4))) 185f1df9364SStefan Roese #define XOR_SIZE_MASK_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 186f1df9364SStefan Roese (0x270 + ((win_num) * 4))) 187f1df9364SStefan Roese #define XOR_HIGH_ADDR_REMAP_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 188f1df9364SStefan Roese (0x290 + ((win_num) * 4))) 189f1df9364SStefan Roese #define XOR_ADDR_OVRD_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 190f1df9364SStefan Roese (0x2a0 + ((win_num) * 4))) 191f1df9364SStefan Roese 192f1df9364SStefan Roese /* XOR Engine [0..1] Window Control Registers */ 193f1df9364SStefan Roese #define XEXWCR_WIN_EN_OFFS(win_num) (win_num) 194f1df9364SStefan Roese #define XEXWCR_WIN_EN_MASK(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 195f1df9364SStefan Roese #define XEXWCR_WIN_EN_ENABLE(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 196f1df9364SStefan Roese #define XEXWCR_WIN_EN_DISABLE(win_num) (0 << (XEXWCR_WIN_EN_OFFS(win_num))) 197f1df9364SStefan Roese 198f1df9364SStefan Roese #define XEXWCR_WIN_ACC_OFFS(win_num) ((2 * win_num) + 16) 199f1df9364SStefan Roese #define XEXWCR_WIN_ACC_MASK(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 200f1df9364SStefan Roese #define XEXWCR_WIN_ACC_NO_ACC(win_num) (0 << (XEXWCR_WIN_ACC_OFFS(win_num))) 201f1df9364SStefan Roese #define XEXWCR_WIN_ACC_RO(win_num) (1 << (XEXWCR_WIN_ACC_OFFS(win_num))) 202f1df9364SStefan Roese #define XEXWCR_WIN_ACC_RW(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 203f1df9364SStefan Roese 204f1df9364SStefan Roese /* XOR Engine Base Address Registers (XEBARx) */ 205f1df9364SStefan Roese #define XEBARX_TARGET_OFFS (0) 206f1df9364SStefan Roese #define XEBARX_TARGET_MASK (0xf << XEBARX_TARGET_OFFS) 207f1df9364SStefan Roese #define XEBARX_ATTR_OFFS (8) 208f1df9364SStefan Roese #define XEBARX_ATTR_MASK (0xff << XEBARX_ATTR_OFFS) 209f1df9364SStefan Roese #define XEBARX_BASE_OFFS (16) 210f1df9364SStefan Roese #define XEBARX_BASE_MASK (0xffff << XEBARX_BASE_OFFS) 211f1df9364SStefan Roese 212f1df9364SStefan Roese /* XOR Engine Size Mask Registers (XESMRx) */ 213f1df9364SStefan Roese #define XESMRX_SIZE_MASK_OFFS (16) 214f1df9364SStefan Roese #define XESMRX_SIZE_MASK_MASK (0xffff << XESMRX_SIZE_MASK_OFFS) 215f1df9364SStefan Roese #define XOR_WIN_SIZE_ALIGN _64K 216f1df9364SStefan Roese 217f1df9364SStefan Roese /* XOR Engine High Address Remap Register (XEHARRx1) */ 218f1df9364SStefan Roese #define XEHARRX_REMAP_OFFS (0) 219f1df9364SStefan Roese #define XEHARRX_REMAP_MASK (0xffffffff << XEHARRX_REMAP_OFFS) 220f1df9364SStefan Roese 221f1df9364SStefan Roese #define XOR_OVERRIDE_CTRL_REG(chan) (MV_XOR_REGS_BASE(XOR_UNIT(chan)) + \ 222f1df9364SStefan Roese (0x2a0 + ((XOR_CHAN(chan)) * 4))) 223f1df9364SStefan Roese 224f1df9364SStefan Roese /* XOR Engine [0..1] Address Override Control Register */ 225f1df9364SStefan Roese #define XEXAOCR_OVR_EN_OFFS(target) (3 * target) 226f1df9364SStefan Roese #define XEXAOCR_OVR_EN_MASK(target) (1 << (XEXAOCR_OVR_EN_OFFS(target))) 227f1df9364SStefan Roese #define XEXAOCR_OVR_PTR_OFFS(target) ((3 * target) + 1) 228f1df9364SStefan Roese #define XEXAOCR_OVR_PTR_MASK(target) (3 << (XEXAOCR_OVR_PTR_OFFS(target))) 229f1df9364SStefan Roese #define XEXAOCR_OVR_BAR(win_num, target) (win_num << \ 230f1df9364SStefan Roese (XEXAOCR_OVR_PTR_OFFS(target))) 231f1df9364SStefan Roese 232f1df9364SStefan Roese /* Maximum address override windows */ 233f1df9364SStefan Roese #define XOR_MAX_OVERRIDE_WIN 4 234f1df9364SStefan Roese 235f1df9364SStefan Roese #endif /* _XOR_REGS_h */ 236