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/openbmc/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_row.S105 v0.w = vdmpy(v0.h, r10.h):sat
108 v1.w = vdmpy(v1.h, r10.h):sat
111 v2.w = vdmpy(v2.h, r10.h):sat
114 v3.w = vdmpy(v3.h, r10.h):sat
117 v4.w = vdmpy(v4.h, r10.h):sat
120 v5.w = vdmpy(v5.h, r10.h):sat
123 v6.w = vdmpy(v6.h, r10.h):sat
126 v7.w = vdmpy(v7.h, r10.h):sat
129 v8.w = vdmpy(v8.h, r10.h):sat
132 v9.w = vdmpy(v9.h, r10.h):sat
[all …]
H A Dmem_noshuf.c190 int32_t w[4]; member
207 n.w[0] = ~0; in main()
211 n.w[0] = ~0; in main()
215 n.w[0] = ~0; in main()
219 n.w[0] = ~0; in main()
223 n.w[0] = ~0; in main()
224 res32 = mem_noshuf_sb_lw(&n.b[0], &n.w[0], 0x87); in main()
234 n.w[0] = ~0; in main()
238 n.w[0] = ~0; in main()
242 n.w[0] = ~0; in main()
[all …]
H A Dhvx_misc.c45 " v4.w = vadd(v12.w, v3.w)\n\t" in test_load_tmp()
47 "v4.w = vadd(v4.w, v12.w)\n\t" in test_load_tmp()
56 expect[i].w[j] = buffer0[i].w[j] + buffer1[i].w[j] + 1; in test_load_tmp()
76 " v25:24 += vmpyo(v18.w, v14.h)\n\t" in test_load_tmp2()
86 expect[0].w[i] = 0x180c0000; in test_load_tmp2()
87 expect[1].w[i] = 0x000c1818; in test_load_tmp2()
196 "q0 = vcmp.eq(v4.w, v5.w)\n\t" in test_masked_store()
205 "q0 = vcmp.eq(v4.w, v5.w)\n\t" in test_masked_store()
218 expect[i].w[j] = buffer0[i].w[j]; in test_masked_store()
222 expect[i].w[j] = buffer0[i].w[j]; in test_masked_store()
[all …]
/openbmc/qemu/include/hw/i2c/
H A Dpmbus_device.h16 PMBUS_PAGE = 0x00, /* R/W byte */
17 PMBUS_OPERATION = 0x01, /* R/W byte */
18 PMBUS_ON_OFF_CONFIG = 0x02, /* R/W byte */
20 PMBUS_PHASE = 0x04, /* R/W byte */
23 PMBUS_WRITE_PROTECT = 0x10, /* R/W byte */
35 PMBUS_VOUT_MODE = 0x20, /* R/W byte */
36 PMBUS_VOUT_COMMAND = 0x21, /* R/W word */
37 PMBUS_VOUT_TRIM = 0x22, /* R/W word */
38 PMBUS_VOUT_CAL_OFFSET = 0x23, /* R/W word */
39 PMBUS_VOUT_MAX = 0x24, /* R/W word */
[all …]
/openbmc/qemu/pc-bios/
HDopenbios-ppc ... w < 0 w $ t o \ v H o w t w h \ w P o D h R ! ...
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_debug.h27 static inline void musb_print_csr0(u16 w) in musb_print_csr0() argument
29 serial_printf("\tcsr0 0x%4.4x\n", w); in musb_print_csr0()
30 MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO); in musb_print_csr0()
31 MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND); in musb_print_csr0()
32 MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY); in musb_print_csr0()
33 MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL); in musb_print_csr0()
34 MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND); in musb_print_csr0()
35 MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND); in musb_print_csr0()
36 MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL); in musb_print_csr0()
37 MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY); in musb_print_csr0()
[all …]
/openbmc/qemu/scripts/
H A Dqom-cast-macro-clean-cocci-gen.py38 r'DECLARE_INSTANCE_CHECKER\((\w+),\W*(\w+),\W*TYPE_\w+\)',
39 r'DECLARE_OBJ_CHECKERS\((\w+),\W*\w+,\W*(\w+),\W*TYPE_\w+\)',
40 r'OBJECT_DECLARE_TYPE\((\w+),\W*\w+,\W*(\w+)\)',
41 r'OBJECT_DECLARE_SIMPLE_TYPE\((\w+),\W*(\w+)\)',
42 r'INTERFACE_CHECK\((\w+),\W*\(\w+\),\W*TYPE_(\w+)\)',
/openbmc/u-boot/drivers/net/
H A Dsmc911x.h104 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
108 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */
109 /* R/W Not Affected by SW Reset */
111 /* R/W Not Affected by SW Reset */
144 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */
145 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
146 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
147 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
148 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
149 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
[all …]
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-con-set.h15 C_O0_I2(w, r)
18 C_O1_I1(w, r)
19 C_O1_I1(w, w)
20 C_O1_I1(w, wr)
31 C_O1_I2(w, 0, w)
32 C_O1_I2(w, w, w)
33 C_O1_I2(w, w, wN)
34 C_O1_I2(w, w, wO)
35 C_O1_I2(w, w, wZ)
36 C_O1_I3(w, w, w, w)
/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-set.h16 C_O0_I2(w, r)
23 C_O1_I1(w, r)
24 C_O1_I1(w, w)
25 C_O1_I1(w, wr)
37 C_O1_I2(w, 0, w)
38 C_O1_I2(w, w, w)
39 C_O1_I2(w, w, wO)
40 C_O1_I2(w, w, wV)
41 C_O1_I2(w, w, wZ)
42 C_O1_I3(w, w, w, w)
/openbmc/qemu/host/include/i386/host/
H A Dbufferiszero.c.inc20 __m128i w = *(__m128i_u *)(buf + len - 16);
27 v |= e[-1]; w |= e[-2];
28 SSE_REASSOC_BARRIER(v, w);
29 v |= e[-3]; w |= e[-4];
30 SSE_REASSOC_BARRIER(v, w);
31 v |= e[-5]; w |= e[-6];
32 SSE_REASSOC_BARRIER(v, w);
33 v |= e[-7]; v |= w;
45 v = p[0]; w = p[1];
46 SSE_REASSOC_BARRIER(v, w);
[all …]
/openbmc/qemu/tests/tcg/mips/include/
H A Dwrappers_msa.h172 DO_MSA__WD__WS(NLOC_W, nloc.w)
177 DO_MSA__WD__WS(NLZC_W, nlzc.w)
182 DO_MSA__WD__WS(PCNT_W, pcnt.w)
197 DO_MSA__WD__WS_WT(BINSL_W, binsl.w)
198 DO_MSA__WD__WD_WT(BINSL_W__DDT, binsl.w)
199 DO_MSA__WD__WS_WD(BINSL_W__DSD, binsl.w)
210 DO_MSA__WD__WS_WT(BINSR_W, binsr.w)
211 DO_MSA__WD__WD_WT(BINSR_W__DDT, binsr.w)
212 DO_MSA__WD__WS_WD(BINSR_W__DSD, binsr.w)
235 DO_MSA__WD__WS_WT(BCLR_W, bclr.w)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h40 #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
41 #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
42 #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
43 #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
44 #define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
46 #define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
47 #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
49 #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
[all …]
/openbmc/qemu/hw/display/
H A Dexynos4210_fimd.c109 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC) argument
111 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF) argument
112 #define WIN_BPP_MODE_WITH_ALPHA(w) \ argument
113 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
117 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w)))) argument
284 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
286 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
587 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a) in fimd_get_alpha_pix() argument
593 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a) in fimd_get_alpha_pix_extlow() argument
599 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a) in fimd_get_alpha_pix_exthigh() argument
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-con-set.h20 C_O0_I2(w, r)
23 C_O1_I1(w, r)
24 C_O1_I1(w, w)
32 C_O1_I2(w, w, w)
33 C_O1_I2(w, w, wM)
34 C_O1_I2(w, w, wA)
35 C_O1_I3(w, w, w, w)
/openbmc/qemu/hw/sd/
H A Dsdmmc-internal.h23 #define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
24 #define EXT_CSD_FLUSH_CACHE 32 /* W */
25 #define EXT_CSD_CACHE_CTRL 33 /* R/W */
26 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
30 #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
41 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
42 #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
43 #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
46 #define EXT_CSD_HPI_MGMT 161 /* R/W */
47 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
[all …]
/openbmc/qemu/util/
H A Dtimed-average.c55 * @w: the window used
59 static void update_expiration(TimedAverageWindow *w, int64_t now, in update_expiration() argument
63 int64_t elapsed = (now - w->expiration) % period; in update_expiration()
67 w->expiration = now + remaining; in update_expiration()
72 * @w: the window to reset
74 static void window_reset(TimedAverageWindow *w) in window_reset() argument
76 w->min = UINT64_MAX; in window_reset()
77 w->max = 0; in window_reset()
78 w->sum = 0; in window_reset()
79 w->count = 0; in window_reset()
[all …]
H A Dqemu-coroutine-sleep.c21 void qemu_co_sleep_wake(QemuCoSleep *w) in qemu_co_sleep_wake() argument
25 co = w->to_wake; in qemu_co_sleep_wake()
26 w->to_wake = NULL; in qemu_co_sleep_wake()
39 QemuCoSleep *w = opaque; in co_sleep_cb() local
40 qemu_co_sleep_wake(w); in co_sleep_cb()
43 void coroutine_fn qemu_co_sleep(QemuCoSleep *w) in qemu_co_sleep() argument
56 w->to_wake = co; in qemu_co_sleep()
59 /* w->to_wake is cleared before resuming this coroutine. */ in qemu_co_sleep()
60 assert(w->to_wake == NULL); in qemu_co_sleep()
63 void coroutine_fn qemu_co_sleep_ns_wakeable(QemuCoSleep *w, in qemu_co_sleep_ns_wakeable() argument
[all …]
/openbmc/u-boot/arch/arc/lib/
H A Dlibgcc2.c16 DWunion w; in __ashldi3() local
19 w.s.low = 0; in __ashldi3()
20 w.s.high = (UWtype)uu.s.low << -bm; in __ashldi3()
24 w.s.low = (UWtype)uu.s.low << b; in __ashldi3()
25 w.s.high = ((UWtype)uu.s.high << b) | carries; in __ashldi3()
28 return w.ll; in __ashldi3()
39 DWunion w; in __ashrdi3() local
42 /* w.s.high = 1..1 or 0..0 */ in __ashrdi3()
43 w.s.high = uu.s.high >> (W_TYPE_SIZE - 1); in __ashrdi3()
44 w.s.low = uu.s.high >> -bm; in __ashrdi3()
[all …]
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef387 …"Vdd32=vunpackh(Vu32)", "Vdd32.w=vunpack(Vu32.h)", "Unpack halves with sign-extend", fVARRAY_…
390 ITERATOR_INSN2_PERMUTE_SLOT_DOUBLE_VEC(16,vunpackoh, "Vxx32|=vunpackoh(Vu32)", "Vxx32.w|=vunpacko(V…
402 …ITERATOR_INSN2_PERMUTE_SLOT(32, vpackeh, "Vd32=vpackeh(Vu32,Vv32)", "Vd32.h=vpacke(Vu32.w,Vv32.w)…
412 …ITERATOR_INSN2_PERMUTE_SLOT(32, vpackoh, "Vd32=vpackoh(Vu32,Vv32)", "Vd32.h=vpacko(Vu32.w,Vv32.w)…
431 …PERMUTE_SLOT(32, vpackwuh_sat, "Vd32=vpackwuh(Vu32,Vv32):sat", "Vd32.uh=vpack(Vu32.w,Vv32.w):sat",
433 VdV.uh[i] = fVSATUH(VvV.w[i]);
434 VdV.uh[i+fVELEM(32)] = fVSATUH(VuV.w[i]))
436 …N2_PERMUTE_SLOT(32, vpackwh_sat, "Vd32=vpackwh(Vu32,Vv32):sat", "Vd32.h=vpack(Vu32.w,Vv32.w):sat",
438 VdV.h[i] = fVSATH(VvV.w[i]);
439 VdV.h[i+fVELEM(32)] = fVSATH(VuV.w[i]))
[all …]
/openbmc/openbmc/meta-yadro/meta-nicole/recipes-phosphor/chassis/avsbus-control/
H A Davsbus-control.sh8 i2cset -y "${BUS}" 0x44 0x24 0x044C w # VOUT_MAX 1100mV
9 i2cset -y "${BUS}" 0x44 0x40 0x0456 w # VOUT_OV_FAULT_LIMIT 1110mV
10 i2cset -y "${BUS}" 0x44 0x25 0x0438 w # VOUT_MARGING_HIGH 1080mV
11 i2cset -y "${BUS}" 0x44 0x26 0x03D4 w # VOUT_MARGING_LOW 980mV
12 i2cset -y "${BUS}" 0x44 0x44 0x024E w # VOUT_UV_FAULT_LIMIT 590mV
13 i2cset -y "${BUS}" 0x44 0x2B 0x0258 w # VOUT_MIN 600mV
16 i2cset -y "${BUS}" 0x44 0x24 0x044C w # VOUT_MAX 1100mV
17 i2cset -y "${BUS}" 0x44 0x40 0x0456 w # VOUT_OV_FAULT_LIMIT 1110mV
18 i2cset -y "${BUS}" 0x44 0x25 0x041A w # VOUT_MARGING_HIGH 1050mV
19 i2cset -y "${BUS}" 0x44 0x26 0x03B6 w # VOUT_MARGING_LOW 950mV
[all …]
/openbmc/qemu/hw/watchdog/
H A Dspapr_watchdog.c74 static target_ulong watchdog_stop(unsigned watchdogNumber, SpaprWatchdog *w) in watchdog_stop() argument
78 if (timer_pending(&w->timer)) { in watchdog_stop()
79 timer_del(&w->timer); in watchdog_stop()
105 SpaprWatchdog *w = pw; in watchdog_expired() local
108 unsigned num = w - spapr->wds; in watchdog_expired()
111 trace_spapr_watchdog_expired(num, w->action); in watchdog_expired()
112 switch (w->action) { in watchdog_expired()
125 if (!w->leave_others) { in watchdog_expired()
140 SpaprWatchdog *w; in h_watchdog() local
155 w = &spapr->wds[watchdogNumber - 1]; in h_watchdog()
[all …]
/openbmc/qemu/tests/tcg/s390x/
H A Dvxeh2_vcvt.c58 S390Vector vs_i32 = { .w[0] = 1, .w[1] = 64, .w[2] = 1024, .w[3] = -10 }; in main()
59 S390Vector vs_u32 = { .w[0] = 2, .w[1] = 32, .w[2] = 4096, .w[3] = 8888 }; in main()
77 if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 != vd.w[3]) { in main()
83 if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 != vd.w[3]) { in main()
/openbmc/qemu/ui/
H A Dvnc-enc-tight.c76 int x, int y, int w, int h);
115 int x, int y, int w, int h, VncPalette *palette);
117 static bool tight_can_send_png_rect(VncState *vs, VncTight *tight, int w, int h) in tight_can_send_png_rect() argument
138 tight_detect_smooth_image24(VncState *vs, VncTight *tight, int w, int h) in tight_detect_smooth_image24() argument
157 for (y = 0, x = 0; y < h && x < w;) { in tight_detect_smooth_image24()
158 for (d = 0; d < h - y && d < w - x - VNC_TIGHT_DETECT_SUBROW_WIDTH; in tight_detect_smooth_image24()
161 left[c] = buf[((y+d)*w+x+d)*4+off+c] & 0xFF; in tight_detect_smooth_image24()
165 pix = buf[((y+d)*w+x+d+dx)*4+off+c] & 0xFF; in tight_detect_smooth_image24()
172 if (w > h) { in tight_detect_smooth_image24()
177 y += w; in tight_detect_smooth_image24()
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-mmx.py23 'PSHUF[LH]W': 0xff,
32 def reg_w(w): argument
33 if w == 8:
35 elif w == 16:
37 elif w == 32:
39 elif w == 64:
41 raise Exception("bad reg_w %d" % w)
43 def mem_w(w): argument
44 if w == 8:
46 elif w == 16:
[all …]

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