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/openbmc/linux/tools/perf/pmu-events/arch/nds32/n13/
H A Datcpmu.json6 "BriefDescription": "V3 Conditional branch"
12 "BriefDescription": "V3 Taken Conditional branch"
18 "BriefDescription": "V3 Prefetch Instruction"
24 "BriefDescription": "V3 RET Inst"
30 "BriefDescription": "V3 JR(non-RET) instructions"
36 "BriefDescription": "V3 JAL/JRAL instructions"
42 "BriefDescription": "V3 NOP instructions"
48 "BriefDescription": "V3 SCW instructions"
54 "BriefDescription": "V3 ISB/DSB instructions"
60 "BriefDescription": "V3 CCTL instructions"
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpci-v3-semi.c3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
249 * The V3 PCI interface chip in Integrator provides several windows from
262 * There are three V3 windows, each described by a pair of V3 registers.
289 * The V3 chip translates an address by checking its range within
293 * LB_BASE1/LB_MAP1, the V3 will use the translation from
313 struct v3_pci *v3 = bus->sysdata; in v3_map_bus() local
365 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
367 v3->base + V3_LB_BASE0); in v3_map_bus()
373 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
375 v3->base + V3_LB_BASE1); in v3_map_bus()
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/x86/
H A Dtune-x86-64-v3.inc1 # Settings for the GCC(1) cpu-type "x86-64-v3":
9 DEFAULTTUNE ?= "x86-64-v3"
15 TUNEVALID[x86-64-v3] = "Enable x86-64-v3 specific processor optimizations"
16 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'x86-64-v3', ' -march=x86-64-v3', '', d)}"
19 AVAILTUNES += "x86-64-v3"
20 TUNE_FEATURES:tune-x86-64-v3 = "${TUNE_FEATURES:tune-x86-64} x86-64-v3"
21 BASE_LIB:tune-x86-64-v3 = "lib64"
22 TUNE_PKGARCH:tune-x86-64-v3 = "x86-64-v3"
23 PACKAGE_EXTRA_ARCHS:tune-x86-64-v3 = "${PACKAGE_EXTRA_ARCHS:tune-corei7-64} x86-64-v3"
24 QEMU_EXTRAOPTIONS_x86-64-v3 = " -cpu Skylake-Client,check=false"
[all …]
/openbmc/linux/include/uapi/linux/
H A Dnfs.h47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
54 NFSERR_EXIST = 17, /* v2 v3 v4 */
55 NFSERR_XDEV = 18, /* v3 v4 */
56 NFSERR_NODEV = 19, /* v2 v3 v4 */
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h103 .ifc \vxr,%v3
200 * @v3: Third vector register designated operand
203 .macro RXB rxb v1 v2=0 v3=0 v4=0
211 .if \v3 & 0x10
224 * @v3: Third vector register designated operand (for RXB)
227 .macro MRXB m v1 v2=0 v3=0 v4=0
229 RXB rxb, \v1, \v2, \v3, \v4
239 * @v3: Third vector register designated operand (for RXB)
242 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
243 MRXB \m, \v1, \v2, \v3, \v4
[all …]
/openbmc/qemu/tests/tcg/s390x/
H A Dvxeh2_vs.c12 static inline void vsl(S390Vector *v1, S390Vector *v2, S390Vector *v3) in vsl() argument
14 asm volatile("vsl %[v1], %[v2], %[v3]\n" in vsl()
17 , [v3] "v" (v3->v)); in vsl()
20 static inline void vsra(S390Vector *v1, S390Vector *v2, S390Vector *v3) in vsra() argument
22 asm volatile("vsra %[v1], %[v2], %[v3]\n" in vsra()
25 , [v3] "v" (v3->v)); in vsra()
28 static inline void vsrl(S390Vector *v1, S390Vector *v2, S390Vector *v3) in vsrl() argument
30 asm volatile("vsrl %[v1], %[v2], %[v3]\n" in vsrl()
33 , [v3] "v" (v3->v)); in vsrl()
37 S390Vector *v3, const uint8_t I) in vsld() argument
[all …]
H A Dvrep.c28 vrep(S390Vector *v1, const S390Vector *v3, const uint16_t i2, const uint8_t m4) in vrep() argument
32 asm("vrep %[v1],%[v3],%[i2],%[m4]\n" in vrep()
35 : [v3] "v" (v3->v) in vrep()
44 S390Vector v3 = {.d[0] = 1, .d[1] = 2}; in main() local
55 assert(vrep(&v1, &v3, 7, 0) == -1); in main()
59 assert(vrep(&v1, &v3, 7, 1) == -1); in main()
63 assert(vrep(&v1, &v3, 1, 2) == -1); in main()
67 assert(vrep(&v1, &v3, 1, 3) == -1); in main()
71 assert(vrep(&v1, &v3, 0x10, 0) == SIGILL); in main()
72 assert(vrep(&v1, &v3, 0x101, 0) == SIGILL); in main()
[all …]
H A Dvxeh2_vstrs.c13 vstrs(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, in vstrs() argument
18 asm("vstrs %[v1],%[v2],%[v3],%[v4],%[m5],%[m6]\n" in vstrs()
23 , [v3] "v" (v3->v) in vstrs()
36 S390Vector v3 = {.d[0] = 0x205e410000000000ULL, .d[1] = 0}; in test_ignored_match() local
39 assert(vstrs(&v1, &v2, &v3, &v4, 0, 2) == 1); in test_ignored_match()
48 S390Vector v3 = {.d[0] = 0, .d[1] = 0}; in test_empty_needle() local
51 assert(vstrs(&v1, &v2, &v3, &v4, 0, 0) == 2); in test_empty_needle()
60 S390Vector v3 = {.d[0] = 0, .d[1] = 0}; in test_max_length() local
63 assert(vstrs(&v1, &v2, &v3, &v4, 0, 0) == 3); in test_max_length()
72 S390Vector v3 = {.d[0] = 0xfffffffeffffffffULL, in test_no_match() local
[all …]
/openbmc/linux/lib/
H A Dsiphash.c20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
26 u64 v3 = SIPHASH_CONST_3; \
28 v3 ^= key->key[1]; \
34 v3 ^= b; \
43 return (v0 ^ v1) ^ (v2 ^ v3);
54 v3 ^= m; in __siphash_aligned()
87 v3 ^= m; in __siphash_unaligned()
119 v3 ^= first; in siphash_1u64()
136 v3 ^= first; in siphash_2u64()
140 v3 ^= second; in siphash_2u64()
[all …]
H A Dxxhash.c112 uint32_t v3 = seed + 0; in xxh32() local
120 v3 = xxh32_round(v3, get_unaligned_le32(p)); in xxh32()
127 xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18); in xxh32()
182 uint64_t v3 = seed + 0; in xxh64() local
190 v3 = xxh64_round(v3, get_unaligned_le64(p)); in xxh64()
197 xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); in xxh64()
200 h64 = xxh64_merge_round(h64, v3); in xxh64()
250 state.v3 = seed + 0; in xxh32_reset()
264 state.v3 = seed + 0; in xxh64_reset()
297 state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32)); in xxh32_update()
[all …]
/openbmc/linux/arch/arm64/lib/
H A Dxor-neon.c19 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_2() local
27 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_2()
33 vst1q_u64(dp1 + 6, v3); in xor_arm64_neon_2()
48 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_3() local
56 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_3()
62 v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); in xor_arm64_neon_3()
68 vst1q_u64(dp1 + 6, v3); in xor_arm64_neon_3()
86 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_4() local
94 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_4()
100 v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); in xor_arm64_neon_4()
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsm4-ce-core.S64 sm4ekey v3.4s, v2.4s, v27.4s;
65 sm4ekey v4.4s, v3.4s, v28.4s;
73 st1 {v0.16b-v3.16b}, [x1], #64;
80 tbl v20.16b, {v3.16b}, v24.16b
121 ld1 {v0.16b-v3.16b}, [x2], #64;
124 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7);
126 st1 {v0.16b-v3.16b}, [x1], #64;
139 ld1 {v0.16b-v3.16b}, [x2], #64;
140 SM4_CRYPT_BLK4(v0, v1, v2, v3);
141 st1 {v0.16b-v3.16b}, [x1], #64;
[all …]
H A Daes-modes.S26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
92 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
96 st1 {v0.16b-v3.16b}, [x0], #64
143 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
150 eor v3.16b, v3.16b, v2.16b
[all …]
H A Dsm3-ce-core.S89 0: ld1 {v0.16b-v3.16b}, [x1], #64
98 CPU_LE( rev32 v3.16b, v3.16b )
102 qround a, v0, v1, v2, v3, v4
103 qround a, v1, v2, v3, v4, v0
104 qround a, v2, v3, v4, v0, v1
105 qround a, v3, v4, v0, v1, v2
109 qround b, v4, v0, v1, v2, v3
110 qround b, v0, v1, v2, v3, v4
111 qround b, v1, v2, v3, v4, v0
112 qround b, v2, v3, v4, v0, v1
[all …]
H A Dchacha-neon-core.S32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
48 rev32 v3.8h, v3.8h
51 add v2.4s, v2.4s, v3.4s
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
62 add v2.4s, v2.4s, v3.4s
72 ext v3.16b, v3.16b, v3.16b, #12
76 eor v3.16b, v3.16b, v0.16b
77 rev32 v3.8h, v3.8h
[all …]
/openbmc/linux/arch/loongarch/lib/
H A Dxor_template.c38 const unsigned long * __restrict v3)
46 LD_AND_XOR_LINE(v3)
48 : : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3) : "memory"
53 v3 += LINE_WIDTH / sizeof(unsigned long);
60 const unsigned long * __restrict v3,
69 LD_AND_XOR_LINE(v3)
72 : : [v1] "r"(v1), [v2] "r"(v2), [v3] "r"(v3), [v4] "r"(v4)
78 v3 += LINE_WIDTH / sizeof(unsigned long);
86 const unsigned long * __restrict v3,
96 LD_AND_XOR_LINE(v3)
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dvec_int_helper.c101 void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
108 const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
117 void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
124 const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
171 void HELPER(gvec_vgfm8)(void *v1, const void *v2, const void *v3, uint32_t d) in HELPER()
174 const uint64_t *q2 = v2, *q3 = v3; in HELPER()
180 void HELPER(gvec_vgfma8)(void *v1, const void *v2, const void *v3, in HELPER()
184 const uint64_t *q2 = v2, *q3 = v3, *q4 = v4; in HELPER()
195 void HELPER(gvec_vgfm16)(void *v1, const void *v2, const void *v3, uint32_t d) in HELPER()
198 const uint64_t *q2 = v2, *q3 = v3; in HELPER()
[all …]
H A Dvec_string_helper.c78 static int vfae(void *v1, const void *v2, const void *v3, bool in, in vfae() argument
90 b0 = s390_vec_read_element64(v3, 0); in vfae()
91 b1 = s390_vec_read_element64(v3, 1); in vfae()
137 void HELPER(gvec_vfae##BITS)(void *v1, const void *v2, const void *v3, \
144 vfae(v1, v2, v3, in, rt, zs, MO_##BITS); \
151 void HELPER(gvec_vfae_cc##BITS)(void *v1, const void *v2, const void *v3, \
158 env->cc_op = vfae(v1, v2, v3, in, rt, zs, MO_##BITS); \
164 static int vfee(void *v1, const void *v2, const void *v3, bool zs, uint8_t es) in vfee() argument
173 b0 = s390_vec_read_element64(v3, 0); in vfee()
174 b1 = s390_vec_read_element64(v3, 1); in vfee()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
76 FN(reg, f3), v3)
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
82 FN(reg, f3), v3,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
90 FN(reg, f3), v3,\
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
99 FN(reg, f3), v3,\
104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
109 FN(reg, f3), v3,\
[all …]
/openbmc/linux/arch/powerpc/lib/
H A Dxor_vmx.c78 DEFINE(v3); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
86 XOR(v1, v3); in __xor_altivec_3()
91 v3 += 4; in __xor_altivec_3()
103 DEFINE(v3); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
113 XOR(v3, v4); in __xor_altivec_4()
114 XOR(v1, v3); in __xor_altivec_4()
119 v3 += 4; in __xor_altivec_4()
133 DEFINE(v3); in __xor_altivec_5()
[all …]
/openbmc/linux/drivers/char/mwave/
H A Dmwavedd.h89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument
96 printk(s,v1,v2,v3,v4); \
99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
[all …]
/openbmc/qemu/docs/system/
H A Dcpu-models-x86-abi.csv1 Model,baseline,v2,v3,v4
5 Broadwell-v3,✅,✅,✅,
9 Cascadelake-Server-v3,✅,✅,✅,✅
17 Denverton-v3,✅,✅,,
25 EPYC-Rome-v3,✅,✅,✅,
29 EPYC-v3,✅,✅,✅,
34 Haswell-v3,✅,✅,✅,
38 Icelake-Server-v3,✅,✅,✅,✅
59 Skylake-Client-v3,✅,✅,✅,
63 Skylake-Server-v3,✅,✅,✅,✅
[all …]
/openbmc/linux/include/pcmcia/
H A Ddevice_id.h34 #define PCMCIA_DEVICE_PROD_ID3(v3, vh3) { \ argument
36 .prod_id = { NULL, NULL, (v3), NULL }, \
45 #define PCMCIA_DEVICE_PROD_ID13(v1, v3, vh1, vh3) { \ argument
48 .prod_id = { (v1), NULL, (v3), NULL }, \
57 #define PCMCIA_DEVICE_PROD_ID123(v1, v2, v3, vh1, vh2, vh3) { \ argument
61 .prod_id = { (v1), (v2), (v3), NULL },\
71 #define PCMCIA_DEVICE_PROD_ID134(v1, v3, v4, vh1, vh3, vh4) { \ argument
75 .prod_id = { (v1), NULL, (v3), (v4) }, \
78 #define PCMCIA_DEVICE_PROD_ID1234(v1, v2, v3, v4, vh1, vh2, vh3, vh4) { \ argument
83 .prod_id = { (v1), (v2), (v3), (v4) }, \
[all …]
/openbmc/qemu/include/qemu/
H A Dxxhash.h56 uint32_t v3 = QEMU_XXHASH_SEED + 0; in qemu_xxhash8() local
74 v3 += c * PRIME32_2; in qemu_xxhash8()
75 v3 = rol32(v3, 13); in qemu_xxhash8()
76 v3 *= PRIME32_1; in qemu_xxhash8()
82 h32 = rol32(v1, 1) + rol32(v2, 7) + rol32(v3, 12) + rol32(v4, 18); in qemu_xxhash8()
143 * v3 = seed + 0;
148 * v3 = XXH64_round(v3, get64bits(input + i + 16));
151 * h64 = XXH64_mergerounds(v1, v2, v3, v4);
192 uint64_t v3, uint64_t v4) in XXH64_mergerounds() argument
196 h64 = rol64(v1, 1) + rol64(v2, 7) + rol64(v3, 12) + rol64(v4, 18); in XXH64_mergerounds()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dltc2990.txt15 2: V1-V2, V3, V4
16 3: TR1, V3, V4
17 4: TR1, V3-V4
19 6: V1-V2, V3-V4
20 7: V1, V2, V3, V4
27 2: TR2, V3 or V3-V4 only per mode
35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */

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