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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event …
12 …"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event i…
15 …"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event …
18 …"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event i…
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side",
30 "BriefDescription": "Duration of a translation table walk requested by the instruction side"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 "PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
12 "BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
15 "PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
18 "BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the Instruction Side",
30 "BriefDescription": "Duration of a translation table walk requested by the Instruction Side"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dtlb.json4 … not count if the translation table walk results in a fault (such as a translation or access fault…
8 …translation table walk. This event will not count if the translation table walk results in a fault…
28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr…
32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2…
36 …translation table walk. This event will not count if the translation table walk results in a fault…
40 …translation table walk. This event will not count if the table walk results in a fault (such as a …
H A Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dtlb.json4 … not count if the translation table walk results in a fault (such as a translation or access fault…
8 …translation table walk. This event will not count if the translation table walk results in a fault…
28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr…
32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2…
36 …translation table walk. This event will not count if the translation table walk results in a fault…
40 …translation table walk. This event will not count if the table walk results in a fault (such as a …
H A Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
/openbmc/linux/arch/arm/mm/
H A Dfsr-3level.c7 { do_bad, SIGBUS, 0, "reserved translation fault" },
8 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
9 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
10 { do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
23 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
24 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
25 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
26 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
31 { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
32 { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
[all …]
H A Dfsr-2level.c12 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
14 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
19 { do_bad, SIGBUS, 0, "external abort on translation" },
21 { do_bad, SIGBUS, 0, "external abort on translation" },
52 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
54 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
59 { do_bad, SIGBUS, 0, "external abort on translation" },
61 { do_bad, SIGBUS, 0, "external abort on translation" },
/openbmc/qemu/include/hw/arm/
H A Dsmmu-common.h30 /* VMSAv8-64 Translation constants and functions */
48 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
49 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
66 bool is_ipa_descriptor; /* src for fault in nested translation. */
70 bool disabled; /* is the translation table disabled? */
87 uint8_t sl0; /* Start level of translation (S2SL0) */
93 uint64_t vttb; /* Address of translation table base (S2TTB) */
103 SMMUStage stage; /* translation stage */
105 bool bypassed; /* translation is bypassed */
106 bool aborted; /* translation is aborted */
[all …]
/openbmc/linux/Documentation/translations/
H A Dindex.rst27 Translation's purpose is to ease reading and understanding in languages other
37 no guarantee that a translation is up to date. If what you read in a
38 translation does not sound right compared to what you read in the code, please
39 inform the translation maintainer and - if you can - check also the English
42 A translation is not a fork of the official documentation, therefore
47 accept only contributions that are merely translation related (e.g. new
52 grammar and culture, so the translation of an English statement may need to be
58 comfortable writing in English, you can ask the translation's maintainers
/openbmc/linux/drivers/mtd/
H A DKconfig30 comment "User Modules And Translation Layers"
76 tristate "FTL (Flash Translation Layer) support"
80 This provides support for the original Flash Translation Layer which
93 tristate "NFTL (NAND Flash Translation Layer) support"
97 This provides support for the NAND Flash Translation Layer which is
113 Support for writing to the NAND Flash Translation Layer, as used
117 tristate "INFTL (Inverse NAND Flash Translation Layer) support"
121 This provides support for the Inverse NAND Flash Translation
135 tristate "Resident Flash Disk (Flash Translation Layer) support"
139 This provides support for the flash translation layer known
[all …]
/openbmc/qemu/hw/block/
H A Dhd-geometry.c121 int cylinders, heads, secs, translation; in hd_geometry_guess() local
130 translation = BIOS_ATA_TRANSLATION_NONE; in hd_geometry_guess()
134 translation = hd_bios_chs_auto_trans(*pcyls, *pheads, *psecs); in hd_geometry_guess()
137 translation was active, so a standard physical disk in hd_geometry_guess()
140 translation = *pcyls * *pheads <= 131072 in hd_geometry_guess()
148 /* disable any translation to be in sync with in hd_geometry_guess()
150 translation = BIOS_ATA_TRANSLATION_NONE; in hd_geometry_guess()
154 *ptrans = translation; in hd_geometry_guess()
156 /* Defer to the translation specified by the user. */ in hd_geometry_guess()
157 translation = *ptrans; in hd_geometry_guess()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dvirtual-memory.json20 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
28 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
36 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
44 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
74 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
82 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
90 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
98 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
151 …ription": "Counts the number of times there was an ITLB miss and a new translation was filled into…
154 …he machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB)…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dvirtual-memory.json20 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
28 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
36 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
44 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
74 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
82 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
90 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
98 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
151 …ription": "Counts the number of times there was an ITLB miss and a new translation was filled into…
154 …he machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB)…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dpipeline.json35 …oup (Distant) due to a marked data side request. When using Radix Page Translation, this count exc…
40 … L2 without conflict due to a data side request. When using Radix Page Translation, this count exc…
80 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
95 … L2 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
115 …n Mepf state. due to a marked data side request. When using Radix Page Translation, this count exc…
160 …e or distant) due to a marked data side request. When using Radix Page Translation, this count exc…
175 …th dispatch conflict due to a data side request. When using Radix Page Translation, this count exc…
180 …hout conflict due to a marked data side request. When using Radix Page Translation, this count exc…
185 … cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
225 …hout conflict due to a marked data side request. When using Radix Page Translation, this count exc…
[all …]
H A Dpmc.json20 … as this chip due to a marked data side request. When using Radix Page Translation, this count exc…
30 … the local core's L3 due to a data side request. When using Radix Page Translation, this count exc…
40 …al core's L2 due to a marked data side request.. When using Radix Page Translation, this count exc…
90 …al remote or distant due to a data side request. When using Radix Page Translation, this count exc…
95 …atch conflict due to a marked data side request. When using Radix Page Translation, this count exc…
100 …cal core's L3 due to a marked data side request. When using Radix Page Translation, this count exc…
110 …ocal chip's L4 cache due to a data side request. When using Radix Page Translation, this count exc…
H A Dmarked.json20 … L3 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
45 …ore's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation"
50 …ore's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation"
60 …p's L4 cache due to a marked data side request.. When using Radix Page Translation, this count exc…
70 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
95 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
100 … L3 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
210 …chip's Memory due to a marked data side request. When using Radix Page Translation, this count exc…
220 …cal core's L3 due to a marked data side request. When using Radix Page Translation, this count exc…
225 …k cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dextended.json84 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
112 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
119 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
126 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
133 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
140 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dextended.json77 …"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translatio…
84 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
91 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
105 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
/openbmc/qemu/docs/system/arm/
H A Demulation.rst25 - FEAT_BBM at level 2 (Translation table break-before-make levels)
57 - FEAT_ETS2 (Enhanced Translation Synchronization)
72 - FEAT_GTG (Guest translation granule size)
77 - FEAT_HPDS2 (Translation table page-based hardware attributes)
143 - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
144 - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
145 - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
149 - FEAT_TTCNP (Translation table Common not private translations)
150 - FEAT_TTL (Translation Table Level)
151 - FEAT_TTST (Small translation tables)
[all …]
/openbmc/u-boot/include/dm/
H A Dfdtaddr.h124 * dm_set_translation_offset() - Set translation offset
125 * @offs: Translation offset
127 * Some platforms need a special address translation. Those
128 * platforms (e.g. mvebu in SPL) can configure a translation
135 * dm_get_translation_offset() - Get translation offset
137 * This function returns the translation offset that can
140 * @return translation offset for the device address (0 as default).
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dcache.json156 …che. If a single translation table walk needs to make multiple accesses to the IPA cache, each acc…
159 …che. If a single translation table walk needs to make multiple accesses to the IPA cache, each acc…
162 …ingle translation table walk needs to make multiple accesses to the IPA cache, each access that ca…
165 …ingle translation table walk needs to make multiple accesses to the IPA cache, each access that ca…
/openbmc/qemu/docs/devel/
H A Dtcg.rst13 QEMU's dynamic translation backend is called TCG, for "Tiny Code
24 translation phase considers that some state information of the virtual
25 CPU cannot change in it. The state is recorded in the Translation
71 The translation code usually implements branching by performing the
163 memory until the end of the translation block. This is done for internal
165 very often throughout the execution of a translation block---this includes
174 virtual to physical address translation is done at every memory
177 QEMU uses an address translation cache (TLB) to speed up the translation.
187 areas. Access is faster for RAM and ROM because the translation cache also
191 translation blocks.
/openbmc/openbmc-test-automation/openpower/ras/
H A Dtest_host_ras.robot166 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
177 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
187 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
201 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
212 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
222 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
248 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
261 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
271 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
285 ${translated_fir}= Fetch FIR Address Translation Value ${value[0]} EX
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
77 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
84 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
91 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…

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