Home
last modified time | relevance | path

Searched full:trcpdcr (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-etm.yaml98 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
101 watchdog counter is stopped when TRCPDCR.PU is set.
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-core.c501 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_enable_hw() local
507 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); in etm4_enable_hw()
880 control = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_disable_hw()
882 etm4x_relaxed_write32(csa, control, TRCPDCR); in etm4_disable_hw()
1763 state->trcpdcr = etm4x_read32(csa, TRCPDCR); in __etm4_cpu_save()
1782 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), in __etm4_cpu_save()
1783 TRCPDCR); in __etm4_cpu_save()
1888 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); in __etm4_cpu_restore()
H A Dcoresight-etm4x.h84 #define TRCPDCR 0x310 macro
446 CASE_##op((val), TRCPDCR) \
917 u32 trcpdcr; member
H A Dcoresight-etm4x-sysfs.c2549 coresight_etm4x_reg(trcpdcr, TRCPDCR),
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etm4x339 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr