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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/sqlite-orm/sqlite-orm/
H A D0001-fix-cstdint-error-with-gcc-15.0.1.patch8 …TOPDIR/tmp/work/core2-64-oe-linux/sqlite-orm/1.5/git/examples/synchronous.cpp:7:5: error: 'uint16_…
11 …TOPDIR/tmp/work/core2-64-oe-linux/sqlite-orm/1.5/git/examples/synchronous.cpp:3:1: note: 'uint16_t…
17 since it was a commit made in v1.9, only synchronous.cpp was modified as other files do not exist i…
23 examples/synchronous.cpp | 11 ++++++-----
26 diff --git a/examples/synchronous.cpp b/examples/synchronous.cpp
28 --- a/examples/synchronous.cpp
29 +++ b/examples/synchronous.cpp
/openbmc/u-boot/arch/arm/lib/
H A Dinterrupts_64.c45 * do_bad_sync handles the impossible case in the Synchronous Abort vector.
50 printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); in do_bad_sync()
89 * do_sync handles the Synchronous Abort exception.
94 printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); in do_sync()
/openbmc/qemu/include/hw/ssi/
H A Dpl022.h2 * ARM PrimeCell PL022 Synchronous Serial Port
13 * This is a model of the Arm PrimeCell PL022 synchronous serial port.
/openbmc/u-boot/doc/
H A DREADME.AX2529 - Synchronous AHB (32-bit/64-bit data-width), or
30 - Synchronous AXI4 (64-bit data-width)
H A DREADME.N121344 - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
45 - Synchronous High speed memory port.
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9261.h37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
38 #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
39 #define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */
H A Dat91sam9rl.h34 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35 #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
H A Dat91sam9263.h35 #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
36 #define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */
H A Dat91sam9g45.h33 #define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
34 #define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */
/openbmc/qemu/linux-headers/asm-generic/
H A Dmman-common.h30 #define MAP_SYNC 0x080000 /* perform synchronous page faults for the mapping */
43 #define MS_SYNC 4 /* synchronous memory sync */
80 #define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
/openbmc/qemu/include/block/
H A Daio-wait.h34 * An object that facilitates synchronous waiting on a condition. A single
67 * Wait while a condition is true. Use this to implement synchronous
112 * synchronous operations performed in an IOThread, the main thread lets the
/openbmc/u-boot/arch/nds32/include/asm/arch-ag101/
H A Dag101.h72 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */
81 /* Synchronous Serial Port Controller (SSP) 01 */
/openbmc/qemu/linux-user/aarch64/
H A Dtarget_signal.h9 #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dexceptions.S16 * - synchronous: traps, data aborts, undefined instructions, ...
38 .align 7 /* Current EL Synchronous Thread */
138 .align 7 /* Current EL (SP_ELx) Synchronous Handler */
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DDimm.interface.yaml23 Additional detail on Memory, such as Synchronous, Static column, etc.
165 Synchronous Dynamic Random Access Memory.
168 Double Data Rate Synchronous Graphics Random-Access Memory.
/openbmc/docs/designs/
H A Dphosphor-hwmon-io-uring.md15 longer than desired. These IO operations are currently synchronous, and
39 accuracy as the current, synchronous reads in each of the daemons. Potential
53 synchronous method. In addition, the performance improvement from using the new
136 sensor reads in the synchronous implementation. The kernel will process these
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/
H A Dpython3-websocket-client_1.7.0.bb5 are the synchronous functions."
/openbmc/qemu/docs/system/arm/
H A Dcollie.rst16 * Synchronous Serial Ports (SSP)
H A Dhighbank.rst17 - PL022 synchronous serial port controller
/openbmc/u-boot/include/configs/
H A Dx600.h216 * Synchronous/Asynchronous operation of DDR
218 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
219 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h63 #define SSCR0_TI (0x1 << 4) /* TI's Synchronous
67 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
/openbmc/qemu/tests/tcg/aarch64/system/
H A Dmte.S51 * insns., like stg & friends, and to enable synchronous exception in
56 * TCF[41:40] = 0b01 => Tag Check Faults cause a synchronous exception
/openbmc/qemu/linux-headers/asm-mips/
H A Dmman.h58 #define MS_SYNC 0x0004 /* synchronous memory sync */
106 #define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
/openbmc/openpower-proc-control/procedures/p9/
H A Dset_sync_fsi_clock_mode.cpp31 * @Brief Sets the P9 FSI clock to synchronous mode.
/openbmc/u-boot/board/xes/common/
H A Dfsl_8xxx_clk.c33 * Return DDR input clock - synchronous with SYSCLK or 66 MHz

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