1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2995b72ddSStefan Roese /* 3e36591c3SPatrice Chotard * Copyright (C) 2009, STMicroelectronics - All Rights Reserved 4e36591c3SPatrice Chotard * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics. 5995b72ddSStefan Roese * 62fbdbda1SStefan Roese * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 7995b72ddSStefan Roese */ 8995b72ddSStefan Roese 9995b72ddSStefan Roese #ifndef __CONFIG_H 10995b72ddSStefan Roese #define __CONFIG_H 11995b72ddSStefan Roese 12995b72ddSStefan Roese /* 13995b72ddSStefan Roese * High Level Configuration Options 14995b72ddSStefan Roese * (easy to change) 15995b72ddSStefan Roese */ 16995b72ddSStefan Roese #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 17995b72ddSStefan Roese #define CONFIG_X600 /* on X600 board */ 18995b72ddSStefan Roese 19995b72ddSStefan Roese #include <asm/arch/hardware.h> 20995b72ddSStefan Roese 21995b72ddSStefan Roese /* Timer, HZ specific defines */ 22995b72ddSStefan Roese #define CONFIG_SYS_HZ_CLOCK 8300000 23995b72ddSStefan Roese 24995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BASE 0xf8000000 25995b72ddSStefan Roese /* Reserve 8KiB for SPL */ 26995b72ddSStefan Roese #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 27995b72ddSStefan Roese #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 28995b72ddSStefan Roese #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 29995b72ddSStefan Roese CONFIG_SYS_SPL_LEN) 30285e266bSStefan Roese #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 31995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 32995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_LEN 0x60000 33995b72ddSStefan Roese 34995b72ddSStefan Roese /* Serial Configuration (PL011) */ 35995b72ddSStefan Roese #define CONFIG_SYS_SERIAL0 0xD0000000 36995b72ddSStefan Roese #define CONFIG_SYS_SERIAL1 0xD0080000 37995b72ddSStefan Roese #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 38995b72ddSStefan Roese (void *)CONFIG_SYS_SERIAL1 } 39995b72ddSStefan Roese #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 40995b72ddSStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 41995b72ddSStefan Roese 57600, 115200 } 42995b72ddSStefan Roese #define CONFIG_SYS_LOADS_BAUD_CHANGE 43995b72ddSStefan Roese 44995b72ddSStefan Roese /* NOR FLASH config options */ 45995b72ddSStefan Roese #define CONFIG_ST_SMI 46995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS 1 47995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 48995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 49995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_SECT 128 50995b72ddSStefan Roese #define CONFIG_SYS_FLASH_EMPTY_INFO 51995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 52995b72ddSStefan Roese #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 53995b72ddSStefan Roese 54995b72ddSStefan Roese /* NAND FLASH config options */ 55995b72ddSStefan Roese #define CONFIG_NAND_FSMC 56995b72ddSStefan Roese #define CONFIG_SYS_NAND_SELF_INIT 57995b72ddSStefan Roese #define CONFIG_SYS_MAX_NAND_DEVICE 1 58995b72ddSStefan Roese #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 59995b72ddSStefan Roese #define CONFIG_MTD_ECC_SOFT 60995b72ddSStefan Roese #define CONFIG_SYS_FSMC_NAND_8BIT 61995b72ddSStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION 620ddc5a2dSStefan Roese #define CONFIG_NAND_ECC_BCH 63995b72ddSStefan Roese 64995b72ddSStefan Roese /* UBI/UBI config options */ 65995b72ddSStefan Roese 66995b72ddSStefan Roese /* Ethernet config options */ 67995b72ddSStefan Roese #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 68995b72ddSStefan Roese 69995b72ddSStefan Roese #define CONFIG_SPEAR_GPIO 70995b72ddSStefan Roese 71995b72ddSStefan Roese /* I2C config options */ 72678398b1SStefan Roese #define CONFIG_SYS_I2C 73f93f589cSAlexey Brodkin #define CONFIG_SYS_I2C_BASE 0xD0200000 74995b72ddSStefan Roese #define CONFIG_SYS_I2C_SPEED 400000 75995b72ddSStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x02 76995b72ddSStefan Roese #define CONFIG_I2C_CHIPADDRESS 0x50 77995b72ddSStefan Roese 78995b72ddSStefan Roese #define CONFIG_SYS_I2C_RTC_ADDR 0x68 79995b72ddSStefan Roese 80995b72ddSStefan Roese /* FPGA config options */ 81995b72ddSStefan Roese #define CONFIG_FPGA_COUNT 1 82995b72ddSStefan Roese 83285e266bSStefan Roese /* USB EHCI options */ 84285e266bSStefan Roese #define CONFIG_USB_EHCI_SPEAR 85285e266bSStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 86285e266bSStefan Roese 87995b72ddSStefan Roese /* 88995b72ddSStefan Roese * U-Boot Environment placing definitions. 89995b72ddSStefan Roese */ 90995b72ddSStefan Roese #define CONFIG_ENV_SECT_SIZE 0x00010000 91995b72ddSStefan Roese #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 92995b72ddSStefan Roese CONFIG_SYS_MONITOR_LEN) 93995b72ddSStefan Roese #define CONFIG_ENV_SIZE 0x02000 94995b72ddSStefan Roese #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 95995b72ddSStefan Roese CONFIG_ENV_SECT_SIZE) 96995b72ddSStefan Roese #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 97995b72ddSStefan Roese 98995b72ddSStefan Roese /* Miscellaneous configurable options */ 99995b72ddSStefan Roese #define CONFIG_ARCH_CPU_INIT 100995b72ddSStefan Roese #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 101995b72ddSStefan Roese #define CONFIG_CMDLINE_TAG 102995b72ddSStefan Roese #define CONFIG_SETUP_MEMORY_TAGS 103995b72ddSStefan Roese #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 104995b72ddSStefan Roese 105995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 106995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_END 0x04000000 107285e266bSStefan Roese #define CONFIG_SYS_MALLOC_LEN (8 << 20) 108995b72ddSStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 109995b72ddSStefan Roese 1105bc0543dSMario Six #define CONFIG_HOSTNAME "x600" 111995b72ddSStefan Roese #define CONFIG_UBI_PART ubi0 112995b72ddSStefan Roese #define CONFIG_UBIFS_VOLUME rootfs 113995b72ddSStefan Roese 114995b72ddSStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 115995b72ddSStefan Roese "u-boot_addr=1000000\0" \ 1165bc0543dSMario Six "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \ 117995b72ddSStefan Roese "load=tftp ${u-boot_addr} ${u-boot}\0" \ 1184a8c3f69SAnatolij Gustschin "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 1194a8c3f69SAnatolij Gustschin " +${filesize};" \ 1204a8c3f69SAnatolij Gustschin "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 1214a8c3f69SAnatolij Gustschin "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 122995b72ddSStefan Roese " ${filesize};" \ 1234a8c3f69SAnatolij Gustschin "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 124995b72ddSStefan Roese " +${filesize}\0" \ 125995b72ddSStefan Roese "upd=run load update\0" \ 1265bc0543dSMario Six "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ 1274a8c3f69SAnatolij Gustschin "part=" __stringify(CONFIG_UBI_PART) "\0" \ 1284a8c3f69SAnatolij Gustschin "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 129995b72ddSStefan Roese "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 130995b72ddSStefan Roese "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 131995b72ddSStefan Roese " ${filesize}\0" \ 132995b72ddSStefan Roese "upd_ubifs=run load_ubifs update_ubifs\0" \ 133995b72ddSStefan Roese "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 134995b72ddSStefan Roese "ubi create ${vol} 4000000\0" \ 135995b72ddSStefan Roese "netdev=eth0\0" \ 136995b72ddSStefan Roese "rootpath=/opt/eldk-4.2/arm\0" \ 137995b72ddSStefan Roese "nfsargs=setenv bootargs root=/dev/nfs rw " \ 138995b72ddSStefan Roese "nfsroot=${serverip}:${rootpath}\0" \ 139995b72ddSStefan Roese "ramargs=setenv bootargs root=/dev/ram rw\0" \ 140995b72ddSStefan Roese "boot_part=0\0" \ 141995b72ddSStefan Roese "altbootcmd=if test $boot_part -eq 0;then " \ 142995b72ddSStefan Roese "echo Switching to partition 1!;" \ 143995b72ddSStefan Roese "setenv boot_part 1;" \ 144995b72ddSStefan Roese "else; " \ 145995b72ddSStefan Roese "echo Switching to partition 0!;" \ 146995b72ddSStefan Roese "setenv boot_part 0;" \ 147995b72ddSStefan Roese "fi;" \ 148995b72ddSStefan Roese "saveenv;boot\0" \ 149995b72ddSStefan Roese "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 150995b72ddSStefan Roese "root=ubi0:rootfs rootfstype=ubifs\0" \ 1515bc0543dSMario Six "kernel=" CONFIG_HOSTNAME "/uImage\0" \ 152995b72ddSStefan Roese "kernel_fs=/boot/uImage \0" \ 153995b72ddSStefan Roese "kernel_addr=1000000\0" \ 1545bc0543dSMario Six "dtb=" CONFIG_HOSTNAME "/" \ 1555bc0543dSMario Six CONFIG_HOSTNAME ".dtb\0" \ 1565bc0543dSMario Six "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ 157995b72ddSStefan Roese "dtb_addr=1800000\0" \ 158995b72ddSStefan Roese "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 159995b72ddSStefan Roese "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 160995b72ddSStefan Roese "addip=setenv bootargs ${bootargs} " \ 161995b72ddSStefan Roese "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 162995b72ddSStefan Roese ":${hostname}:${netdev}:off panic=1\0" \ 163995b72ddSStefan Roese "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 164995b72ddSStefan Roese "${baudrate}\0" \ 165995b72ddSStefan Roese "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 166995b72ddSStefan Roese "net_nfs=run load_dtb load_kernel; " \ 167995b72ddSStefan Roese "run nfsargs addip addcon addmtd addmisc;" \ 168995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 16943ede0bcSTom Rini "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 17043ede0bcSTom Rini "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 171995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 172995b72ddSStefan Roese " addcon addmisc addmtd;" \ 173995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 174949a7710SJoe Hershberger "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 175995b72ddSStefan Roese "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 176995b72ddSStefan Roese "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 177995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 178995b72ddSStefan Roese "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 179995b72ddSStefan Roese "bootcmd=run nand_ubifs\0" \ 180995b72ddSStefan Roese "\0" 181995b72ddSStefan Roese 182995b72ddSStefan Roese /* Physical Memory Map */ 183995b72ddSStefan Roese #define PHYS_SDRAM_1 0x00000000 184995b72ddSStefan Roese #define PHYS_SDRAM_1_MAXSIZE 0x40000000 185995b72ddSStefan Roese 186995b72ddSStefan Roese #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 1872fbdbda1SStefan Roese #define CONFIG_SRAM_BASE 0xd2800000 1882fbdbda1SStefan Roese /* Preserve the last 2 lwords for the boot-counter */ 1892fbdbda1SStefan Roese #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 1902fbdbda1SStefan Roese #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 1912fbdbda1SStefan Roese #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 192995b72ddSStefan Roese 193995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET \ 194995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 195995b72ddSStefan Roese 196995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_ADDR \ 197995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 198995b72ddSStefan Roese 199995b72ddSStefan Roese /* 200995b72ddSStefan Roese * SPL related defines 201995b72ddSStefan Roese */ 202995b72ddSStefan Roese #define CONFIG_SPL_TEXT_BASE 0xd2800b00 2032fbdbda1SStefan Roese #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 204995b72ddSStefan Roese #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 205995b72ddSStefan Roese 206995b72ddSStefan Roese /* 207995b72ddSStefan Roese * Please select/define only one of the following 208995b72ddSStefan Roese * Each definition corresponds to a supported DDR chip. 209995b72ddSStefan Roese * DDR configuration is based on the following selection 210995b72ddSStefan Roese */ 211995b72ddSStefan Roese #define CONFIG_DDR_MT47H64M16 1 212995b72ddSStefan Roese #define CONFIG_DDR_MT47H32M16 0 213995b72ddSStefan Roese #define CONFIG_DDR_MT47H128M8 0 214995b72ddSStefan Roese 215995b72ddSStefan Roese /* 216995b72ddSStefan Roese * Synchronous/Asynchronous operation of DDR 217995b72ddSStefan Roese * 218995b72ddSStefan Roese * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 219995b72ddSStefan Roese * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 220995b72ddSStefan Roese * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 221995b72ddSStefan Roese */ 222995b72ddSStefan Roese #define CONFIG_DDR_2HCLK 1 223995b72ddSStefan Roese #define CONFIG_DDR_HCLK 0 224995b72ddSStefan Roese #define CONFIG_DDR_PLL2 0 225995b72ddSStefan Roese 226995b72ddSStefan Roese /* 227995b72ddSStefan Roese * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 228995b72ddSStefan Roese * or not. Modify/Add to only these macros to define new boot types 229995b72ddSStefan Roese */ 230995b72ddSStefan Roese #define USB_BOOT_SUPPORTED 0 231995b72ddSStefan Roese #define PCIE_BOOT_SUPPORTED 0 232995b72ddSStefan Roese #define SNOR_BOOT_SUPPORTED 1 233995b72ddSStefan Roese #define NAND_BOOT_SUPPORTED 1 234995b72ddSStefan Roese #define PNOR_BOOT_SUPPORTED 0 235995b72ddSStefan Roese #define TFTP_BOOT_SUPPORTED 0 236995b72ddSStefan Roese #define UART_BOOT_SUPPORTED 0 237995b72ddSStefan Roese #define SPI_BOOT_SUPPORTED 0 238995b72ddSStefan Roese #define I2C_BOOT_SUPPORTED 0 239995b72ddSStefan Roese #define MMC_BOOT_SUPPORTED 0 240995b72ddSStefan Roese 241995b72ddSStefan Roese #endif /* __CONFIG_H */ 242