| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | nvidia,tegra210-xusb.yaml | 42 - description: XUSB SuperSpeed clock
43 - description: XUSB SuperSpeed clock divider
44 - description: XUSB SuperSpeed source clock
68 - description: reset for the SuperSpeed logic
104 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra124-xusb.yaml | 50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
76 - description: reset for the SuperSpeed logic
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| H A D | microchip,usb5744.yaml | 10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
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| H A D | nvidia,tegra234-xusb.yaml | 43 - description: XUSB SuperSpeed clock
44 - description: XUSB SuperSpeed source clock
102 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra194-xusb.yaml | 39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
98 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra186-xusb.yaml | 39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
97 - description: XUSBA power domain (for SuperSpeed)
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| H A D | nvidia,tegra-xudc.yaml | 11 USB 3.0 SuperSpeed protocols.
79 - description: XUSBA(superspeed) power-domain
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| H A D | dwc3-cavium.txt | 1 Cavium SuperSpeed DWC3 USB SoC controller
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,gcc-sc8280xp.yaml | 32 - description: Primary USB SuperSpeed pipe clock
40 - description: Secondary USB SuperSpeed pipe clock
48 - description: Multiport USB first SuperSpeed pipe clock
49 - description: Multiport USB second SuperSpeed pipe clock
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,usb-ss.yaml | 7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
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| /openbmc/linux/drivers/usb/dwc3/ |
| H A D | dwc3-octeon.c | 30 /* Reference clock select for SuperSpeed and HighSpeed PLLs:
33 * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
35 * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
60 /* Enable reference clock to prescaler for SuperSpeed functionality.
101 /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
105 /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
326 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ in dwc3_octeon_setup()
329 /* Step 5c: Enable SuperSpeed. */ in dwc3_octeon_setup()
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| /openbmc/u-boot/include/linux/usb/ |
| H A D | dwc3-omap.h | 6 * Designware SuperSpeed Glue
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| /openbmc/linux/drivers/thunderbolt/ |
| H A D | acpi.c | 37 * bound so the USB3 SuperSpeed ports are not yet created. in tb_acpi_add_link()
49 * SuperSpeed ports have this property and they are not power in tb_acpi_add_link()
50 * managed with the xHCI and the SuperSpeed hub so we create the in tb_acpi_add_link()
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| /openbmc/u-boot/include/ |
| H A D | dwc3-omap-uboot.h | 6 * Designware SuperSpeed OMAP Glue uboot init
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| H A D | dwc3-uboot.h | 6 * Designware SuperSpeed USB uboot init
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| /openbmc/linux/Documentation/driver-api/usb/ |
| H A D | usb3-debug-port.rst | 75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
143 [ 79.454780] usb 2-2.1: new SuperSpeed USB device number 3 using xhci_hcd
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| H A D | power-management.rst | 655 another hub. The expectation is that all superspeed ports have a
662 peer ports are simply the hi-speed and superspeed interface pins that
666 While a superspeed port is powered off a device may downgrade its
671 before their superspeed peer is permitted to power-off. The implication is
672 that the setting ``pm_qos_no_power_off`` to zero on a superspeed port may
675 if it wants to guarantee that a superspeed port will power-off.
677 2. Port resume is sequenced to force a superspeed port to power-on prior to its
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| /openbmc/linux/drivers/usb/core/ |
| H A D | port.c | 520 * may miss a suspend event for the SuperSpeed port. in link_peers()
537 * The SuperSpeed reference is dropped when the HiSpeed port in in link_peers()
539 * SuperSpeed connection to drop since there is no risk of a in link_peers()
575 * usb_port_runtime_resume() event which takes a SuperSpeed ref in unlink_peers()
593 /* Drop the SuperSpeed ref held on behalf of the active HiSpeed port */ in unlink_peers()
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| /openbmc/linux/include/linux/usb/ |
| H A D | gadget.h | 217 * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
347 * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
348 * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
422 /* USB SuperSpeed Plus only */
571 * gadget_is_superspeed() - return true if the hardware handles superspeed
572 * @g: controller that might support superspeed
581 * superspeed plus
582 * @g: controller that might support superspeed plus
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| H A D | ch9.h | 35 /* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
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| /openbmc/u-boot/drivers/usb/host/ |
| H A D | Kconfig | 14 "SuperSpeed" host controller hardware.
21 Say Y or if your system has a Dual Role SuperSpeed
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| /openbmc/u-boot/drivers/usb/dwc3/ |
| H A D | Kconfig | 5 Say Y here if your system has a Dual Role SuperSpeed
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| /openbmc/linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12b-s922x-khadas-vim3.dts | 20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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| H A D | meson-g12b-a311d-khadas-vim3.dts | 20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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| /openbmc/linux/drivers/usb/mtu3/ |
| H A D | Kconfig | 13 Dual Role SuperSpeed USB controller. You can select usb
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