Home
last modified time | relevance | path

Searched full:skew (Results 1 – 25 of 81) sorted by relevance

1234

/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt13 All skew control options are specified in picoseconds. The minimum
19 - rxc-skew-ps : Skew control of RXC pad
20 - rxdv-skew-ps : Skew control of RX CTL pad
21 - txc-skew-ps : Skew control of TXC pad
22 - txen-skew-ps : Skew control of TX CTL pad
23 - rxd0-skew-ps : Skew control of RX data 0 pad
24 - rxd1-skew-ps : Skew control of RX data 1 pad
25 - rxd2-skew-ps : Skew control of RX data 2 pad
26 - rxd3-skew-ps : Skew control of RX data 3 pad
27 - txd0-skew-ps : Skew control of TX data 0 pad
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3xcm.dtsi47 txen-skew-ps = <800>;
48 txc-skew-ps = <3000>;
49 rxdv-skew-ps = <400>;
50 rxc-skew-ps = <3000>;
51 rxd0-skew-ps = <400>;
52 rxd1-skew-ps = <400>;
53 rxd2-skew-ps = <400>;
54 rxd3-skew-ps = <400>;
61 txen-skew-ps = <800>;
62 txc-skew-ps = <3000>;
[all …]
H A Dsocfpga_stratix10_socdk.dts62 txd0-skew-ps = <0>; /* -420ps */
63 txd1-skew-ps = <0>; /* -420ps */
64 txd2-skew-ps = <0>; /* -420ps */
65 txd3-skew-ps = <0>; /* -420ps */
66 rxd0-skew-ps = <420>; /* 0ps */
67 rxd1-skew-ps = <420>; /* 0ps */
68 rxd2-skew-ps = <420>; /* 0ps */
69 rxd3-skew-ps = <420>; /* 0ps */
70 txen-skew-ps = <0>; /* -420ps */
71 txc-skew-ps = <1860>; /* 960ps */
[all …]
H A Dsama5d3xcm_cmp.dtsi46 txen-skew-ps = <800>;
47 txc-skew-ps = <3000>;
48 rxdv-skew-ps = <400>;
49 rxc-skew-ps = <3000>;
50 rxd0-skew-ps = <400>;
51 rxd1-skew-ps = <400>;
52 rxd2-skew-ps = <400>;
53 rxd3-skew-ps = <400>;
60 txen-skew-ps = <800>;
61 txc-skew-ps = <3000>;
[all …]
H A Dsocfpga_cyclone5_de0_nano_soc.dts48 txd0-skew-ps = <0>; /* -420ps */
49 txd1-skew-ps = <0>; /* -420ps */
50 txd2-skew-ps = <0>; /* -420ps */
51 txd3-skew-ps = <0>; /* -420ps */
52 rxd0-skew-ps = <420>; /* 0ps */
53 rxd1-skew-ps = <420>; /* 0ps */
54 rxd2-skew-ps = <420>; /* 0ps */
55 rxd3-skew-ps = <420>; /* 0ps */
56 txen-skew-ps = <0>; /* -420ps */
57 txc-skew-ps = <1860>; /* 960ps */
[all …]
H A Dsocfpga_arria10_socdk.dtsi78 * All skews are offset since hardware skew values for the ksz9031
79 * range from a negative skew to a positive skew.
82 txd0-skew-ps = <0>; /* -420ps */
83 txd1-skew-ps = <0>; /* -420ps */
84 txd2-skew-ps = <0>; /* -420ps */
85 txd3-skew-ps = <0>; /* -420ps */
86 rxd0-skew-ps = <420>; /* 0ps */
87 rxd1-skew-ps = <420>; /* 0ps */
88 rxd2-skew-ps = <420>; /* 0ps */
89 rxd3-skew-ps = <420>; /* 0ps */
[all …]
H A Dsocfpga_cyclone5_de10_nano.dts39 rxd0-skew-ps = <420>;
40 rxd1-skew-ps = <420>;
41 rxd2-skew-ps = <420>;
42 rxd3-skew-ps = <420>;
43 txen-skew-ps = <0>;
44 txc-skew-ps = <1860>;
45 rxdv-skew-ps = <420>;
46 rxc-skew-ps = <1680>;
H A Dsocfpga_cyclone5_de1_soc.dts37 rxd0-skew-ps = <420>;
38 rxd1-skew-ps = <420>;
39 rxd2-skew-ps = <420>;
40 rxd3-skew-ps = <420>;
41 txen-skew-ps = <0>;
42 txc-skew-ps = <1860>;
43 rxdv-skew-ps = <420>;
44 rxc-skew-ps = <1680>;
H A Dimx6qdl-icore-rqs.dtsi65 rxc-skew-ps = <1140>;
66 txc-skew-ps = <1140>;
67 txen-skew-ps = <600>;
68 rxdv-skew-ps = <240>;
69 rxd0-skew-ps = <420>;
70 rxd1-skew-ps = <600>;
71 rxd2-skew-ps = <420>;
72 rxd3-skew-ps = <240>;
73 txd0-skew-ps = <60>;
74 txd1-skew-ps = <60>;
[all …]
H A Dsocfpga_cyclone5_is1.dts44 rxd0-skew-ps = <0>;
45 rxd1-skew-ps = <0>;
46 rxd2-skew-ps = <0>;
47 rxd3-skew-ps = <0>;
48 txen-skew-ps = <0>;
49 txc-skew-ps = <2600>;
50 rxdv-skew-ps = <0>;
51 rxc-skew-ps = <2000>;
H A Dsocfpga_arria5_socdk.dts65 rxd0-skew-ps = <0>;
66 rxd1-skew-ps = <0>;
67 rxd2-skew-ps = <0>;
68 rxd3-skew-ps = <0>;
69 txen-skew-ps = <0>;
70 txc-skew-ps = <2600>;
71 rxdv-skew-ps = <0>;
72 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_socdk.dts69 rxd0-skew-ps = <0>;
70 rxd1-skew-ps = <0>;
71 rxd2-skew-ps = <0>;
72 rxd3-skew-ps = <0>;
73 txen-skew-ps = <0>;
74 txc-skew-ps = <2600>;
75 rxdv-skew-ps = <0>;
76 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_sockit.dts126 rxd0-skew-ps = <0>;
127 rxd1-skew-ps = <0>;
128 rxd2-skew-ps = <0>;
129 rxd3-skew-ps = <0>;
130 txen-skew-ps = <0>;
131 txc-skew-ps = <2600>;
132 rxdv-skew-ps = <0>;
133 rxc-skew-ps = <2000>;
H A Dsocfpga_cyclone5_vining_fpga.dts83 rxd0-skew-ps = <0>;
84 rxd1-skew-ps = <0>;
85 rxd2-skew-ps = <0>;
86 rxd3-skew-ps = <0>;
87 txen-skew-ps = <0>;
88 txc-skew-ps = <2600>;
89 rxdv-skew-ps = <0>;
90 rxc-skew-ps = <2000>;
/openbmc/u-boot/drivers/net/phy/
H A Dmicrel_ksz90x1.c82 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
83 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
87 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
88 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
92 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
93 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
97 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
101 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c54 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
97 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
/openbmc/u-boot/board/seco/common/
H A Dmx6.c76 /* control data pad skew - devaddr = 0x02, register = 0x04 */ in seco_mx6_rgmii_rework()
80 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ in seco_mx6_rgmii_rework()
84 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ in seco_mx6_rgmii_rework()
89 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ in seco_mx6_rgmii_rework()
/openbmc/u-boot/board/spear/x600/
H A Dx600.c85 /* control data pad skew - devaddr = 0x02, register = 0x04 */ in board_phy_config()
90 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ in board_phy_config()
95 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ in board_phy_config()
100 /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ in board_phy_config()
/openbmc/u-boot/board/liebherr/mccmon6/
H A Dmccmon6.c384 * Default setting for GMII Clock Pad Skew Register 0x1EF: in board_phy_config()
387 * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew in board_phy_config()
388 * RX_CLK Pad Skew 0xF -> 0.9 nsec skew in board_phy_config()
391 * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew in board_phy_config()
392 * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew in board_phy_config()
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c41 /* Temp array for skew data storage */
80 * Array to hold the total sum of skew from all iterations in ddr3_pbs_tx()
86 * Array to hold the total average skew from both patterns in ddr3_pbs_tx()
254 /* Set skew value for all dq */ in ddr3_pbs_tx()
303 /* set skew value for all dq */ in ddr3_pbs_tx()
316 * Calculate the average skew for current pattern for each in ddr3_pbs_tx()
325 * pattern skew array in ddr3_pbs_tx()
336 /* Calculate the average skew */ in ddr3_pbs_tx()
354 /* Set skew value for all dq */ in ddr3_pbs_tx()
522 * Array to hold the total sum of skew from all iterations in ddr3_pbs_rx()
[all …]
/openbmc/u-boot/board/udoo/
H A Dudoo.c78 /* control data pad skew - devaddr = 0x02, register = 0x04 */ in mx6_rgmii_rework()
82 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ in mx6_rgmii_rework()
86 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ in mx6_rgmii_rework()
90 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ in mx6_rgmii_rework()
/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/
H A DCP00.interface.yaml19 MK keyword.Mesh Clock Skew.
/openbmc/u-boot/include/
H A Dspd.h59 unsigned char tdqsq; /* 44 Max DQS to DQ skew */
60 unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh

1234