| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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| H A D | phy-cadence-sierra.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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| H A D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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| H A D | qcom,msm8996-qmp-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-usb3-phy
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
16 processing, single pass security offload and robust traffic management
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | xusb-padctl-common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
11 #include "xusb-padctl-common.h"
17 if (phy && phy->ops && phy->ops->prepare) in tegra_xusb_phy_prepare()
18 return phy->ops->prepare(phy); in tegra_xusb_phy_prepare()
20 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_prepare()
25 if (phy && phy->ops && phy->ops->enable) in tegra_xusb_phy_enable()
26 return phy->ops->enable(phy); in tegra_xusb_phy_enable()
28 return phy ? -ENOSYS : -EINVAL; in tegra_xusb_phy_enable()
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| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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| H A D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
33 vddio-supply:
36 stby-gpios:
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| H A D | ps8640.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk_edp.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <dt-bindings/clock/rk3288-cru.h>
46 writel(SEL_24M, ®s->analog_ctl_2); in rk_edp_init_refclk()
47 writel(REF_CLK_24M, ®s->pll_reg_1); in rk_edp_init_refclk()
50 V2L_CUR_SEL_1MA, ®s->pll_reg_2); in rk_edp_init_refclk()
54 ®s->pll_reg_3); in rk_edp_init_refclk()
58 ®s->pll_reg_5); in rk_edp_init_refclk()
60 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg); in rk_edp_init_refclk()
64 ®s->tx_common); in rk_edp_init_refclk()
67 ®s->dp_aux); in rk_edp_init_refclk()
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | hte.c | 1 // SPDX-License-Identifier: Intel
18 * (per-bit or full byte lane).
73 * Execute a basic single-cache-line memory write/read/verify test using simple
81 * assumed configuration is done and we just re-run the test
84 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
125 * Examine a single-cache-line memory with write/read/verify test using multiple
126 * data patterns (victim-aggressor algorithm).
135 * @victim_bit: should be 0 as auto-rotate feature is in use
137 * assumed configuration is done and we just re-run the test
139 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
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| /openbmc/linux/drivers/edac/ |
| H A D | thunderx_edac.c | 8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
56 while (descr->type && descr->mask && descr->descr) { in decode_register()
57 if (reg & descr->mask) { in decode_register()
59 descr->type == ERR_CORRECTED ? in decode_register()
61 descr->descr); in decode_register()
63 size -= ret; in decode_register()
71 return (data >> pos) & ((1 << width) - 1); in get_bits()
127 .descr = "Single-bit ECC error",
137 .descr = "Double-bit ECC error",
142 .descr = "Non-existent memory write",
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| /openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
| H A D | high_speed_env_spec-38x.c | 1 // SPDX-License-Identifier: GPL-2.0
66 case MV_6811: /* A381/A3282: 6811/6821: single/dual cpu */ in hws_serdes_get_max_lane()
85 /* Maximum lane count for A388 (6828) is 6 */ in hws_is_serdes_active()
89 /* 4th Lane (#4 on Device 6810 is not Active */ in hws_is_serdes_active()
91 printf("%s: Error: Lane#4 on Device 6810 is not Active.\n", in hws_is_serdes_active()
97 * 6th Lane (#5) on Device 6810 is Active, even though 6810 in hws_is_serdes_active()
123 * INPUT: serdes_num - Serdes number
124 * serdes_type - Serdes type
|
| /openbmc/linux/drivers/gpu/drm/bridge/ |
| H A D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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| /openbmc/linux/drivers/thunderbolt/ |
| H A D | clx.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 - 2023, Intel Corporation
16 MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
44 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
54 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set()
73 /* Don't enable CLx in case of two single-lane links */ in tb_port_clx_supported()
74 if (!port->bonded && port->dual_link_port) in tb_port_clx_supported()
77 /* Don't enable CLx in case of inter-domain link */ in tb_port_clx_supported()
78 if (port->xdomain) in tb_port_clx_supported()
81 if (tb_switch_is_usb4(port->sw)) { in tb_port_clx_supported()
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| /openbmc/linux/drivers/phy/tegra/ |
| H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
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| /openbmc/linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 45 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
50 * @aux_ch: driver callback to transfer a single byte of the i2c payload
60 /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
65 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
68 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
85 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
92 algo_data->address = address; in i2c_algo_dp_aux_address()
93 algo_data->running = true; in i2c_algo_dp_aux_address()
104 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
111 if (algo_data->running) { in i2c_algo_dp_aux_stop()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
8 * and earlier U-Boot Allwinner A10 SPL work
10 * (C) Copyright 2007-2012
68 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()
69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-io.json | 148 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
154 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
165 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
187 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
198 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
209 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
220 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
231 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
242 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra124-xusb-padctl.txt | 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
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| /openbmc/linux/drivers/phy/cadence/ |
| H A D | phy-cadence-torrent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
228 /* PHY PCS lane registers */
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
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