Searched full:srwd (Results 1 – 4 of 4) sorted by relevance
/openbmc/qemu/tests/qtest/ |
H A D | aspeed-smc-utils.c | 492 /* default case: WP# is high and SRWD is low -> status register writable */ in aspeed_smc_test_status_reg_write_protection() 495 /* test ability to write SRWD */ in aspeed_smc_test_status_reg_write_protection() 497 flash_writeb(test_data, 0, SRWD); in aspeed_smc_test_status_reg_write_protection() 501 g_assert_cmphex(r & SRWD, ==, SRWD); in aspeed_smc_test_status_reg_write_protection() 503 /* WP# high and SRWD high -> status register writable */ in aspeed_smc_test_status_reg_write_protection() 506 /* test ability to write SRWD */ in aspeed_smc_test_status_reg_write_protection() 512 g_assert_cmphex(r & SRWD, ==, 0); in aspeed_smc_test_status_reg_write_protection() 514 /* WP# low and SRWD low -> status register writable */ in aspeed_smc_test_status_reg_write_protection() 518 /* test ability to write SRWD */ in aspeed_smc_test_status_reg_write_protection() 520 flash_writeb(test_data, 0, SRWD); in aspeed_smc_test_status_reg_write_protection() [all …]
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H A D | aspeed-smc-utils.h | 62 SRWD = 0x80, enumerator
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/openbmc/linux/Documentation/devicetree/bindings/mtd/ |
H A D | jedec,spi-nor.yaml | 78 The status register write disable (SRWD) bit in status register, combined 80 the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard 85 pull-downs) then status register permanently becomes read-only as the SRWD bit 87 the SRWD bit while writing the status register. WP# signal hard strapped to GND
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/openbmc/linux/drivers/mtd/spi-nor/ |
H A D | atmel.c | 87 /* SRWD bit needs to be cleared, otherwise the protection doesn't change */ in atmel_nor_set_global_protection() 92 dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n"); in atmel_nor_set_global_protection() 100 * Set the SRWD bit again as soon as we are protecting in atmel_nor_set_global_protection() 103 * spi_nor_sr_lock(), which sets SRWD if any block protection in atmel_nor_set_global_protection()
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