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/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml4 $id: http://devicetree.org/schemas/sram/sram.yaml#
7 title: Generic on-chip SRAM
15 Each child of the sram node specifies a region of reserved memory. Each
25 pattern: "^sram(@.*)?"
30 - mmio-sram
31 - amlogic,meson-gxbb-sram
32 - arm,juno-sram-ns
38 - rockchip,rk3288-pmu-sram
47 SRAM clock.
58 Should translate from local addresses within the sram to bus addresses.
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H A Dallwinner,sun4i-a10-system-control.yaml4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
28 - allwinner,sun4i-a10-sram-controller
29 - allwinner,sun50i-a64-sram-controller
59 "^sram@[a-z0-9]+":
60 $ref: /schemas/sram/sram.yaml#
64 "^sram-section?@[a-f0-9]+$":
73 - const: allwinner,sun4i-a10-sram-a3-a4
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/openbmc/linux/drivers/misc/
H A Dsram.c3 * Generic on-chip SRAM allocation driver
21 #include "sram.h"
55 static int sram_add_pool(struct sram_dev *sram, struct sram_reserve *block, in sram_add_pool() argument
60 part->pool = devm_gen_pool_create(sram->dev, ilog2(SRAM_GRANULARITY), in sram_add_pool()
68 dev_err(sram->dev, "failed to register subpool: %d\n", ret); in sram_add_pool()
75 static int sram_add_export(struct sram_dev *sram, struct sram_reserve *block, in sram_add_export() argument
79 part->battr.attr.name = devm_kasprintf(sram->dev, GFP_KERNEL, in sram_add_export()
80 "%llx.sram", in sram_add_export()
90 return device_create_bin_file(sram->dev, &part->battr); in sram_add_export()
93 static int sram_add_partition(struct sram_dev *sram, struct sram_reserve *block, in sram_add_partition() argument
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H A Dsram-exec.c3 * SRAM protect-exec region helper functions
12 #include <linux/sram.h>
17 #include "sram.h"
22 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
29 dev_err(sram->dev, in sram_check_protect_exec()
30 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
47 * sram_exec_copy - copy data to a protected executable region of sram
49 * @pool: struct gen_pool retrieved that is part of this sram
57 * This helper function allows sram driver to act as central control location
58 * of 'protect-exec' pools which are normal sram pools but are always set
/openbmc/linux/arch/arm/mach-omap1/
H A Dsram-init.c3 * OMAP SRAM detection and management
22 #include "sram.h"
35 * Memory allocator for SRAM: calculates the new ceiling address
48 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
61 void *sram; in omap_sram_push() local
66 sram = omap_sram_push_address(size); in omap_sram_push()
67 if (!sram) in omap_sram_push()
70 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
75 dst = fncpy(sram, funcp, size); in omap_sram_push()
83 * The amount of SRAM depends on the core type.
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/openbmc/linux/arch/arm/mach-omap2/
H A Dsram.c4 * OMAP SRAM detection and management
29 #include "sram.h"
57 * Memory allocator for SRAM: calculates the new ceiling address
70 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
83 void *sram; in omap_sram_push() local
88 sram = omap_sram_push_address(size); in omap_sram_push()
89 if (!sram) in omap_sram_push()
92 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
97 dst = fncpy(sram, funcp, size); in omap_sram_push()
105 * The SRAM context is lost during off-idle and stack
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4357.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/openbmc/u-boot/board/samsung/common/
H A Dexynos-uboot-spl.lds11 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
26 } >.sram
29 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
32 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
37 } >.sram
40 .machine_param : { *(.machine_param) } >.sram
48 } >.sram
57 } >.sram
/openbmc/linux/arch/arm/mach-davinci/
H A Dsram.h3 * mach/sram.h - DaVinci simple SRAM allocator
10 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14 * SRAM allocations return a CPU virtual address, or NULL on error.
15 * If a DMA address is requested and the SRAM supports DMA, its
18 * Errors include SRAM memory not being available, and requesting
19 * DMA mapped SRAM on systems which don't allow that.
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dmv_cesa.txt9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;
H A Dmarvell-cesa.txt13 region. Can also contain an entry for the SRAM attached to the CESA,
16 - reg-names: "regs". Can contain an "sram" entry, but this representation
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
43 marvell,crypto-sram-size = <0x600>;
/openbmc/linux/drivers/mtd/devices/
H A Dms02-nv.h16 * 0x000000 - 0x3fffff SRAM
19 * Within the SRAM area the following ranges are forced by the system
28 * ID value is found, the firmware considers the SRAM clean, i.e.
38 * as well as the size of SRAM available, which can be 1MiB or 2MiB
44 * stored in the SRAM cannot be relied upon. But from the hardware
74 #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */
75 #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */
76 #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */
77 #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */
78 #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */
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/openbmc/u-boot/board/Barix/ipam390/
H A Du-boot-spl-ipam390.lds10 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
27 } >.sram
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
40 } >.sram
49 } >.sram
56 } >.sram
/openbmc/u-boot/board/davinci/da8xxevm/
H A Du-boot-spl-da850evm.lds10 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
27 } >.sram
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
36 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
43 } >.sram
52 } >.sram
/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst29 the system SRAM) for different peripheral. It can access external RAMs but
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
113 bad with DDR, while they are optimal with SRAM. Hence the SRAM buffer used
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
140 **1. Allocate a SRAM buffer**
142 SRAM device tree node is defined in SoC device tree. You can refer to it in
143 your board device tree to define your SRAM pool.
146 &sram {
147 my_foo_device_dma_pool: dma-sram@0 {
152 Be careful of the start index, in case there are other SRAM consumers.
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/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c279 struct ath_aic_sram_info sram; in ar9003_aic_cal_post_process() local
282 cal_sram_valid[i] = sram.valid = in ar9003_aic_cal_post_process()
284 sram.rot_quad_att_db = in ar9003_aic_cal_post_process()
286 sram.vga_quad_sign = in ar9003_aic_cal_post_process()
288 sram.rot_dir_att_db = in ar9003_aic_cal_post_process()
290 sram.vga_dir_sign = in ar9003_aic_cal_post_process()
292 sram.com_att_6db = in ar9003_aic_cal_post_process()
295 if (sram.valid) { in ar9003_aic_cal_post_process()
296 dir_path_gain_idx = sram.rot_dir_att_db + in ar9003_aic_cal_post_process()
297 com_att_db_table[sram.com_att_6db]; in ar9003_aic_cal_post_process()
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/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pm.c12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
24 static void __iomem *sram; variable
81 mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ in mpc52xx_pm_prepare()
93 sram = mbar + 0x8000; /* Those will be handled by the */ in mpc52xx_pm_prepare()
134 /* save SRAM */ in mpc52xx_pm_enter()
135 memcpy(saved_sram, sram, sram_size); in mpc52xx_pm_enter()
137 /* copy low level suspend code to sram */ in mpc52xx_pm_enter()
138 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size); in mpc52xx_pm_enter()
144 /* disable all but SDRAM and bestcomm (SRAM) clocks */ in mpc52xx_pm_enter()
162 mpc52xx_deep_sleep(sram, sdram, cdm, intr); in mpc52xx_pm_enter()
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Du-boot-spl.lds14 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,
29 } >.sram
34 } >.sram
39 } >.sram
44 } >.sram
49 } >.sram
54 } >.sram
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dcanaan,k210-sram.yaml4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
20 - canaan,k210-sram
47 compatible = "canaan,k210-sram";
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Du-boot-spl.lds15 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
29 } > .sram
32 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
35 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
40 } > .sram
53 } > .sram
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Damlogic,meson-mx-ao-arc.yaml50 sram:
53 phandles to a reserved SRAM region which is used as the memory of
55 AHB SRAM node as per the generic bindings in
56 Documentation/devicetree/bindings/sram/sram.yaml
70 - sram
83 sram = <&ahb_sram_ao_arc>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-orion-net.txt43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Du-boot-spl.lds7 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
23 } >.sram
26 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
29 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
32 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
40 } >.sram
/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Du-boot-spl.lds14 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
30 } >.sram
33 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
36 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
39 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
47 } >.sram

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