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/openbmc/linux/drivers/watchdog/
H A DiTCO_vendor_support.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
9 * provided "AS-IS" and at no charge.
26 #include <linux/errno.h> /* For the -ENODEV/... values */
29 #include <linux/ioport.h> /* For io-port access */
35 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
37 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems - no longer supported */
47 "0 (none), 1=SuperMicro Pent3, 911=Broken SMI BIOS");
55 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
62 * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
[all …]
H A Dmachzwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MachZ ZF-Logic Watchdog Timer driver for Linux
6 * any of this software. This material is provided "AS-IS" in
11 * Based on sbc60xxwdt.c by Jakob Oestergaard
15 * wd#1 - 2 seconds;
16 * wd#2 - 7.2 ms;
17 * After the expiration of wd#1, it can generate a NMI, SCI, SMI, or
21 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
87 MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver");
101 .identity = "ZF-Logic watchdog",
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H A Dnv_tco.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based off i8xx_tco.c:
13 * based on softdog.c by Alan Cox <alan@redhat.com>
121 return -EINVAL; in tco_timer_set_heartbeat()
124 /* "Values of 0h-3h are ignored and should not be attempted" */ in tco_timer_set_heartbeat()
126 return -EINVAL; in tco_timer_set_heartbeat()
137 ret = -EINVAL; in tco_timer_set_heartbeat()
155 return -EBUSY; in nv_tco_open()
198 return -EFAULT; in nv_tco_write()
213 int new_options, retval = -EINVAL; in nv_tco_ioctl()
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/openbmc/linux/tools/power/cpupower/debug/i386/
H A Dintel_gsic.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Based on code found in
7 * linux/include/asm-i386/ist.h and linux/arch/i386/kernel/setup.c
48 printf("non-default command value. If speedstep-smi " in main()
55 printf("non-default command port. If speedstep-smi " in main()
68 "GSIC call, but the newer\nspeedstep-smi driver may " in main()
70 "the speedstep-smi driver:\n"); in main()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c86 * implemented via a per-engine length decoding vfunc.
91 * in the per-engine command tables.
149 * A non-zero step value implies that the command may access multiple
164 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
167 * If the check specifies a non-zero condition_mask then the parser
169 * are non-zero.
192 #define STD_MI_OPCODE_SHIFT (32 - 9)
193 #define STD_3D_OPCODE_SHIFT (32 - 16)
194 #define STD_2D_OPCODE_SHIFT (32 - 10)
195 #define STD_MFX_OPCODE_SHIFT (32 - 16)
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
17 switches. They can be controlled using different interfaces, like SMI,
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
26 The MDIO-connected switches use MDIO protocol to access their registers.
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/openbmc/linux/drivers/mtd/devices/
H A Dspear_smi.c2 * SMI (Serial Memory Controller) device driver for Serial NOR Flash on
4 * The serial nor interface is largely based on m25p80.c, however the SPI
5 * interface has been replaced by SMI.
40 /* SMI clock rate */
50 /* registers of smi */
51 #define SMI_CR1 0x0 /* SMI control register 1 */
52 #define SMI_CR2 0x4 /* SMI control register 2 */
53 #define SMI_SR 0x8 /* SMI status register */
54 #define SMI_TR 0xC /* SMI transmit register */
55 #define SMI_RR 0x10 /* SMI receive register */
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/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Dadln-metrics.json4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
53 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
60 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
67 "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/Security/
H A DRestrictionMode.interface.yaml5 - name: RestrictionMode
11 - name: Modes
15 - name: None
18 - name: Allowlist
21 - name: Blocklist
24 - name: Provisioning
28 - name: ProvisionedHostAllowlist
33 - name: ProvisionedHostDisabled
37 commands are blocked (except BIOS SMI based ones).
/openbmc/linux/Documentation/arch/x86/
H A Dmicrocode.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
8 - Borislav Petkov <bp@suse.de>
9 - Ashok Raj <ashok.raj@intel.com>
13 updating the microcode on platforms beyond the OEM End-Of-Life support,
14 and updating the microcode on long-running systems without rebooting.
39 During BSP (BootStrapping Processor) boot (pre-SMP), the kernel
56 if [ -z "$1" ]; then
66 rm -rf $TMPDIR
70 mkdir -p $DSTDIR
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
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/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c10 * This is based on piix.c, but heavily modified.
48 #include "hw/qdev-properties.h"
90 /* D{25 - 31}IR, but D30IR is read only to 0. */ in ich9_cc_update()
95 ich9_cc_update_ir(lpc->irr[slot], in ich9_cc_update()
96 pci_get_word(lpc->chip_config + *offset)); in ich9_cc_update()
102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. in ich9_cc_update()
103 * INT[A-D] are connected to PIRQ[E-H] in ich9_cc_update()
106 lpc->irr[30][pci_intx] = pci_intx + 4; in ich9_cc_update()
121 * int[A-D] -> pirq[E-F] in ich9_cc_init()
122 * avoid pirq A-D because they are used for pci express port in ich9_cc_init()
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/openbmc/linux/Documentation/admin-guide/media/
H A Dpci-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - Vendor ID and device ID;
10 - Subsystem ID and Subsystem device ID;
12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs:
14 .. code-block:: none
15 :emphasize-lines: 3
17 $ lspci -nn
23 …02:02.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23418 Single-Chip MPEG-2 Enco…
27 The subsystem IDs can be obtained using ``lspci -vn``
29 .. code-block:: none
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/openbmc/linux/arch/x86/kvm/
H A Dsmm.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * 32 bit KVM's emulated SMM layout. Based on Intel P6 layout
69 /* 64 bit KVM's emulated SMM layout. Based on AMD64 layout */
108 * SVM guest vmcb address if the #SMI was received while in the guest mode.
151 return vcpu->arch.hflags & HF_SMM_MASK; in is_smm()
159 static inline int kvm_inject_smi(struct kvm_vcpu *vcpu) { return -ENOTTY; } in kvm_inject_smi()
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
22 pattern: '^power-controller(@[0-9a-f]+)?$'
26 - mediatek,mt6795-power-controller
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/openbmc/linux/drivers/platform/x86/dell/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 Dell x86 platforms, including vendor-specific laptop extension drivers.
28 USB MCU such as the X51 and X51-R2.
40 See <file:Documentation/driver-api/dcdbas.rst> for more details on the driver
77 See <file:Documentation/admin-guide/dell_rbu.rst> for more details on the driver.
94 be called dell-rbtn.
120 communicated over ACPI-WMI.
133 communicated over SMI/SMM.
148 be called dell-smo8800.
161 Say Y here if you want to support WMI-based hotkeys on Dell laptops.
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/openbmc/u-boot/drivers/net/
H A Dmvgbe.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 * based on - Driver for MV64360X ethernet ports
42 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
52 printf("Error: SMI busy timeout\n"); in smi_wait_ready()
62 struct mvgbe_registers *regs = dmvgbe->regs; in __mvgbe_mdio_read()
71 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); in __mvgbe_mdio_read()
78 return -EFAULT; in __mvgbe_mdio_read()
83 return -EFAULT; in __mvgbe_mdio_read()
86 /* wait till the SMI is not busy */ in __mvgbe_mdio_read()
[all …]
H A Dmvneta.c1 // SPDX-License-Identifier: GPL-2.0
5 * U-Boot version:
6 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
8 * Based on the Linux version which is:
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
30 #include <asm-generic/gpio.h>
70 /* SMI register fields */
148 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
150 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
220 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
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/openbmc/qemu/hw/acpi/
H A Dich9.c9 * This is based on acpi.c.
23 * Contributions after 2012-01-13 are licensed under the terms of the
41 #include "hw/mem/pc-dimm.h"
56 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_pm_update_sci_fn()
62 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); in ich9_gpe_readb()
69 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); in ich9_gpe_writeb()
70 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_gpe_writeb()
88 return pm->smi_en; in ich9_smi_readl()
90 return pm->smi_sts; in ich9_smi_readl()
100 TCOIORegs *tr = &pm->tco_regs; in ich9_smi_writel()
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dpxa168_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
38 #define DRIVER_NAME "pxa168-eth"
46 #define SMI 0x0010 macro
63 /* smi register */
64 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
65 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
158 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
173 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
275 return readl_relaxed(pep->base + offset); in rdl()
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/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-39x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell Armada 39x pinctrl driver based on mvebu pinctrl core
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include "pinctrl-mvebu.h"
45 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
50 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
107 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
124 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
363 .compatible = "marvell,mv88f6920-pinctrl",
367 .compatible = "marvell,mv88f6925-pinctrl",
[all …]
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <dm/uclass-internal.h>
69 ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, in broadwell_pch_early_init()
119 /* PCH-LP has 39 redirection entries */ in pch_enable_ioapic()
142 * Enable GPIO SMI events - it would be good to put this in the GPIO driver
155 return -EINVAL; in enable_alt_smi()
159 setio_32(regs->alt_gpi_smi_en, mask); in enable_alt_smi()
193 /* GPE setup based on device tree configuration */ in pch_power_options()
194 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), in pch_power_options()
195 "intel,gpe0-en", enable, ARRAY_SIZE(enable)); in pch_power_options()
[all …]
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-piix4.rst2 Kernel driver i2c-piix4
9 * ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
18 * AMD Hudson-2, ML, CZ
26 - Frodo Looijaard <frodol@dds.nl>
27 - Philip Edelbrock <phil@netroedge.com>
31 -----------------
40 -----------
45 SMBus - you can not access it on I2C levels. The good news is that it
47 timing problems. The bad news is that non-SMBus devices connected to it can
50 Do ``lspci -v`` and see whether it contains an entry like this::
[all …]
/openbmc/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-37xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot Marvell 37xx SoC pinctrl driver
7 * This driver is based on the Linux driver version, which is:
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
22 #include <dm/device-internal.h>
186 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
214 *offset -= GPIO_PER_REG; in armada_37xx_update_reg()
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/openbmc/linux/drivers/ata/
H A Dpata_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata_pcmcia.c - PCMCIA PATA controller driver.
4 * Copyright 2005-2006 Red Hat Inc, all rights reserved.
8 * Heavily based upon ide-cs.c
33 * pcmcia_set_mode - PCMCIA specific mode setup
45 struct ata_device *master = &link->device[0]; in pcmcia_set_mode()
46 struct ata_device *slave = &link->device[1]; in pcmcia_set_mode()
51 if (memcmp(master->id + ATA_ID_FW_REV, slave->id + ATA_ID_FW_REV, in pcmcia_set_mode()
54 the same vendor - check serial */ in pcmcia_set_mode()
55 if (memcmp(master->id + ATA_ID_SERNO, slave->id + ATA_ID_SERNO, in pcmcia_set_mode()
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