12bb3fbadSZhengjun Xing[
22bb3fbadSZhengjun Xing    {
3fa607370SIan Rogers        "BriefDescription": "C10 residency percent per package",
4fa607370SIan Rogers        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
5fa607370SIan Rogers        "MetricGroup": "Power",
6fa607370SIan Rogers        "MetricName": "C10_Pkg_Residency",
72bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
82bb3fbadSZhengjun Xing    },
92bb3fbadSZhengjun Xing    {
102bb3fbadSZhengjun Xing        "BriefDescription": "C1 residency percent per core",
112bb3fbadSZhengjun Xing        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
122bb3fbadSZhengjun Xing        "MetricGroup": "Power",
132bb3fbadSZhengjun Xing        "MetricName": "C1_Core_Residency",
142bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
152bb3fbadSZhengjun Xing    },
162bb3fbadSZhengjun Xing    {
172bb3fbadSZhengjun Xing        "BriefDescription": "C2 residency percent per package",
182bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
192bb3fbadSZhengjun Xing        "MetricGroup": "Power",
202bb3fbadSZhengjun Xing        "MetricName": "C2_Pkg_Residency",
212bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
222bb3fbadSZhengjun Xing    },
232bb3fbadSZhengjun Xing    {
242bb3fbadSZhengjun Xing        "BriefDescription": "C3 residency percent per package",
252bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
262bb3fbadSZhengjun Xing        "MetricGroup": "Power",
272bb3fbadSZhengjun Xing        "MetricName": "C3_Pkg_Residency",
282bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
292bb3fbadSZhengjun Xing    },
302bb3fbadSZhengjun Xing    {
31fa607370SIan Rogers        "BriefDescription": "C6 residency percent per core",
32fa607370SIan Rogers        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
33fa607370SIan Rogers        "MetricGroup": "Power",
34fa607370SIan Rogers        "MetricName": "C6_Core_Residency",
35fa607370SIan Rogers        "ScaleUnit": "100%"
36fa607370SIan Rogers    },
37fa607370SIan Rogers    {
382bb3fbadSZhengjun Xing        "BriefDescription": "C6 residency percent per package",
392bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
402bb3fbadSZhengjun Xing        "MetricGroup": "Power",
412bb3fbadSZhengjun Xing        "MetricName": "C6_Pkg_Residency",
422bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
432bb3fbadSZhengjun Xing    },
442bb3fbadSZhengjun Xing    {
45fa607370SIan Rogers        "BriefDescription": "C7 residency percent per core",
46fa607370SIan Rogers        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
47fa607370SIan Rogers        "MetricGroup": "Power",
48fa607370SIan Rogers        "MetricName": "C7_Core_Residency",
49fa607370SIan Rogers        "ScaleUnit": "100%"
50fa607370SIan Rogers    },
51fa607370SIan Rogers    {
522bb3fbadSZhengjun Xing        "BriefDescription": "C7 residency percent per package",
532bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
542bb3fbadSZhengjun Xing        "MetricGroup": "Power",
552bb3fbadSZhengjun Xing        "MetricName": "C7_Pkg_Residency",
562bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
572bb3fbadSZhengjun Xing    },
582bb3fbadSZhengjun Xing    {
592bb3fbadSZhengjun Xing        "BriefDescription": "C8 residency percent per package",
602bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
612bb3fbadSZhengjun Xing        "MetricGroup": "Power",
622bb3fbadSZhengjun Xing        "MetricName": "C8_Pkg_Residency",
632bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
642bb3fbadSZhengjun Xing    },
652bb3fbadSZhengjun Xing    {
662bb3fbadSZhengjun Xing        "BriefDescription": "C9 residency percent per package",
672bb3fbadSZhengjun Xing        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
682bb3fbadSZhengjun Xing        "MetricGroup": "Power",
692bb3fbadSZhengjun Xing        "MetricName": "C9_Pkg_Residency",
702bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
712bb3fbadSZhengjun Xing    },
722bb3fbadSZhengjun Xing    {
73fa607370SIan Rogers        "BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
74fa607370SIan Rogers        "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75fa607370SIan Rogers        "MetricGroup": "smi",
76fa607370SIan Rogers        "MetricName": "smi_cycles",
77fa607370SIan Rogers        "MetricThreshold": "smi_cycles > 0.1",
78fa607370SIan Rogers        "ScaleUnit": "100%"
79fa607370SIan Rogers    },
80fa607370SIan Rogers    {
81fa607370SIan Rogers        "BriefDescription": "Number of SMI interrupts.",
82fa607370SIan Rogers        "MetricExpr": "msr@smi@",
83fa607370SIan Rogers        "MetricGroup": "smi",
84fa607370SIan Rogers        "MetricName": "smi_num",
85fa607370SIan Rogers        "ScaleUnit": "1SMI#"
86fa607370SIan Rogers    },
87fa607370SIan Rogers    {
88fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to certain allocation restrictions.",
89c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_core_slots",
90fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
91fa607370SIan Rogers        "MetricName": "tma_alloc_restriction",
92fa607370SIan Rogers        "MetricThreshold": "tma_alloc_restriction > 0.1",
93fa607370SIan Rogers        "ScaleUnit": "100%"
94fa607370SIan Rogers    },
95fa607370SIan Rogers    {
96fa607370SIan Rogers        "BriefDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls",
97969a4661SKan Liang        "DefaultMetricgroupName": "TopdownL1",
98c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_core_slots",
99969a4661SKan Liang        "MetricGroup": "Default;TopdownL1;tma_L1_group",
100fa607370SIan Rogers        "MetricName": "tma_backend_bound",
101fa607370SIan Rogers        "MetricThreshold": "tma_backend_bound > 0.1",
102969a4661SKan Liang        "MetricgroupNoGroup": "TopdownL1;Default",
103fa607370SIan Rogers        "PublicDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that uops must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.   The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound.   The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.",
104fa607370SIan Rogers        "ScaleUnit": "100%"
105fa607370SIan Rogers    },
106fa607370SIan Rogers    {
107fa607370SIan Rogers        "BriefDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls",
108969a4661SKan Liang        "DefaultMetricgroupName": "TopdownL1",
109fa607370SIan Rogers        "MetricExpr": "tma_backend_bound",
110969a4661SKan Liang        "MetricGroup": "Default;TopdownL1;tma_L1_group",
111fa607370SIan Rogers        "MetricName": "tma_backend_bound_aux",
112fa607370SIan Rogers        "MetricThreshold": "tma_backend_bound_aux > 0.2",
113969a4661SKan Liang        "MetricgroupNoGroup": "TopdownL1;Default",
114fa607370SIan Rogers        "PublicDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that UOPS must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.  All of these subevents count backend stalls, in slots, due to a resource limitation.   These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based.  These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.",
115fa607370SIan Rogers        "ScaleUnit": "100%"
116fa607370SIan Rogers    },
117fa607370SIan Rogers    {
118fa607370SIan Rogers        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
119969a4661SKan Liang        "DefaultMetricgroupName": "TopdownL1",
120c04fcf7cSIan Rogers        "MetricExpr": "(tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_core_slots",
121969a4661SKan Liang        "MetricGroup": "Default;TopdownL1;tma_L1_group",
122fa607370SIan Rogers        "MetricName": "tma_bad_speculation",
123fa607370SIan Rogers        "MetricThreshold": "tma_bad_speculation > 0.15",
124969a4661SKan Liang        "MetricgroupNoGroup": "TopdownL1;Default",
125fa607370SIan Rogers        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
126fa607370SIan Rogers        "ScaleUnit": "100%"
127fa607370SIan Rogers    },
128fa607370SIan Rogers    {
129fa607370SIan Rogers        "BriefDescription": "Counts the number of uops that are not from the microsequencer.",
130c04fcf7cSIan Rogers        "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_core_slots",
131fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group",
132fa607370SIan Rogers        "MetricName": "tma_base",
133fa607370SIan Rogers        "MetricThreshold": "tma_base > 0.6",
134ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
135fa607370SIan Rogers        "ScaleUnit": "100%"
136fa607370SIan Rogers    },
137fa607370SIan Rogers    {
138fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
139c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_core_slots",
1400372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
141fa607370SIan Rogers        "MetricName": "tma_branch_detect",
142fa607370SIan Rogers        "MetricThreshold": "tma_branch_detect > 0.05",
143fa607370SIan Rogers        "PublicDescription": "Counts the number of issue slots  that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
144fa607370SIan Rogers        "ScaleUnit": "100%"
145fa607370SIan Rogers    },
146fa607370SIan Rogers    {
147fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to branch mispredicts.",
148c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_core_slots",
149fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
150fa607370SIan Rogers        "MetricName": "tma_branch_mispredicts",
151fa607370SIan Rogers        "MetricThreshold": "tma_branch_mispredicts > 0.05",
152ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
153fa607370SIan Rogers        "ScaleUnit": "100%"
154fa607370SIan Rogers    },
155fa607370SIan Rogers    {
156fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
157c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_core_slots",
1580372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
159fa607370SIan Rogers        "MetricName": "tma_branch_resteer",
160fa607370SIan Rogers        "MetricThreshold": "tma_branch_resteer > 0.05",
161fa607370SIan Rogers        "ScaleUnit": "100%"
162fa607370SIan Rogers    },
163fa607370SIan Rogers    {
164fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to the microcode sequencer (MS).",
165c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_core_slots",
1660372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
167fa607370SIan Rogers        "MetricName": "tma_cisc",
168fa607370SIan Rogers        "MetricThreshold": "tma_cisc > 0.05",
169fa607370SIan Rogers        "ScaleUnit": "100%"
170fa607370SIan Rogers    },
171fa607370SIan Rogers    {
172fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.",
1730372358aSIan Rogers        "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
174fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
175fa607370SIan Rogers        "MetricName": "tma_core_bound",
176fa607370SIan Rogers        "MetricThreshold": "tma_core_bound > 0.1",
177ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
178fa607370SIan Rogers        "ScaleUnit": "100%"
179fa607370SIan Rogers    },
180fa607370SIan Rogers    {
181fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to decode stalls.",
182c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_core_slots",
1830372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
184fa607370SIan Rogers        "MetricName": "tma_decode",
185fa607370SIan Rogers        "MetricThreshold": "tma_decode > 0.05",
186fa607370SIan Rogers        "ScaleUnit": "100%"
187fa607370SIan Rogers    },
188fa607370SIan Rogers    {
189fa607370SIan Rogers        "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.",
190fa607370SIan Rogers        "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)",
191fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
192fa607370SIan Rogers        "MetricName": "tma_disambiguation",
193fa607370SIan Rogers        "MetricThreshold": "tma_disambiguation > 0.02",
194fa607370SIan Rogers        "ScaleUnit": "100%"
195fa607370SIan Rogers    },
196fa607370SIan Rogers    {
197fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
198fa607370SIan Rogers        "MetricConstraint": "NO_GROUP_EVENTS",
199c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
2000372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
201fa607370SIan Rogers        "MetricName": "tma_dram_bound",
202fa607370SIan Rogers        "MetricThreshold": "tma_dram_bound > 0.1",
203fa607370SIan Rogers        "ScaleUnit": "100%"
204fa607370SIan Rogers    },
205fa607370SIan Rogers    {
206fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.",
207c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_core_slots",
208fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
209fa607370SIan Rogers        "MetricName": "tma_fast_nuke",
210fa607370SIan Rogers        "MetricThreshold": "tma_fast_nuke > 0.05",
211fa607370SIan Rogers        "ScaleUnit": "100%"
212fa607370SIan Rogers    },
213fa607370SIan Rogers    {
2140372358aSIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
215c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_core_slots",
2160372358aSIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
2170372358aSIan Rogers        "MetricName": "tma_fetch_bandwidth",
2180372358aSIan Rogers        "MetricThreshold": "tma_fetch_bandwidth > 0.1",
219ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
2200372358aSIan Rogers        "ScaleUnit": "100%"
2210372358aSIan Rogers    },
2220372358aSIan Rogers    {
2230372358aSIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
224c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_core_slots",
2250372358aSIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
2260372358aSIan Rogers        "MetricName": "tma_fetch_latency",
2270372358aSIan Rogers        "MetricThreshold": "tma_fetch_latency > 0.15",
228ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
2290372358aSIan Rogers        "ScaleUnit": "100%"
2300372358aSIan Rogers    },
2310372358aSIan Rogers    {
232fa607370SIan Rogers        "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.",
233fa607370SIan Rogers        "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)",
234fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
235fa607370SIan Rogers        "MetricName": "tma_fp_assist",
236fa607370SIan Rogers        "MetricThreshold": "tma_fp_assist > 0.02",
237fa607370SIan Rogers        "ScaleUnit": "100%"
238fa607370SIan Rogers    },
239fa607370SIan Rogers    {
2400372358aSIan Rogers        "BriefDescription": "Counts the number of floating point divide operations per uop.",
241c04fcf7cSIan Rogers        "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_core_slots",
242fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group",
2430372358aSIan Rogers        "MetricName": "tma_fpdiv_uops",
2440372358aSIan Rogers        "MetricThreshold": "tma_fpdiv_uops > 0.2",
245fa607370SIan Rogers        "ScaleUnit": "100%"
246fa607370SIan Rogers    },
247fa607370SIan Rogers    {
248fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to frontend stalls.",
249969a4661SKan Liang        "DefaultMetricgroupName": "TopdownL1",
250c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_core_slots",
251969a4661SKan Liang        "MetricGroup": "Default;TopdownL1;tma_L1_group",
252fa607370SIan Rogers        "MetricName": "tma_frontend_bound",
253fa607370SIan Rogers        "MetricThreshold": "tma_frontend_bound > 0.2",
254969a4661SKan Liang        "MetricgroupNoGroup": "TopdownL1;Default",
255fa607370SIan Rogers        "ScaleUnit": "100%"
256fa607370SIan Rogers    },
257fa607370SIan Rogers    {
258fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to instruction cache misses.",
259c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_core_slots",
2600372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
2610372358aSIan Rogers        "MetricName": "tma_icache_misses",
2620372358aSIan Rogers        "MetricThreshold": "tma_icache_misses > 0.05",
263fa607370SIan Rogers        "ScaleUnit": "100%"
264fa607370SIan Rogers    },
265fa607370SIan Rogers    {
266fa607370SIan Rogers        "BriefDescription": "",
267fa607370SIan Rogers        "MetricExpr": "CPU_CLK_UNHALTED.CORE",
268c04fcf7cSIan Rogers        "MetricName": "tma_info_core_clks"
269fa607370SIan Rogers    },
270fa607370SIan Rogers    {
271fa607370SIan Rogers        "BriefDescription": "",
272fa607370SIan Rogers        "MetricExpr": "CPU_CLK_UNHALTED.CORE_P",
273c04fcf7cSIan Rogers        "MetricName": "tma_info_core_clks_p"
274fa607370SIan Rogers    },
275fa607370SIan Rogers    {
276fa607370SIan Rogers        "BriefDescription": "Cycles Per Instruction",
277c04fcf7cSIan Rogers        "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY",
278c04fcf7cSIan Rogers        "MetricName": "tma_info_core_cpi"
279fa607370SIan Rogers    },
280fa607370SIan Rogers    {
281fa607370SIan Rogers        "BriefDescription": "Instructions Per Cycle",
282c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks",
283c04fcf7cSIan Rogers        "MetricName": "tma_info_core_ipc"
284fa607370SIan Rogers    },
285fa607370SIan Rogers    {
286fa607370SIan Rogers        "BriefDescription": "",
287c04fcf7cSIan Rogers        "MetricExpr": "5 * tma_info_core_clks",
288c04fcf7cSIan Rogers        "MetricName": "tma_info_core_slots"
289fa607370SIan Rogers    },
290fa607370SIan Rogers    {
291fa607370SIan Rogers        "BriefDescription": "Uops Per Instruction",
292fa607370SIan Rogers        "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY",
293c04fcf7cSIan Rogers        "MetricName": "tma_info_core_upi"
294c04fcf7cSIan Rogers    },
295c04fcf7cSIan Rogers    {
296c04fcf7cSIan Rogers        "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
297c04fcf7cSIan Rogers        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
298c04fcf7cSIan Rogers        "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent"
299c04fcf7cSIan Rogers    },
300c04fcf7cSIan Rogers    {
301c04fcf7cSIan Rogers        "BriefDescription": "Percent of instruction miss cost that hit in the L2",
302c04fcf7cSIan Rogers        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
303c04fcf7cSIan Rogers        "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent"
304c04fcf7cSIan Rogers    },
305c04fcf7cSIan Rogers    {
306c04fcf7cSIan Rogers        "BriefDescription": "Percent of instruction miss cost that hit in the L3",
307c04fcf7cSIan Rogers        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
308c04fcf7cSIan Rogers        "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent"
309c04fcf7cSIan Rogers    },
310c04fcf7cSIan Rogers    {
311c04fcf7cSIan Rogers        "BriefDescription": "Ratio of all branches which mispredict",
312c04fcf7cSIan Rogers        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES",
313c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_branch_mispredict_ratio"
314c04fcf7cSIan Rogers    },
315c04fcf7cSIan Rogers    {
316c04fcf7cSIan Rogers        "BriefDescription": "Ratio between Mispredicted branches and unknown branches",
317c04fcf7cSIan Rogers        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY",
318c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_branch_ratio"
319c04fcf7cSIan Rogers    },
320c04fcf7cSIan Rogers    {
321c04fcf7cSIan Rogers        "BriefDescription": "Percentage of all uops which are FPDiv uops",
322c04fcf7cSIan Rogers        "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL",
323c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio"
324c04fcf7cSIan Rogers    },
325c04fcf7cSIan Rogers    {
326c04fcf7cSIan Rogers        "BriefDescription": "Percentage of all uops which are IDiv uops",
327c04fcf7cSIan Rogers        "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL",
328c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_idiv_uop_ratio"
329c04fcf7cSIan Rogers    },
330c04fcf7cSIan Rogers    {
331c04fcf7cSIan Rogers        "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
332c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
333c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipbranch"
334c04fcf7cSIan Rogers    },
335c04fcf7cSIan Rogers    {
336c04fcf7cSIan Rogers        "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
337c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
338c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipcall"
339c04fcf7cSIan Rogers    },
340c04fcf7cSIan Rogers    {
341c04fcf7cSIan Rogers        "BriefDescription": "Instructions per Far Branch",
342c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)",
343c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipfarbranch"
344c04fcf7cSIan Rogers    },
345c04fcf7cSIan Rogers    {
346c04fcf7cSIan Rogers        "BriefDescription": "Instructions per Load",
347c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
348c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipload"
349c04fcf7cSIan Rogers    },
350c04fcf7cSIan Rogers    {
351c04fcf7cSIan Rogers        "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken",
352c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)",
353c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken"
354c04fcf7cSIan Rogers    },
355c04fcf7cSIan Rogers    {
356c04fcf7cSIan Rogers        "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken",
357c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN",
358c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipmisp_cond_taken"
359c04fcf7cSIan Rogers    },
360c04fcf7cSIan Rogers    {
361c04fcf7cSIan Rogers        "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction",
362c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT",
363c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipmisp_indirect"
364c04fcf7cSIan Rogers    },
365c04fcf7cSIan Rogers    {
366c04fcf7cSIan Rogers        "BriefDescription": "Instructions per retired return Branch Misprediction",
367c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN",
368c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipmisp_ret"
369c04fcf7cSIan Rogers    },
370c04fcf7cSIan Rogers    {
371c04fcf7cSIan Rogers        "BriefDescription": "Instructions per retired Branch Misprediction",
372c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
373c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipmispredict"
374c04fcf7cSIan Rogers    },
375c04fcf7cSIan Rogers    {
376c04fcf7cSIan Rogers        "BriefDescription": "Instructions per Store",
377c04fcf7cSIan Rogers        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
378c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_ipstore"
379c04fcf7cSIan Rogers    },
380c04fcf7cSIan Rogers    {
381c04fcf7cSIan Rogers        "BriefDescription": "Percentage of all uops which are ucode ops",
382c04fcf7cSIan Rogers        "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL",
383c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_microcode_uop_ratio"
384fa607370SIan Rogers    },
385fa607370SIan Rogers    {
386fa607370SIan Rogers        "BriefDescription": "Percentage of all uops which are x87 uops",
387fa607370SIan Rogers        "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL",
388c04fcf7cSIan Rogers        "MetricName": "tma_info_inst_mix_x87_uop_ratio"
389c04fcf7cSIan Rogers    },
390c04fcf7cSIan Rogers    {
391c04fcf7cSIan Rogers        "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
392c04fcf7cSIan Rogers        "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS",
393c04fcf7cSIan Rogers        "MetricName": "tma_info_l1_bound_address_alias_blocks"
394c04fcf7cSIan Rogers    },
395c04fcf7cSIan Rogers    {
396c04fcf7cSIan Rogers        "BriefDescription": "Percentage of total non-speculative loads that are splits",
397c04fcf7cSIan Rogers        "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
398c04fcf7cSIan Rogers        "MetricName": "tma_info_l1_bound_load_splits"
399c04fcf7cSIan Rogers    },
400c04fcf7cSIan Rogers    {
401c04fcf7cSIan Rogers        "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
402c04fcf7cSIan Rogers        "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS",
403c04fcf7cSIan Rogers        "MetricName": "tma_info_l1_bound_store_fwd_blocks"
404c04fcf7cSIan Rogers    },
405c04fcf7cSIan Rogers    {
406c04fcf7cSIan Rogers        "BriefDescription": "Cycle cost per DRAM hit",
407c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
408c04fcf7cSIan Rogers        "MetricName": "tma_info_memory_cycles_per_demand_load_dram_hit"
409c04fcf7cSIan Rogers    },
410c04fcf7cSIan Rogers    {
411c04fcf7cSIan Rogers        "BriefDescription": "Cycle cost per L2 hit",
412c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT",
413c04fcf7cSIan Rogers        "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit"
414c04fcf7cSIan Rogers    },
415c04fcf7cSIan Rogers    {
416c04fcf7cSIan Rogers        "BriefDescription": "Cycle cost per LLC hit",
417c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT",
418c04fcf7cSIan Rogers        "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit"
419c04fcf7cSIan Rogers    },
420c04fcf7cSIan Rogers    {
421c04fcf7cSIan Rogers        "BriefDescription": "load ops retired per 1000 instruction",
422c04fcf7cSIan Rogers        "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
423c04fcf7cSIan Rogers        "MetricName": "tma_info_memory_memloadpki"
424c04fcf7cSIan Rogers    },
425c04fcf7cSIan Rogers    {
426c04fcf7cSIan Rogers        "BriefDescription": "Average CPU Utilization",
427c04fcf7cSIan Rogers        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
428c04fcf7cSIan Rogers        "MetricName": "tma_info_system_cpu_utilization"
429c04fcf7cSIan Rogers    },
430c04fcf7cSIan Rogers    {
431c04fcf7cSIan Rogers        "BriefDescription": "Fraction of cycles spent in Kernel mode",
432c04fcf7cSIan Rogers        "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE",
433c04fcf7cSIan Rogers        "MetricGroup": "Summary",
434c04fcf7cSIan Rogers        "MetricName": "tma_info_system_kernel_utilization"
435c04fcf7cSIan Rogers    },
436c04fcf7cSIan Rogers    {
437c04fcf7cSIan Rogers        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
438c04fcf7cSIan Rogers        "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC",
439c04fcf7cSIan Rogers        "MetricGroup": "Power",
440c04fcf7cSIan Rogers        "MetricName": "tma_info_system_turbo_utilization"
441fa607370SIan Rogers    },
442fa607370SIan Rogers    {
443fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
444c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_core_slots",
4450372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group",
4460372358aSIan Rogers        "MetricName": "tma_itlb_misses",
4470372358aSIan Rogers        "MetricThreshold": "tma_itlb_misses > 0.05",
448fa607370SIan Rogers        "ScaleUnit": "100%"
449fa607370SIan Rogers    },
450fa607370SIan Rogers    {
451fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.",
452c04fcf7cSIan Rogers        "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_core_clks",
4530372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
454fa607370SIan Rogers        "MetricName": "tma_l1_bound",
455fa607370SIan Rogers        "MetricThreshold": "tma_l1_bound > 0.1",
456fa607370SIan Rogers        "ScaleUnit": "100%"
457fa607370SIan Rogers    },
458fa607370SIan Rogers    {
459fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
460fa607370SIan Rogers        "MetricConstraint": "NO_GROUP_EVENTS",
461c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
4620372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
463fa607370SIan Rogers        "MetricName": "tma_l2_bound",
464fa607370SIan Rogers        "MetricThreshold": "tma_l2_bound > 0.1",
465fa607370SIan Rogers        "ScaleUnit": "100%"
466fa607370SIan Rogers    },
467fa607370SIan Rogers    {
468fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
469*9a7d82c1SIan Rogers        "MetricConstraint": "NO_GROUP_EVENTS_NMI",
470c04fcf7cSIan Rogers        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks, 0) * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
4710372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
472fa607370SIan Rogers        "MetricName": "tma_l3_bound",
473fa607370SIan Rogers        "MetricThreshold": "tma_l3_bound > 0.1",
474fa607370SIan Rogers        "ScaleUnit": "100%"
475fa607370SIan Rogers    },
476fa607370SIan Rogers    {
477fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full",
478fa607370SIan Rogers        "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL",
479fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
480fa607370SIan Rogers        "MetricName": "tma_ld_buffer",
481fa607370SIan Rogers        "MetricThreshold": "tma_ld_buffer > 0.05",
482fa607370SIan Rogers        "ScaleUnit": "100%"
483fa607370SIan Rogers    },
484fa607370SIan Rogers    {
485fa607370SIan Rogers        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
486c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_core_slots",
487fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
488fa607370SIan Rogers        "MetricName": "tma_machine_clears",
489fa607370SIan Rogers        "MetricThreshold": "tma_machine_clears > 0.05",
490ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
491fa607370SIan Rogers        "ScaleUnit": "100%"
492fa607370SIan Rogers    },
493fa607370SIan Rogers    {
494fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
495c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_core_slots",
496fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
497fa607370SIan Rogers        "MetricName": "tma_mem_scheduler",
498fa607370SIan Rogers        "MetricThreshold": "tma_mem_scheduler > 0.1",
499fa607370SIan Rogers        "ScaleUnit": "100%"
500fa607370SIan Rogers    },
501fa607370SIan Rogers    {
5020372358aSIan Rogers        "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.",
503c04fcf7cSIan Rogers        "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_core_clks + tma_store_bound)",
5040372358aSIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
5050372358aSIan Rogers        "MetricName": "tma_memory_bound",
5060372358aSIan Rogers        "MetricThreshold": "tma_memory_bound > 0.2",
507ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
5080372358aSIan Rogers        "ScaleUnit": "100%"
5090372358aSIan Rogers    },
5100372358aSIan Rogers    {
511fa607370SIan Rogers        "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.",
512fa607370SIan Rogers        "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)",
513fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
514fa607370SIan Rogers        "MetricName": "tma_memory_ordering",
515fa607370SIan Rogers        "MetricThreshold": "tma_memory_ordering > 0.02",
516fa607370SIan Rogers        "ScaleUnit": "100%"
517fa607370SIan Rogers    },
518fa607370SIan Rogers    {
519fa607370SIan Rogers        "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)",
520c04fcf7cSIan Rogers        "MetricExpr": "UOPS_RETIRED.MS / tma_info_core_slots",
521fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group",
522fa607370SIan Rogers        "MetricName": "tma_ms_uops",
523fa607370SIan Rogers        "MetricThreshold": "tma_ms_uops > 0.05",
524ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
525fa607370SIan Rogers        "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
526fa607370SIan Rogers        "ScaleUnit": "100%"
527fa607370SIan Rogers    },
528fa607370SIan Rogers    {
529fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
530c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_core_slots",
531fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
532fa607370SIan Rogers        "MetricName": "tma_non_mem_scheduler",
533fa607370SIan Rogers        "MetricThreshold": "tma_non_mem_scheduler > 0.1",
534fa607370SIan Rogers        "ScaleUnit": "100%"
535fa607370SIan Rogers    },
536fa607370SIan Rogers    {
537fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to a machine clear (slow nuke).",
538c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_core_slots",
539fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
540fa607370SIan Rogers        "MetricName": "tma_nuke",
541fa607370SIan Rogers        "MetricThreshold": "tma_nuke > 0.05",
542fa607370SIan Rogers        "ScaleUnit": "100%"
543fa607370SIan Rogers    },
544fa607370SIan Rogers    {
545fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to other common frontend stalls not categorized.",
546c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_core_slots",
5470372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
548fa607370SIan Rogers        "MetricName": "tma_other_fb",
549fa607370SIan Rogers        "MetricThreshold": "tma_other_fb > 0.05",
550fa607370SIan Rogers        "ScaleUnit": "100%"
551fa607370SIan Rogers    },
552fa607370SIan Rogers    {
553fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.",
554c04fcf7cSIan Rogers        "MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_core_clks",
555fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
556fa607370SIan Rogers        "MetricName": "tma_other_l1",
557fa607370SIan Rogers        "MetricThreshold": "tma_other_l1 > 0.05",
558fa607370SIan Rogers        "ScaleUnit": "100%"
559fa607370SIan Rogers    },
560fa607370SIan Rogers    {
561fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.",
5620372358aSIan Rogers        "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))",
5630372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
564fa607370SIan Rogers        "MetricName": "tma_other_load_store",
565fa607370SIan Rogers        "MetricThreshold": "tma_other_load_store > 0.1",
566fa607370SIan Rogers        "ScaleUnit": "100%"
567fa607370SIan Rogers    },
568fa607370SIan Rogers    {
569fa607370SIan Rogers        "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.",
570c04fcf7cSIan Rogers        "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_core_slots",
571fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group",
572fa607370SIan Rogers        "MetricName": "tma_other_ret",
573fa607370SIan Rogers        "MetricThreshold": "tma_other_ret > 0.3",
574fa607370SIan Rogers        "ScaleUnit": "100%"
575fa607370SIan Rogers    },
576fa607370SIan Rogers    {
577fa607370SIan Rogers        "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.",
578fa607370SIan Rogers        "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)",
579fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
580fa607370SIan Rogers        "MetricName": "tma_page_fault",
581fa607370SIan Rogers        "MetricThreshold": "tma_page_fault > 0.02",
582fa607370SIan Rogers        "ScaleUnit": "100%"
583fa607370SIan Rogers    },
584fa607370SIan Rogers    {
585fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not delivered by the frontend due to wrong predecodes.",
586c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_core_slots",
5870372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
588fa607370SIan Rogers        "MetricName": "tma_predecode",
589fa607370SIan Rogers        "MetricThreshold": "tma_predecode > 0.05",
590fa607370SIan Rogers        "ScaleUnit": "100%"
591fa607370SIan Rogers    },
592fa607370SIan Rogers    {
593fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
594c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_core_slots",
595fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
596fa607370SIan Rogers        "MetricName": "tma_register",
597fa607370SIan Rogers        "MetricThreshold": "tma_register > 0.1",
598fa607370SIan Rogers        "ScaleUnit": "100%"
599fa607370SIan Rogers    },
600fa607370SIan Rogers    {
601fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
602c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_core_slots",
603fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
604fa607370SIan Rogers        "MetricName": "tma_reorder_buffer",
605fa607370SIan Rogers        "MetricThreshold": "tma_reorder_buffer > 0.1",
606fa607370SIan Rogers        "ScaleUnit": "100%"
607fa607370SIan Rogers    },
608fa607370SIan Rogers    {
609fa607370SIan Rogers        "BriefDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls",
610fa607370SIan Rogers        "MetricExpr": "tma_backend_bound",
611fa607370SIan Rogers        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group",
612fa607370SIan Rogers        "MetricName": "tma_resource_bound",
613fa607370SIan Rogers        "MetricThreshold": "tma_resource_bound > 0.2",
614ccc66c60SIan Rogers        "MetricgroupNoGroup": "TopdownL2",
615fa607370SIan Rogers        "PublicDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that uops must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.",
616fa607370SIan Rogers        "ScaleUnit": "100%"
617fa607370SIan Rogers    },
618fa607370SIan Rogers    {
619fa607370SIan Rogers        "BriefDescription": "Counts the numer of issue slots  that result in retirement slots.",
620969a4661SKan Liang        "DefaultMetricgroupName": "TopdownL1",
621c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_core_slots",
622969a4661SKan Liang        "MetricGroup": "Default;TopdownL1;tma_L1_group",
623fa607370SIan Rogers        "MetricName": "tma_retiring",
624fa607370SIan Rogers        "MetricThreshold": "tma_retiring > 0.75",
625969a4661SKan Liang        "MetricgroupNoGroup": "TopdownL1;Default",
626fa607370SIan Rogers        "ScaleUnit": "100%"
627fa607370SIan Rogers    },
628fa607370SIan Rogers    {
629fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative",
630fa607370SIan Rogers        "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL",
631fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
632fa607370SIan Rogers        "MetricName": "tma_rsv",
633fa607370SIan Rogers        "MetricThreshold": "tma_rsv > 0.05",
634fa607370SIan Rogers        "ScaleUnit": "100%"
635fa607370SIan Rogers    },
636fa607370SIan Rogers    {
637fa607370SIan Rogers        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
638c04fcf7cSIan Rogers        "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_core_slots",
639fa607370SIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
640fa607370SIan Rogers        "MetricName": "tma_serialization",
641fa607370SIan Rogers        "MetricThreshold": "tma_serialization > 0.1",
642fa607370SIan Rogers        "ScaleUnit": "100%"
643fa607370SIan Rogers    },
644fa607370SIan Rogers    {
645fa607370SIan Rogers        "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.",
646fa607370SIan Rogers        "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)",
647fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group",
648fa607370SIan Rogers        "MetricName": "tma_smc",
649fa607370SIan Rogers        "MetricThreshold": "tma_smc > 0.02",
650fa607370SIan Rogers        "ScaleUnit": "100%"
651fa607370SIan Rogers    },
652fa607370SIan Rogers    {
653fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full",
654fa607370SIan Rogers        "MetricExpr": "tma_store_bound",
655fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group",
656fa607370SIan Rogers        "MetricName": "tma_st_buffer",
657fa607370SIan Rogers        "MetricThreshold": "tma_st_buffer > 0.05",
658fa607370SIan Rogers        "ScaleUnit": "100%"
659fa607370SIan Rogers    },
660fa607370SIan Rogers    {
661fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.",
662c04fcf7cSIan Rogers        "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_core_clks",
663fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
664fa607370SIan Rogers        "MetricName": "tma_stlb_hit",
665fa607370SIan Rogers        "MetricThreshold": "tma_stlb_hit > 0.05",
666fa607370SIan Rogers        "ScaleUnit": "100%"
667fa607370SIan Rogers    },
668fa607370SIan Rogers    {
669fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.",
670c04fcf7cSIan Rogers        "MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_core_clks",
671fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
672fa607370SIan Rogers        "MetricName": "tma_stlb_miss",
673fa607370SIan Rogers        "MetricThreshold": "tma_stlb_miss > 0.05",
674fa607370SIan Rogers        "ScaleUnit": "100%"
675fa607370SIan Rogers    },
676fa607370SIan Rogers    {
677fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
678fa607370SIan Rogers        "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
6790372358aSIan Rogers        "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group",
680fa607370SIan Rogers        "MetricName": "tma_store_bound",
681fa607370SIan Rogers        "MetricThreshold": "tma_store_bound > 0.1",
682fa607370SIan Rogers        "ScaleUnit": "100%"
683fa607370SIan Rogers    },
684fa607370SIan Rogers    {
685fa607370SIan Rogers        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.",
686*9a7d82c1SIan Rogers        "MetricConstraint": "NO_GROUP_EVENTS_NMI",
687c04fcf7cSIan Rogers        "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_core_clks",
688fa607370SIan Rogers        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
6890372358aSIan Rogers        "MetricName": "tma_store_fwd_blk",
6900372358aSIan Rogers        "MetricThreshold": "tma_store_fwd_blk > 0.05",
6912bb3fbadSZhengjun Xing        "ScaleUnit": "100%"
6922bb3fbadSZhengjun Xing    }
6932bb3fbadSZhengjun Xing]
694