Home
last modified time | relevance | path

Searched full:slc (Results 1 – 25 of 76) sorted by relevance

1234

/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm379 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1
411 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1
458 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
460 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
461 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
462 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
471 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
473 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
474 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
475 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
[all …]
H A Dcwsr_trap_handler_gfx8.asm352 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
353 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
354 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
407 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
450 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
451 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
452 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
547 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
[all …]
H A Dcwsr_trap_handler_gfx9.asm584 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
982 buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
983 buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
984 buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
985 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
989 buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
990 buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
991 buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
992 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
/openbmc/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h89 * SLC: Queue Virtual Window Window for accessing into a specific VF
98 /* SLC: Queue Segment */
102 /* SLC: Queue Offset */
106 /* SLC: Queue Configuration */
110 /* SLC: Job Timout/Only accessible for the PF */
116 /* SLC: Queue InitSequence Register */
120 /* SLC: Queue Wrap */
124 /* SLC: Queue Status */
128 /* SLC: Queue Working Time */
132 /* SLC: Queue Error Counts */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-slc.txt1 NXP LPC32xx SoC NAND SLC controller
4 - compatible: "nxp,lpc3220-slc"
27 slc: flash@20020000 {
28 compatible = "nxp,lpc3220-slc";
/openbmc/openbmc/poky/meta/recipes-extended/slang/slang/
H A Dterminfo_fixes.patch106 + tests="$$tests $$test.slc"; \
122 + if [ ! -e lastrun/$$X.slc ] || [ $$X.sl -nt lastrun/$$X.slc ] ; \
124 + tests="$$tests $$X.slc"; \
152 + $(MEMCHECK) --log-file=log.$${X}_c $(RUN_TEST_PGM) $$X.slc; \
153 + $(MEMCHECK) --log-file=log.$${X}_uc $(RUN_TEST_PGM) -utf8 $$X.slc; \
164 + -/bin/rm -f *~ *.o *.log log.pid* *.slc log.* *.log-*
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dphy3250.c21 .bus_id = "nand-slc",
22 .min_signal = 1, /* SLC NAND Flash */
65 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c3 * LPC32xx SLC NAND flash controller driver
96 * Helper macro for the DMA client (i.e. NAND SLC):
114 /* Reset SLC NAND controller */ in lpc32xx_nand_init()
299 /* Setup SLC controller and start transfer */ in lpc32xx_nand_xfer()
355 * Enables and prepares SLC NAND controller
363 /* Setup SLC controller for H/W ECC operations */ in lpc32xx_hwecc_enable()
425 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction in lpc32xx_read_page_hwecc()
462 * and section 9.7, the NAND SLC & DMA allowed single DMA transaction in lpc32xx_write_page_hwecc()
503 * LPC32xx has only one SLC NAND controller, don't utilize
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_toshiba.c158 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per in toshiba_nand_decode_id()
159 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as in toshiba_nand_decode_id()
163 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC in toshiba_nand_decode_id()
174 * For Toshiba SLC, ecc requrements are as follows: in toshiba_nand_decode_id()
H A Dlpc32xx_slc.c3 * NXP LPC32XX NAND SLC driver
33 * SLC NAND controller register offsets
73 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
240 /* Reset SLC controller */ in lpc32xx_nand_setup()
250 /* Get base clock for SLC block */ in lpc32xx_nand_setup()
325 * Prepares SLC for transfers with H/W ECC enabled
732 "nand-slc"); in lpc32xx_nand_dma_setup()
893 /* NAND callbacks for LPC32xx SLC hardware */ in lpc32xx_nand_probe()
1002 { .compatible = "nxp,lpc3220-slc" },
1023 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
H A Dnand_esmt.c45 * It is known that some ESMT SLC NANDs have been shipped in esmt_nand_init()
/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dpartition.yaml49 slc-mode:
50 description: This parameter, if present, allows one to emulate SLC mode
/openbmc/u-boot/arch/arc/lib/
H A Dstart.S53 ; Disable System-Level Cache (SLC)
55 breq r5, 0, 1f ; SLC doesn't exist
H A Dcache.c382 panic("Try to enable IOC but SLC is not present"); in arc_ioc_setup()
424 panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent"); in read_decode_cache_bcr_arcv2()
519 * TODO: HS 3.0 supports SLC disable so we need to check slc in invalidate_icache_all()
548 * As SLC will be bypassed for data after L1 D$ disable we need to in dcache_disable()
549 * flush it first before L1 D$ disable. Also we invalidate SLC to in dcache_disable()
/openbmc/linux/drivers/mtd/parsers/
H A Dcmdlinepart.c12 * <partdef> := <size>[@<offset>][<name>][ro][lk][slc]
156 /* if slc is found use emulated SLC mode on this partition*/ in newpart()
157 if (!strncmp(s, "slc", 3)) { in newpart()
/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_reqmgr.c474 sr->instr.slc.value[0] = 0; in nitrox_process_se_request()
475 sr->instr.slc.s.ssz = sr->out.sgmap_cnt; in nitrox_process_se_request()
476 sr->instr.slc.bev[0] = cpu_to_be64(sr->instr.slc.value[0]); in nitrox_process_se_request()
479 sr->instr.slc.s.rptr = cpu_to_be64(sr->out.sgcomp_dma); in nitrox_process_se_request()
H A Dnitrox_hal.c168 /* step 1: disable slc port */ in reset_pkt_solicit_port()
184 /* step 3: clear slc counters */ in reset_pkt_solicit_port()
285 * This includes NPS packet in and slc interrupts.
293 /* NPS packet slc port interrupts */ in enable_nps_pkt_interrupts()
/openbmc/linux/include/linux/mtd/
H A Dlpc32xx_slc.h3 * Platform data for LPC32xx SoC SLC NAND controller
H A Donenand_regs.h102 /* Note: It's actually 0x3f in case of SLC */
115 /* Note: It's actually 0x03 in case of SLC */
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts149 /* 64MB Flash via SLC NAND controller */
150 &slc {
H A Dlpc3250-ea3250.dts215 /* 128MB Flash via SLC NAND controller */
216 &slc {
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dll_cache.json4 …ose transactions are either hit in the system level cache or missed in the SLC and are returned fr…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dll_cache.json4 …ose transactions are either hit in the system level cache or missed in the SLC and are returned fr…
/openbmc/u-boot/arch/arc/include/asm/
H A Dcache.h15 * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
/openbmc/linux/arch/arc/mm/
H A Dcache.c58 "SLC\t\t: %uK, %uB Line%s\n", in read_decode_cache_bcr_arcv2()
551 * SLC is shared between all cores and concurrent aux operations from in slc_op_rgn()
614 * SLC is shared between all cores and concurrent aux operations from in slc_op_line()
1042 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
1069 /* Flush + invalidate SLC */ in arc_ioc_setup()
1167 /* Note that SLC disable not formally supported till HS 3.0 */ in arc_cache_init_master()
1184 * In case of IOC (say IOC+SLC case), pointers above could still be set in arc_cache_init_master()

1234