| /openbmc/u-boot/board/freescale/m54418twr/ |
| H A D | m54418twr.c | 38 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
57 out_be32(&sdram->rcrcr, 0x40000000); in dram_init()
58 out_be32(&sdram->padcr, 0x01030203); in dram_init()
60 out_be32(&sdram->cr00, 0x01010101); in dram_init()
61 out_be32(&sdram->cr01, 0x00000101); in dram_init()
62 out_be32(&sdram->cr02, 0x01010100); in dram_init()
63 out_be32(&sdram->cr03, 0x01010000); in dram_init()
64 out_be32(&sdram->cr04, 0x00010101); in dram_init()
65 out_be32(&sdram->cr06, 0x00010100); in dram_init()
66 out_be32(&sdram->cr07, 0x00000001); in dram_init()
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/memory-controllers/ |
| H A D | st,stm32-fmc.txt | 8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
45 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
51 /* sdram memory configuration from sdram datasheet */
53 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
|
| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_axp_mc_static.h | 11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
28 {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
[all …]
|
| /openbmc/u-boot/include/ |
| H A D | fsl_immap.h | 33 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
34 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
35 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
36 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
37 u32 sdram_cfg; /* SDRAM Control Configuration */
38 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
39 u32 sdram_mode; /* SDRAM Mode Configuration */
40 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
41 u32 sdram_md_cntl; /* SDRAM Mode Control */
42 u32 sdram_interval; /* SDRAM Interval Configuration */
[all …]
|
| H A D | spd.h | 7 * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
24 unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */
25 unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */
28 unsigned char primw; /* 13 Primary SDRAM Width */
29 unsigned char ecw; /* 14 Error Checking SDRAM width */
32 unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
36 unsigned char mod_attr; /* 21 SDRAM Module Attributes */
37 unsigned char dev_attr; /* 22 SDRAM Device Attributes */
38 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
39 unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
[all …]
|
| /openbmc/u-boot/board/freescale/m5329evb/ |
| H A D | m5329evb.c | 26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
38 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
39 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
42 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
45 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m5373evb/ |
| H A D | m5373evb.c | 26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
38 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
39 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
42 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
45 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m5208evbe/ |
| H A D | m5208evbe.c | 26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
47 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
58 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m53017evb/ |
| H A D | m53017evb.c | 26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
47 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
58 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m54451evb/ |
| H A D | m54451evb.c | 38 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
44 if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && in dram_init()
45 (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) in dram_init()
56 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
58 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
59 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
64 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
68 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m52277evb/ |
| H A D | m52277evb.c | 34 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
48 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
50 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
51 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
54 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
58 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
60 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); in dram_init()
66 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m547xevb/ |
| H A D | m547xevb.c | 28 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
|
| /openbmc/u-boot/board/freescale/m548xevb/ |
| H A D | m548xevb.c | 28 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
|
| /openbmc/u-boot/drivers/ram/ |
| H A D | Kconfig | 5 This allows drivers to be provided for SDRAM and other RAM
18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
30 bool "Enable STM32 SDRAM support"
34 support external memories like sdram, psram & nand.
35 This driver is for the sdram memory interface with the FMC.
38 bool "Enable MPC83XX SDRAM support"
53 provides an interface to external SDRAM devices. Enabling this
55 SDRAM devices connected to DDR subsystem.
|
| /openbmc/u-boot/drivers/ddr/altera/ |
| H A D | sdram_gen5.c | 10 #include <asm/arch/sdram.h>
15 u32 sdram_start; /* SDRAM start address */
16 u32 sdram_end; /* SDRAM end address */
17 u32 rule; /* SDRAM protection rule number: 0-19 */
34 * @cfg: SDRAM controller configuration data
36 * SDRAM Failure happens when accessing non-existent memory. Artificially
42 /* Define constant for 4G memory - used for SDRAM errata workaround */ in get_errata_rows()
85 printf("SDRAM workaround failed, bits set %d\n", bits); in get_errata_rows()
90 printf("SDRAM workaround rangecheck failed, %lld\n", newrows); in get_errata_rows()
99 printf("SDRAM workaround failed, newrows %lld\n", newrows); in get_errata_rows()
[all …]
|
| /openbmc/u-boot/board/freescale/m5235evb/ |
| H A D | m5235evb.c | 26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
32 * the port-size of SDRAM. In this case it is necessary to enable in dram_init()
39 /* Initialize PAR to enable SDRAM signals */ in dram_init()
52 if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { in dram_init()
56 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
61 out_be32(&sdram->dacr0, in dram_init()
68 out_be32(&sdram->dmr0, in dram_init()
73 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); in dram_init()
84 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); in dram_init()
92 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); in dram_init()
[all …]
|
| /openbmc/u-boot/arch/arm/mach-orion5x/ |
| H A D | lowlevel_init.S | 14 * Configuration values for SDRAM access setup
86 /*DDR SDRAM Initialization Control */
107 /* 1) Configure SDRAM */
111 /* 2) Set SDRAM Control reg */
115 /* 3) Write SDRAM address control register */
119 /* 4) Write SDRAM bank 0 size register */
124 /* 5) Write SDRAM open pages control register */
128 /* 6) Write SDRAM timing Low register */
132 /* 7) Write SDRAM timing High register */
136 /* 8) Write SDRAM mode register */
[all …]
|
| /openbmc/u-boot/board/Synology/ds109/ |
| H A D | openocd.cfg | 44 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
48 mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
49 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
50 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
51 mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
52 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
[all …]
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Dimm.interface.yaml | 163 - name: SDRAM
174 Double Data Rate SDRAM.
177 Double Data Rate 2 SDRAM.
180 DDR2 SDRAM Fully Buffered DIMM.
192 Double Data Rate 3 SDRAM.
198 Double Data Rate 4 SDRAM.
201 Low-Power Double Data Rate SDRAM.
204 Low-Power Double Data Rate 2 SDRAM.
207 Low-Power Double Data Rate 3 SDRAM.
210 Low-Power Double Data Rate 4 SDRAM.
[all …]
|
| /openbmc/u-boot/board/renesas/sh7785lcr/ |
| H A D | README.sh7785lcr | 11 - DDR2-SDRAM 512MB
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
[all …]
|
| /openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/ |
| H A D | lowlevel_init.S | 20 /* Configure the SDRAM based on the supplied settings.
22 * Input: r0 - SDRAM DEVCFG register
23 * r2 - configuration for SDRAM chips
28 /* Program the SDRAM device configuration register. */
68 /* Delay for at least 80 SDRAM clock cycles. */
85 /* Program the mode register on the SDRAM by performing fake read */
96 * Test to see if the SDRAM has been configured in a usable mode.
98 * Input: r0 - Test address of SDRAM
103 /* Load the test patterns to be written to SDRAM. */
109 /* Store the test patterns to SDRAM. */
[all …]
|
| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9_sdramc.h | 9 * SDRAM Controllers (SDRAMC) - System peripherals registers.
44 /* SDRAM Controller (SDRAMC) registers */
45 #define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
55 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
58 #define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
91 #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
105 #define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
106 #define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register …
107 #define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
108 #define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
[all …]
|
| /openbmc/u-boot/board/freescale/m54455evb/ |
| H A D | m54455evb.c | 34 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
48 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
49 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); in dram_init()
51 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
52 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
55 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
58 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); in dram_init()
59 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); in dram_init()
64 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
|
| /openbmc/u-boot/include/configs/ |
| H A D | edb93xx.h | 98 /* SDRAM configuration */
103 * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
104 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
107 * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
109 * 64 MB of SDRAM.
117 * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
118 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
121 * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
122 * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
|
| /openbmc/u-boot/board/alliedtelesis/SBx81LIFKW/ |
| H A D | kwbimage.cfg | 35 DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
36 DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
38 DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
39 DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
40 DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
|