marvell/axp/ddr3_axp_mc_static.h

11 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
13 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
16 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
17 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
21 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
23 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
26 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
27 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
28 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
38 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
39 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
69 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
71 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
74 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
75 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
76 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
79 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
81 	{0x00001410, 0x040F000C},	/*DDR SDRAM Open Pages Control Register */
84 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
85 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
86 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
96 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
97 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
127 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
129 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
132 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
133 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
134 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
135 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
136 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
137 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
138 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
144 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
145 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
179 	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
181 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
184 	{0x00001408, 0x44149887},	/*DDR SDRAM Timing (Low) Register */
185 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
186 	{0x0000140C, 0x38D83FE0},	/*DDR SDRAM Timing (High) Register */
189 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
191 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
194 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
195 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
196 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
205 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
206 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
236 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
238 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
239 	/*{0x00001400, 0x7304CC30},  *//*DDR SDRAM Configuration Register */
242 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
243 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
244 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
245 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
246 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
247 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
248 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
254 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
255 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */