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/openbmc/linux/drivers/dma/
H A Dimx-sdma.c3 // drivers/dma/imx-sdma.c
46 /* SDMA registers */
104 * Error bit set in the CCB status field by the SDMA,
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
193 * struct sdma_script_start_addrs - SDMA script start pointers
196 * address space of the SDMA engine.
275 * @unused: padding. The SDMA engine expects an array of 128 byte
285 * struct sdma_state_registers - SDMA context for a channel
314 * struct sdma_context_data - sdma context specific to a channel
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_rxtx.c102 /* protect SDMA with concurrent access from multiple CPUs */
107 struct prestera_sdma sdma; member
110 static int prestera_sdma_buf_init(struct prestera_sdma *sdma, in prestera_sdma_buf_init() argument
116 desc = dma_pool_alloc(sdma->desc_pool, GFP_DMA | GFP_KERNEL, &dma); in prestera_sdma_buf_init()
128 static u32 prestera_sdma_map(struct prestera_sdma *sdma, dma_addr_t pa) in prestera_sdma_map() argument
130 return sdma->map_addr + pa; in prestera_sdma_map()
133 static void prestera_sdma_rx_desc_init(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_init() argument
142 desc->buff = cpu_to_le32(prestera_sdma_map(sdma, buf)); in prestera_sdma_rx_desc_init()
150 static void prestera_sdma_rx_desc_set_next(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_set_next() argument
154 desc->next = cpu_to_le32(prestera_sdma_map(sdma, next)); in prestera_sdma_rx_desc_set_next()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,imx-sdma.yaml4 $id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
7 title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
20 - fsl,imx50-sdma
21 - fsl,imx51-sdma
22 - fsl,imx53-sdma
23 - fsl,imx6q-sdma
24 - fsl,imx7d-sdma
25 - const: fsl,imx35-sdma
28 - fsl,imx6sx-sdma
29 - fsl,imx6sl-sdma
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_sdma.c30 /* SDMA CSA reside in the 3rd page of CSA */
34 * GPU SDMA IP block helpers function.
42 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
43 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_instance_from_ring()
44 ring == &adev->sdma.instance[i].page) in amdgpu_sdma_get_instance_from_ring()
45 return &adev->sdma.instance[i]; in amdgpu_sdma_get_instance_from_ring()
55 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
56 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_index_from_ring()
57 ring == &adev->sdma.instance[i].page) { in amdgpu_sdma_get_index_from_ring()
74 /* don't enable OS preemption on SDMA under SRIOV */ in amdgpu_sdma_get_csa_mc_addr()
[all …]
H A Dsdma_v4_4_2.c34 #include "sdma/sdma_4_4_2_offset.h"
35 #include "sdma/sdma_4_4_2_sh_mask.h"
105 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
134 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
288 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_4_2_ring_insert_nop() local
292 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_4_2_ring_insert_nop()
369 << (ring->me % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_ring_emit_hdp_flush()
429 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; in sdma_v4_4_2_inst_gfx_stop() local
434 sdma[i] = &adev->sdma.instance[i].ring; in sdma_v4_4_2_inst_gfx_stop()
436 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { in sdma_v4_4_2_inst_gfx_stop()
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H A Dsdma_v4_0.c555 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
580 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
584 for every SDMA instance */ in sdma_v4_0_init_microcode()
737 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_0_ring_insert_nop() local
741 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_0_ring_insert_nop()
870 * @enable: enable SDMA RB/IB
880 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_enable()
916 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
965 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
977 * Enable SDMA utilization. Its only supported on in sdma_v4_0_ctx_switch_enable()
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H A Dsdma_v3_0.c182 * sDMA - System DMA
190 * (ring buffer, IBs, etc.), but sDMA has it's own
192 * used by the CP. sDMA supports copying data, writing
254 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v3_0_free_microcode()
255 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in sdma_v3_0_free_microcode()
306 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_init_microcode()
311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); in sdma_v3_0_init_microcode()
314 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v3_0_init_microcode()
315 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v3_0_init_microcode()
316 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v3_0_init_microcode()
[all …]
H A Dcik_sdma.c77 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_free_microcode()
78 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in cik_sdma_free_microcode()
82 * sDMA - System DMA
90 * (ring buffer, IBs, etc.), but sDMA has it's own
92 * used by the CP. sDMA supports copying data, writing
134 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
139 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); in cik_sdma_init_microcode()
146 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_init_microcode()
147 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in cik_sdma_init_microcode()
199 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in cik_sdma_ring_insert_nop() local
[all …]
H A Dsdma_v2_4.c81 * sDMA - System DMA
89 * (ring buffer, IBs, etc.), but sDMA has it's own
91 * used by the CP. sDMA supports copying data, writing
117 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_free_microcode()
118 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in sdma_v2_4_free_microcode()
148 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
153 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); in sdma_v2_4_init_microcode()
156 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v2_4_init_microcode()
157 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v2_4_init_microcode()
158 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v2_4_init_microcode()
[all …]
H A Dsdma_v5_2.c191 /* SDMA seems to miss doorbells sometimes when powergating kicks in. in sdma_v5_2_ring_set_wptr()
216 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_insert_nop() local
220 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_insert_nop()
381 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_stop()
440 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
479 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
507 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
508 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume()
662 * sdma_v5_2_load_microcode - load the sDMA ME ucode
679 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
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H A Dsdma_v6_0.c226 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v6_0_ring_insert_nop() local
230 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v6_0_ring_insert_nop()
386 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
422 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
452 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
478 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
479 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_gfx_resume()
548 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v6_0_gfx_resume()
619 * sdma_v6_0_load_microcode - load the sDMA ME ucode
637 if (!adev->sdma.instance[0].fw) in sdma_v6_0_load_microcode()
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H A Dsi_dma.c49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_get_wptr()
57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_set_wptr()
120 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
135 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
136 ring = &adev->sdma.instance[i].ring; in si_dma_start()
353 * si_dma_vm_set_pte_pde - update the page tables using sDMA
362 * Update the page tables using sDMA (CIK).
434 * si_dma_ring_emit_vm_flush - cik vm flush using sDMA
441 * using sDMA (VI).
469 adev->sdma.num_instances = 2; in si_dma_early_init()
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H A Dsdma_v5_0.c243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
401 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
405 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
564 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
623 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
665 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
692 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
693 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume()
850 * sdma_v5_0_load_microcode - load the sDMA ME ucode
867 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
[all …]
H A Dsdma_v4_4.c24 #include "sdma/sdma_4_4_0_offset.h"
25 #include "sdma/sdma_4_4_0_sh_mask.h"
35 * to calculate register offset for all the sdma instances */
180 /* the SDMA_EDC_COUNTER register in each sdma instance in sdma_v4_4_get_ras_error_count()
187 dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n", in sdma_v4_4_get_ras_error_count()
222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
241 /* write 0 to EDC_COUNTER reg to clear sdma edc counters */ in sdma_v4_4_reset_ras_error_count()
243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap3.dtsi164 dmas = <&sdma 65 &sdma 66>;
208 sdma: dma-controller@48056000 { label
209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
292 dmas = <&sdma 49 &sdma 50>;
302 dmas = <&sdma 51 &sdma 52>;
312 dmas = <&sdma 53 &sdma 54>;
322 dmas = <&sdma 27 &sdma 28>;
333 dmas = <&sdma 29 &sdma 30>;
344 dmas = <&sdma 25 &sdma 26>;
373 dmas = <&sdma 35>,
[all …]
H A Dimx6sll.dtsi197 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
221 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
233 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
245 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
257 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
269 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
281 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
293 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
305 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
318 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
[all …]
H A Dimx6ull.dtsi230 dmas = <&sdma 41 18 0>,
231 <&sdma 42 18 0>;
257 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
271 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
285 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
299 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
312 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
339 dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
356 dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
371 dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
[all …]
H A Dimx6qdl.dtsi304 dmas = <&sdma 14 18 0>,
305 <&sdma 15 18 0>;
329 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
343 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
357 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
371 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
383 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
399 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
413 dmas = <&sdma 37 1 0>,
414 <&sdma 38 1 0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi62 dmas = <&sdma 9 &sdma 10>;
100 sdma: dma-controller@0 { label
101 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
136 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
137 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
147 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
163 dmas = <&sdma 13>;
172 dmas = <&sdma 49 &sdma 50>;
182 dmas = <&sdma 51 &sdma 52>;
192 dmas = <&sdma 53 &sdma 54>;
H A Domap2430.dtsi186 dmas = <&sdma 31>,
187 <&sdma 32>;
202 dmas = <&sdma 33>,
203 <&sdma 34>;
218 dmas = <&sdma 17>,
219 <&sdma 18>;
234 dmas = <&sdma 19>,
235 <&sdma 20>;
250 dmas = <&sdma 21>,
251 <&sdma 22>;
[all …]
H A Domap3.dtsi181 dmas = <&sdma 9 &sdma 10>;
207 dmas = <&sdma 65 &sdma 66>;
289 sdma: dma-controller@0 { label
290 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
373 dmas = <&sdma 49 &sdma 50>;
383 dmas = <&sdma 51 &sdma 52>;
393 dmas = <&sdma 53 &sdma 54>;
448 dmas = <&sdma 35>,
449 <&sdma 36>,
450 <&sdma 37>,
[all …]
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dvnic_sdma.c7 * This file contains HFI1 support for VNIC SDMA functionality
10 #include "sdma.h"
21 * @txreq: sdma transmit request
22 * @sdma: vnic sdma pointer
30 struct hfi1_vnic_sdma *sdma; member
42 struct hfi1_vnic_sdma *vnic_sdma = tx->sdma; in vnic_sdma_complete()
130 struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx]; in hfi1_vnic_send_dma()
147 tx->sdma = vnic_sdma; in hfi1_vnic_send_dma()
157 /* When -ECOMM, sdma callback will be called with ABORT status */ in hfi1_vnic_send_dma()
179 * hfi1_vnic_sdma_sleep - vnic sdma sleep function
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H A Dvnic.h10 #include "sdma.h"
33 * struct hfi1_vnic_sdma - VNIC per Tx ring SDMA information
35 * @sde - sdma engine
38 * @stx - sdma tx request
39 * @state - vnic Tx ring SDMA state
79 * @sdma: VNIC SDMA structure per TXQ
95 struct hfi1_vnic_sdma sdma[HFI1_VNIC_MAX_TXQ]; member
/openbmc/linux/arch/powerpc/include/asm/
H A Dmpc52xx.h76 /* SDMA */
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi160 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
184 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
196 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
208 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
220 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
233 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
246 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
259 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
271 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
284 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
[all …]

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