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/openbmc/linux/drivers/fsi/
H A Dfsi-scom.c3 * SCOM FSI Client device driver
22 /* SCOM engine register set */
47 /* SCOM address encodings */
51 /* SCOM indirect stuff */
145 static int put_indirect_scom_form0(struct scom_device *scom, uint64_t value, in put_indirect_scom_form0() argument
156 rc = __put_scom(scom, ind_data, ind_addr, status); in put_indirect_scom_form0()
160 rc = __get_scom(scom, &ind_data, addr, status); in put_indirect_scom_form0()
170 static int put_indirect_scom_form1(struct scom_device *scom, uint64_t value, in put_indirect_scom_form1() argument
180 return __put_scom(scom, ind_data, ind_addr, status); in put_indirect_scom_form1()
183 static int get_indirect_scom_form0(struct scom_device *scom, uint64_t *value, in get_indirect_scom_form0() argument
[all …]
H A Di2cr-scom.c37 struct i2cr_scom *scom = filep->private_data; in i2cr_scom_read() local
44 ret = fsi_master_i2cr_read(scom->i2cr, (u32)*offset, &data); in i2cr_scom_read()
58 struct i2cr_scom *scom = filep->private_data; in i2cr_scom_write() local
69 ret = fsi_master_i2cr_write(scom->i2cr, (u32)*offset, data); in i2cr_scom_write()
87 struct i2cr_scom *scom; in i2cr_scom_probe() local
94 scom = devm_kzalloc(dev, sizeof(*scom), GFP_KERNEL); in i2cr_scom_probe()
95 if (!scom) in i2cr_scom_probe()
98 scom->i2cr = to_fsi_master_i2cr(fsi_dev->slave->master); in i2cr_scom_probe()
99 dev_set_drvdata(dev, scom); in i2cr_scom_probe()
101 scom->dev.type = &fsi_cdev_type; in i2cr_scom_probe()
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H A DKconfig71 that translates I2C commands to CFAM or SCOM operations, effectively
75 tristate "SCOM FSI client device driver"
77 This option enables an FSI based SCOM device driver.
98 tristate "IBM I2C Responder SCOM driver"
101 This option enables an I2C Responder based SCOM device driver. The
102 I2CR has the capability to directly perform SCOM operations instead
H A DMakefile9 obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
12 obj-$(CONFIG_I2CR_SCOM) += i2cr-scom.o
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dopal-prd.c273 struct opal_prd_scom scom; in opal_prd_ioctl() local
286 rc = copy_from_user(&scom, (void __user *)param, sizeof(scom)); in opal_prd_ioctl()
290 scom.rc = opal_xscom_read(scom.chip, scom.addr, in opal_prd_ioctl()
291 (__be64 *)&scom.data); in opal_prd_ioctl()
292 scom.data = be64_to_cpu(scom.data); in opal_prd_ioctl()
294 scom.chip, scom.addr, scom.data, scom.rc); in opal_prd_ioctl()
296 rc = copy_to_user((void __user *)param, &scom, sizeof(scom)); in opal_prd_ioctl()
302 rc = copy_from_user(&scom, (void __user *)param, sizeof(scom)); in opal_prd_ioctl()
306 scom.rc = opal_xscom_write(scom.chip, scom.addr, scom.data); in opal_prd_ioctl()
308 scom.chip, scom.addr, scom.data, scom.rc); in opal_prd_ioctl()
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H A Dopal-xscom.c3 * PowerNV SCOM bus debugfs interface
197 root = debugfs_create_dir("scom", arch_debugfs_dir); in scom_debug_init()
202 for_each_node_with_property(dn, "scom-controller") { in scom_debug_init()
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power10-quad.dtsi19 scom100: scom@1000 {
20 compatible = "ibm,i2cr-scom";
47 scom101: scom@1000 {
48 compatible = "ibm,i2cr-scom";
75 scom110: scom@1000 {
76 compatible = "ibm,i2cr-scom";
103 scom111: scom@1000 {
104 compatible = "ibm,i2cr-scom";
131 scom112: scom@1000 {
132 compatible = "ibm,i2cr-scom";
[all …]
H A Dibm-power11-quad.dtsi137 scom@1000 {
138 compatible = "ibm,p9-scom";
165 scom100: scom@1000 {
166 compatible = "ibm,i2cr-scom";
195 scom101: scom@1000 {
196 compatible = "ibm,i2cr-scom";
225 scom110: scom@1000 {
226 compatible = "ibm,i2cr-scom";
255 scom111: scom@1000 {
256 compatible = "ibm,i2cr-scom";
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H A Daspeed-bmc-ibm-fuji.dts2507 scom@1000 {
2508 compatible = "ibm,p9-scom";
2535 scom500: scom@1000 {
2536 compatible = "ibm,i2cr-scom";
2565 scom501: scom@1000 {
2566 compatible = "ibm,i2cr-scom";
2595 scom510: scom@1000 {
2596 compatible = "ibm,i2cr-scom";
2625 scom511: scom@1000 {
2626 compatible = "ibm,i2cr-scom";
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H A Daspeed-bmc-ibm-everest.dts2569 scom@1000 {
2597 scom500: scom@1000 {
2598 compatible = "ibm,i2cr-scom";
2629 scom501: scom@1000 {
2630 compatible = "ibm,i2cr-scom";
2661 scom510: scom@1000 {
2662 compatible = "ibm,i2cr-scom";
2693 scom511: scom@1000 {
2694 compatible = "ibm,i2cr-scom";
2725 scom512: scom@1000 {
[all …]
H A Dibm-power9-dual.dtsi11 scom@1000 {
112 scom@1000 {
/openbmc/openpower-sbe-interface/
H A Dsbe_interfaces.hpp9 namespace scom namespace
13 * @brief Read processor SCOM register.
18 * @param[in] SCOM register address.
24 * @brief Write processor SCOM register.
29 * @param[in] SCOM register address.
34 } // namespace scom
H A Dsbe_interfaces.cpp31 namespace scom namespace
34 // Constants specific to SCOM operations
41 // Reading SCOM Registers
52 // Build SCOM read request command. in read()
80 // Build SCOM write request command in write()
101 } // namespace scom
/openbmc/openpower-hw-diags/test/
H A Dsim-hw-access.hpp34 /** The SCOM values for each chip and address. */
37 /** All addresses that will return a SCOM error. */
42 * @brief Stores a SCOM register value, which can be accessed later in test.
44 * @param i_addr A SCOM address on the given chip.
55 * @brief This can be used to specify if a specific SCOM address will return
58 * @param i_addr A SCOM address on the given chip.
68 * @brief Clears all SCOM value/error data.
77 * @brief Returns the stored SCOM register value.
79 * @param i_addr A SCOM address on the given chip.
83 * Otherwise, will return 0 for a successful SCOM access.
H A Dtest-tod-step-check-fault.cpp26 sim::ScomAccess& scom = sim::ScomAccess::getSingleton(); in TEST() local
27 scom.flush(); in TEST()
30 scom.add(proc0, 0x00040030, 0x0002000000000000); // TOD_ERROR in TEST()
36 scom.add(proc0, 0x00040008, 0x0006000000000000); in TEST()
40 scom.add(proc1, 0x00040030, 0x0000440000000000); // TOD_ERROR in TEST()
44 scom.add(proc1, 0x00040008, 0x0001000000000000); in TEST()
47 scom.add(proc1, 0x00040002, 0x2000000000000000); in TEST()
H A Dtest-pdbg-dts.cpp178 sim::ScomAccess& scom = sim::ScomAccess::getSingleton(); in TEST() local
179 scom.flush(); in TEST()
180 scom.add(procChip, 0x11111111, 0x0011223344556677); in TEST()
181 scom.error(ocmbChip, 0x22222222); in TEST()
196 // Test SCOM error. in TEST()
259 sim::ScomAccess& scom = sim::ScomAccess::getSingleton(); in TEST()
260 scom.flush(); in TEST()
264 scom.add(proc0, 0x0C010D03, 0x0f00000000000000); in TEST()
268 scom.add(proc0, 0x0D010D03, 0xA500000000000000); in TEST()
272 scom.add(proc1, 0x0F010D43, 0xf000000000000000); in TEST()
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/openbmc/linux/include/uapi/linux/
H A Dfsi.h9 * /dev/scom "raw" ioctl interface
18 /* Structure for SCOM read/write */
20 __u64 addr; /* SCOM address, supports indirect */
21 __u64 data; /* SCOM data (in for write, out for read) */
45 /* Flags for SCOM check */
49 /* Flags for SCOM reset */
/openbmc/openpower-hw-diags/analyzer/
H A Dhei_user_interface.cpp25 str = "SCOM"; in __regType()
45 // The processor PIB target is required for SCOM access. in __readProc()
52 // Read the 64-bit SCOM register. in __readProc()
73 // The OCMB target is used for SCOM access. in __readOcmb()
80 // Read the 64-bit SCOM register. in __readOcmb()
/openbmc/qemu/hw/ppc/
H A Dpnv_chiptod.c235 * skiboot uses Core ID for P9, though SCOM should work too. in chiptod_power9_tx_ttype_target()
237 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power9_tx_ttype_target()
242 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power9_tx_ttype_target()
259 * skiboot uses SCOM for P10 because Core ID was unable to be made to in chiptod_power10_tx_ttype_target()
260 * work correctly. For this reason only SCOM addressing is implemented. in chiptod_power10_tx_ttype_target()
262 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power10_tx_ttype_target()
267 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power10_tx_ttype_target()
312 * should be used. ChipTOD has a "SCOM addressing" mode which fully in pnv_chiptod_xscom_write()
313 * specifies the SCOM address, and a core-ID mode which uses the in pnv_chiptod_xscom_write()
351 * XXX: it should be a cleaner model to have this drive a SCOM in pnv_chiptod_xscom_write()
H A Dpnv_n1_chiplet.c129 "xscom-n1-chiplet-pb-scom-eq", in pnv_n1_chiplet_realize()
135 "xscom-n1-chiplet-pb-scom-es", in pnv_n1_chiplet_realize()
H A Dpnv_nest_pervasive.c18 * by the pervasive subsystem, which connects registers to the SCOM bus,
32 * scom registers.
/openbmc/linux/arch/powerpc/kernel/
H A Dmisc_64.S179 * SCOM access functions for 970 (FX only for now)
195 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
202 /* do the actual scom read */
213 * the scom on any of the bogus CPUs yet, but may have to be done
229 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
/openbmc/openpower-hw-diags/attn/
H A Dattn_common.cpp43 // Get SCOM regs next (just 2 of them) in addHbStatusRegs()
46 trace::err("scom read error: 0x%016" PRIx64 "", l_scomAddr1); in addHbStatusRegs()
52 trace::err("scom read error: 0x%016" PRIx64 "", l_scomAddr2); in addHbStatusRegs()
/openbmc/linux/drivers/cpufreq/
H A Dmaple-cpufreq.c32 #define SCOM_PCR 0x0aa001 /* PCR scom addr */
47 #define SCOM_PSR 0x408001 /* PSR scom addr */
75 * SCOM based frequency switching for 970FX rev3
/openbmc/openpower-hw-diags/util/
H A Dpdbg-no-sim.cpp66 throw std::logic_error("Invalid type for SCOM operation: target=" + in getScom()
73 "SCOM read failure: target={SCOM_TARGET} addr={SCOM_ADDRESS}", in getScom()

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