| /openbmc/linux/Documentation/riscv/ |
| H A D | patch-acceptance.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 ---------
22 RISC-V has a patchwork instance, where the status of patches can be checked:
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| H A D | boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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| H A D | hwprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
24 be only be valid if all CPUs in the given set have the same value. Otherwise -1
25 will be returned. For boolean-like keys, the value returned will be a logical
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| H A D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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| H A D | boot-image-header.rst | 2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
10 The following 64-byte header is present in decompressed Linux kernel image::
25 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
31 - This header is also reused to support EFI stub for RISC-V. EFI specification
37 - version field indicate header version number
47 - The "magic" field is deprecated as of version 0.2. In a future
52 - In current header, the flags field has only one field.
58 - Image size is mandatory for boot loader to load kernel image. Booting will
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| /openbmc/u-boot/doc/ |
| H A D | README.ae350 | 5 base on RISC-V architecture.
10 AX25-AE350
13 AX25-AE350 is the SoC with AE350 hardcore CPU.
19 If you want to boot this system from SPI ROM and bypass e-bios (the
21 in "include/configs/ax25-ae350.h".
28 2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for 32 or 64 bit.
45 1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
46 2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
48 4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
49 5. Burn this u-boot image to spi rom by spi driver
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| H A D | README.qemu-riscv | 1 # SPDX-License-Identifier: GPL-2.0+
5 U-Boot on QEMU's 'virt' machine on RISC-V
8 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
9 virtualization purposes. This document describes how to run U-Boot under it.
10 Both 32-bit 64-bit targets are supported.
12 The QEMU virt machine models a generic RISC-V virtual machine with support for
14 16550A UART devices in addition to VirtIO and it also uses device-tree to pass
15 configuration information to guest software. It implements RISC-V privileged
18 Building U-Boot
19 ---------------
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| /openbmc/qemu/docs/system/ |
| H A D | target-riscv.rst | 1 .. _RISC-V-System-emulator:
3 RISC-V System emulator
6 QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the
7 ``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine,
8 ``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine.
10 QEMU has generally good support for RISC-V guests. It has support for
12 RISC-V hardware is much more widely varying than x86 hardware. RISC-V
13 CPUs are generally built into "system-on-chip" (SoC) designs created by
23 ----------------------
25 For QEMU's RISC-V system emulation, you must specify which board
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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| /openbmc/linux/Documentation/translations/it_IT/riscv/ |
| H A D | patch-acceptance.rst | 1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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| /openbmc/qemu/docs/specs/ |
| H A D | riscv-iommu.rst | 1 .. _riscv-iommu:
3 RISC-V IOMMU support for RISC-V machines
6 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
9 The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
10 RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
13 riscv-iommu-pci reference device
14 --------------------------------
16 This device implements the RISC-V IOMMU emulation as recommended by the section
18 class 08h, sub-class 06h and programming interface 00h.
25 .. code-block:: bash
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| /openbmc/openbmc/poky/meta/conf/machine/include/riscv/ |
| H A D | tune-riscv.inc | 1 require conf/machine/include/riscv/arch-riscv.inc
3 TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
4 TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
6 TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
7 TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
9 TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions"
16 TUNE_FEATURES:tune-riscv64 = "riscv64"
17 TUNE_ARCH:tune-riscv64 = "riscv64"
18 TUNE_PKGARCH:tune-riscv64 = "riscv64"
19 PACKAGE_EXTRA_ARCHS:tune-riscv64 = "riscv64"
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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| /openbmc/linux/drivers/cpuidle/ |
| H A D | Kconfig.riscv | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
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| /openbmc/linux/Documentation/translations/zh_CN/riscv/ |
| H A D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/riscv/vm-layout.rst
12 RISC-V Linux上的虚拟内存布局
18 这份文件描述了RISC-V Linux内核使用的虚拟内存布局。
20 32位 RISC-V Linux 内核
23 RISC-V Linux Kernel SV32
24 ------------------------
28 64位 RISC-V Linux 内核
31 RISC-V特权架构文档指出，64位地址 "必须使第63-48位值都等于第47位，否则将发生缺页异常。"：这将虚
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| /openbmc/linux/Documentation/devicetree/bindings/riscv/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /openbmc/u-boot/drivers/timer/ |
| H A D | riscv_timer.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * RISC-V privileged architecture defined generic timer driver
7 * This driver relies on RISC-V platform codes to provide the essential API
9 * by the RISC-V privileged architecture spec.
11 * This driver can be used in both M-mode and S-mode U-Boot.
21 * riscv_get_time() - get the timer counter
25 * @time: the 64-bit timer count as defined by the RISC-V privileged
27 * @return: 0 on success, -ve on error.
41 uc_priv->clock_rate = dev->driver_data; in riscv_timer_probe()
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| /openbmc/qemu/include/semihosting/ |
| H A D | common-semi.h | 3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig.socs | 12 bool "Renesas RISC-V SoCs"
14 This enables support for the RISC-V based Renesas SoCs.
46 bool "T-HEAD RISC-V SoCs"
50 This enables support for the RISC-V based T-HEAD SoCs.
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| /openbmc/u-boot/arch/riscv/cpu/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/uclass-internal.h>
28 debug("unable to find the RISC-V cpu device\n"); in supports_extension()
40 return csr_read(misa) & (1 << (ext - 'a')); in supports_extension()
42 #warning "There is no way to determine the available extensions in S-mode." in supports_extension()
43 #warning "Please convert your board to use the RISC-V CPU driver." in supports_extension()
54 /* probe cpus so that RISC-V timer can be bound */ in riscv_cpu_probe()
57 return log_msg_ret("RISC-V cpus probe failed\n", ret); in riscv_cpu_probe()
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| /openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/ |
| H A D | add-riscv-support.patch | 4 Subject: [PATCH] ldconfig: Add RISC-V support
6 ldconfig-native does not support RISC-V at the moment.
10 Upstream-Status: Backport
12 Signed-off-by: Christoph Muellner <cmuellner@linux.com>
13 ---
19 diff --git a/cache.c b/cache.c
21 --- a/cache.c
23 @@ -125,6 +125,12 @@ print_entry (const char *lib, int flag, unsigned int osversion,
28 + fputs (",soft-float", stdout);
31 + fputs (",double-float", stdout);
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| /openbmc/linux/drivers/perf/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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| /openbmc/u-boot/arch/riscv/ |
| H A D | Kconfig | 1 menu "RISC-V architecture"
12 bool "Support ax25-ae350"
22 # board-specific options below
23 source "board/AndesTech/ax25-ae350/Kconfig"
24 source "board/emulation/qemu-riscv/Kconfig"
27 # platform-specific options below
31 # architecture-specific options below
59 U-Boot and its statically defined symbols must lie within a single 2 GiB
60 address range and must lie between absolute addresses -2 GiB and +2 GiB.
65 U-Boot and its statically defined symbols must be within any single 2 GiB
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| /openbmc/openbmc/poky/meta/recipes-bsp/opensbi/ |
| H A D | opensbi_1.6.bb | 1 SUMMARY = "RISC-V Open Source Supervisor Binary Interface (OpenSBI)"
2 …-source and extensible implementation of the RISC-V SBI specification for a platform specific firm…
4 LICENSE = "BSD-2-Clause"
7 require opensbi-payloads.inc
9 inherit autotools-brokensep deploy
32 rm -r ${D}/include
33 rm -r ${D}/lib*
34 rm -r ${D}/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/payloads
38 install -m 755 ${D}/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_payload.* ${DEPLOYDIR}/
39 install -m 755 ${D}/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_jump.* ${DEPLOYDIR}/
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