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/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dcpld.c32 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
36 cpld_rev_bit(&reg5); in cpld_set_altbank()
40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
54 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
57 cpld_rev_bit(&reg5); in cpld_set_defbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
72 u8 reg5 = (u8)(reg >> 1); in cpld_set_nand() local
75 cpld_rev_bit(&reg5); in cpld_set_nand()
79 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_nand()
88 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
[all …]
/openbmc/u-boot/board/freescale/ls1046ardb/
H A Dcpld.c32 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
36 cpld_rev_bit(&reg5); in cpld_set_altbank()
40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
54 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
57 cpld_rev_bit(&reg5); in cpld_set_defbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
72 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
75 cpld_rev_bit(&reg5); in cpld_set_sd()
79 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_sd()
/openbmc/linux/arch/arm/lib/
H A Dcopy_from_user.S53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
55 ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_to_user.S44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
69 str1w \ptr, \reg5, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_template.S28 * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
41 * str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
/openbmc/u-boot/board/freescale/ls2080aqds/
H A Dls2080aqds.c175 u8 reg5; in config_board_mux() local
177 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
181 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
184 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
191 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
/openbmc/u-boot/board/freescale/ls2080ardb/
H A Dls2080ardb.c183 u8 reg5; in config_board_mux() local
185 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
189 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
192 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
199 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drockchip,rk806.yaml50 The input supply for dcdc-reg5.
78 The input supply for pldo-reg4 and pldo-reg5.
86 The input supply for nldo-reg4 and nldo-reg5.
206 vdd_gpu_mem_s0: dcdc-reg5 {
327 vccio_sd_s0: pldo-reg5 {
394 vdd_0v85_s0: nldo-reg5 {
/openbmc/linux/drivers/net/ethernet/8390/
H A Dwd.c205 unsigned char reg5 = inb(ioaddr+5); in wd_probe1() local
214 dev->mem_start = ((reg5 & 0x1c) + 0xc0) << 12; in wd_probe1()
215 dev->irq = (reg5 & 0xe0) == 0xe0 ? 10 : (reg5 >> 5) + 1; in wd_probe1()
379 ei_status.reg5 = ((dev->mem_start>>19) & 0x1f) | NIC16; in wd_open()
382 outb(ei_status.reg5, ioaddr+WD_CMDREG5); in wd_open()
421 outb(ISA16 | ei_status.reg5, wd_cmdreg+WD_CMDREG5); in wd_get_8390_hdr()
458 outb(ei_status.reg5, wd_cmdreg+WD_CMDREG5); in wd_block_input()
471 outb(ISA16 | ei_status.reg5, wd_cmdreg+WD_CMDREG5); in wd_block_output()
473 outb(ei_status.reg5, wd_cmdreg+WD_CMDREG5); in wd_block_output()
490 outb(ei_status.reg5, wd_cmdreg + WD_CMDREG5 ); in wd_close()
/openbmc/u-boot/arch/arm/lib/
H A Dmemcpy.S24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/openbmc/linux/arch/m68k/atari/
H A Ddebug.c219 int clksrc, clkmode, div, reg3, reg5; in atari_init_scc_port() local
240 reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */; in atari_init_scc_port()
248 SCC_WRITE(5, reg5); in atari_init_scc_port()
258 SCC_WRITE(5, reg5 | 8); in atari_init_scc_port()
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dactive-semi,act8846.yaml32 description: Handle to the INL1 input supply (REG5-7)
110 REG5 {
/openbmc/u-boot/board/freescale/lx2160a/
H A Dlx2160a.c307 u8 reg11, reg5, reg13; in config_board_mux() local
324 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
325 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); in config_board_mux()
326 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-evb1-v10.dts303 vdd_gpu_mem_s0: dcdc-reg5 {
426 vccio_sd_s0: pldo-reg5 {
498 vdd_0v85_s0: nldo-reg5 {
603 vdd_cpu_big1_mem_s0: dcdc-reg5 {
721 vcc_2v8_cam_s0: pldo-reg5 {
792 avdd_1v2_s0: nldo-reg5 {
H A Drk3588-edgeble-neu6b.dtsi176 vdd_ddr_s0: dcdc-reg5 {
300 vccio_sd_s0: pldo-reg5 {
376 vdd_0v75_s0: nldo-reg5 {
H A Drk3588-rock-5b.dts369 vdd_ddr_s0: dcdc-reg5 {
493 vccio_sd_s0: pldo-reg5 {
569 vdd_0v75_s0: nldo-reg5 {
H A Drk3588s-rock-5a.dts483 vdd_ddr_s0: dcdc-reg5 {
607 vccio_sd_s0: pldo-reg5 {
683 vdd_0v75_s0: nldo-reg5 {
/openbmc/u-boot/board/freescale/p2041rdb/
H A Dcpld.c51 u8 reg5 = CPLD_READ(sw_ctl_on); in __cpld_set_altbank() local
53 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); in __cpld_set_altbank()
/openbmc/linux/sound/soc/codecs/
H A Dwm9081.c549 u16 reg1, reg4, reg5; in wm9081_set_fll() local
571 reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5); in wm9081_set_fll()
572 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; in wm9081_set_fll()
576 reg5 |= 0x1; in wm9081_set_fll()
613 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; in wm9081_set_fll()
614 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; in wm9081_set_fll()
615 snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5); in wm9081_set_fll()
H A Dwm8993.c471 u16 reg1, reg4, reg5; in _wm8993_set_fll() local
497 reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5); in _wm8993_set_fll()
498 reg5 &= ~WM8993_FLL_CLK_SRC_MASK; in _wm8993_set_fll()
505 reg5 |= 1; in _wm8993_set_fll()
509 reg5 |= 2; in _wm8993_set_fll()
540 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; in _wm8993_set_fll()
541 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; in _wm8993_set_fll()
542 snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5); in _wm8993_set_fll()
H A Dtas2780.h84 /* TDM Configuration Reg5 */
H A Dtas2764.h82 /* TDM Configuration Reg5 */
/openbmc/linux/arch/sparc/lib/
H A Dcopy_page.S38 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \ argument
41 fsrc2 %reg4, %f56; fsrc2 %reg5, %f58; \
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_rf2959.c77 PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
188 0x17dd43, /* REG5 */ in rf2959_init_hw()

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