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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllgt215.c42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
51 fN = tmp % info->refclk; in gt215_pll_calc()
54 if (fN >= info->refclk / 2) in gt215_pll_calc()
57 if (fN < info->refclk / 2) in gt215_pll_calc()
59 fN = tmp - (N * info->refclk); in gt215_pll_calc()
67 err = abs(freq - (info->refclk * N / M / *P)); in gt215_pll_calc()
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; in gt215_pll_calc()
86 return info->refclk * *pN / *pM / *P; in gt215_pll_calc()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7620-pinctrl.yaml39 pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
40 refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite,
41 wdt refclk, wdt rst, wled]
70 spi refclk, uartf, uartlite, wdt, wled]
138 const: pcie refclk
183 const: refclk
228 const: spi refclk
232 enum: [spi refclk]
255 const: wdt refclk
/openbmc/qemu/hw/timer/
H A Darmv7m_systick.c42 ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); in systick_set_period_from_clock()
101 if (!clock_has_source(s->refclk)) { in systick_read()
105 val = clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1; in systick_read()
107 if (clock_ticks_to_ns(s->refclk, val + 1) != 10 * SCALE_MS) { in systick_read()
142 if (!clock_has_source(s->refclk)) { in systick_write()
143 /* This bit is always 1 if there is no external refclk */ in systick_write()
206 if (!clock_has_source(s->refclk)) { in systick_reset()
207 /* This bit is always 1 if there is no external refclk */ in systick_reset()
222 /* currently using refclk, we can ignore cpuclk changes */ in systick_cpuclk_update()
235 /* currently using cpuclk, we can ignore refclk changes */ in systick_refclk_update()
[all …]
/openbmc/linux/drivers/phy/ti/
H A Dphy-dm816x-usb.c47 struct clk *refclk; member
77 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
78 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
124 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_suspend()
135 error = clk_enable(phy->refclk); in dm816x_usb_phy_runtime_resume()
152 clk_disable(phy->refclk); in dm816x_usb_phy_runtime_resume()
227 phy->refclk = devm_clk_get(phy->dev, "refclk"); in dm816x_usb_phy_probe()
228 if (IS_ERR(phy->refclk)) in dm816x_usb_phy_probe()
229 return PTR_ERR(phy->refclk); in dm816x_usb_phy_probe()
230 error = clk_prepare(phy->refclk); in dm816x_usb_phy_probe()
[all …]
H A Dphy-ti-pipe3.c171 struct clk *refclk; member
607 phy->refclk = devm_clk_get(dev, "refclk"); in ti_pipe3_get_clk()
608 if (IS_ERR(phy->refclk)) { in ti_pipe3_get_clk()
609 dev_err(dev, "unable to get refclk\n"); in ti_pipe3_get_clk()
610 /* older DTBs have missing refclk in SATA PHY in ti_pipe3_get_clk()
614 return PTR_ERR(phy->refclk); in ti_pipe3_get_clk()
823 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 in ti_pipe3_probe()
826 if (!IS_ERR(phy->refclk)) { in ti_pipe3_probe()
827 clk_prepare_enable(phy->refclk); in ti_pipe3_probe()
849 clk_disable_unprepare(phy->refclk); in ti_pipe3_remove()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c1227 u16 refclk; member
1234 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1235 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1243 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1244 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1250 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
[all …]
H A Dintel_dpll.c234 /* LVDS 100mhz refclk limits. */
313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
319 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
336 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
348 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
360 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
368 * Returns whether the given set of divisors are valid for a given refclk with
[all …]
H A Dintel_dpll.h23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsmsc,usb3503.yaml64 Clock used for driving REFCLK signal. If not provided the driver assumes
70 const: refclk
72 refclk-frequency:
75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
76 provided, driver will not set rate of the REFCLK signal and assume that a
122 clock-names = "refclk";
141 clock-names = "refclk";
156 refclk-frequency = <19200000>;
H A Docteon-usb.txt24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
54 cavium,refclk-type = "crystal";
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c207 u32 refclk = priv->ref_clk; in rk_mipi_phy_enable() local
208 u32 remain = refclk; in rk_mipi_phy_enable()
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable()
261 max_prediv = (refclk / (5 * MHz)); in rk_mipi_phy_enable()
262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); in rk_mipi_phy_enable()
268 debug("%s: Invalid refclk value\n", __func__); in rk_mipi_phy_enable()
272 /* Calculate the best refclk and feedback division value for dphy pll */ in rk_mipi_phy_enable()
274 if ((ddr_clk * i % refclk < remain) && in rk_mipi_phy_enable()
275 (ddr_clk * i / refclk) < max_fbdiv) { in rk_mipi_phy_enable()
277 remain = ddr_clk * i % refclk; in rk_mipi_phy_enable()
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dgma_display.h44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
84 extern void gma_clock(int refclk, struct gma_clock_t *clock);
89 struct drm_crtc *crtc, int target, int refclk,
H A Doaktrail_crtc.c41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
128 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
153 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
181 * Returns a set of divisors for the desired target clock with the given refclk,
186 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
[all …]
H A Dcdv_intel_display.c25 int refclk, struct gma_clock_t *best_clock);
365 int refclk) in cdv_intel_limit() argument
373 if (refclk == 96000) in cdv_intel_limit()
379 if (refclk == 27000) in cdv_intel_limit()
384 if (refclk == 27000) in cdv_intel_limit()
393 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
397 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
403 int refclk, in cdv_intel_find_dp_pll() argument
411 switch (refclk) { in cdv_intel_find_dp_pll()
448 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml43 fsl,refclk-pad-mode:
45 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
47 is provided externally via the refclk pad) or OUTPUT(PHY refclock
48 is derived from SoC internal source and provided on the refclk pad).
79 - fsl,refclk-pad-mode
99 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.c161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
268 * Assume refclk is sourced from xtalin in dccg32_get_dccg_ref_freq()
284 /* always program refclk as DTBCLK. No use-case expected to require DPREFCLK as refclk */ in dccg32_set_dpstreamclk()
292 (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
296 (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
300 (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
304 (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); in dccg32_set_dpstreamclk()
/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
76 * We use s->refclk internally and only define it with qdev_init_clock_in() in stm32f100_soc_realize()
80 if (clock_has_source(s->refclk)) { in stm32f100_soc_realize()
81 error_setg(errp, "refclk clock must not be wired up by the board code"); in stm32f100_soc_realize()
95 /* The refclk always runs at frequency HCLK / 8 */ in stm32f100_soc_realize()
96 clock_set_mul_div(s->refclk, 8, 1); in stm32f100_soc_realize()
97 clock_set_source(s->refclk, s->sysclk); in stm32f100_soc_realize()
122 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in stm32f100_soc_realize()
H A Dstm32f205_soc.c80 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f205_soc_initfn()
93 * We use s->refclk internally and only define it with qdev_init_clock_in() in stm32f205_soc_realize()
97 if (clock_has_source(s->refclk)) { in stm32f205_soc_realize()
98 error_setg(errp, "refclk clock must not be wired up by the board code"); in stm32f205_soc_realize()
112 /* The refclk always runs at frequency HCLK / 8 */ in stm32f205_soc_realize()
113 clock_set_mul_div(s->refclk, 8, 1); in stm32f205_soc_realize()
114 clock_set_source(s->refclk, s->sysclk); in stm32f205_soc_realize()
134 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in stm32f205_soc_realize()
H A Dmsf2-soc.c79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn()
97 * We use s->refclk internally and only define it with qdev_init_clock_in() in m2sxxx_soc_realize()
101 if (clock_has_source(s->refclk)) { in m2sxxx_soc_realize()
102 error_setg(errp, "refclk must not be wired up by the board code"); in m2sxxx_soc_realize()
109 * the systick refclk to either /4, /8, /16 or /32, as well as setting in m2sxxx_soc_realize()
114 clock_set_mul_div(s->refclk, 32, 1); in m2sxxx_soc_realize()
115 clock_set_source(s->refclk, s->m3clk); in m2sxxx_soc_realize()
140 qdev_connect_clock_in(armv7m, "refclk", s->refclk); in m2sxxx_soc_realize()
/openbmc/linux/drivers/net/ethernet/arc/
H A Demac_rockchip.c32 struct clk *refclk; member
147 priv->refclk = devm_clk_get(dev, "macref"); in emac_rockchip_probe()
148 if (IS_ERR(priv->refclk)) { in emac_rockchip_probe()
150 PTR_ERR(priv->refclk)); in emac_rockchip_probe()
151 err = PTR_ERR(priv->refclk); in emac_rockchip_probe()
155 err = clk_prepare_enable(priv->refclk); in emac_rockchip_probe()
195 err = clk_set_rate(priv->refclk, 50000000); in emac_rockchip_probe()
241 clk_disable_unprepare(priv->refclk); in emac_rockchip_probe()
254 clk_disable_unprepare(priv->refclk); in emac_rockchip_remove()
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.h14 * refclk: reference frequency, 100 MHz from external oscillator
19 * refclk +-----------+ +------------------+ +---------+ outclk
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
30 refclk-frequency = <24000000>;
32 refclk-type = "crystal";
/openbmc/linux/arch/mips/bcm63xx/
H A Dclk.c423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
454 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
468 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
482 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
497 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
498 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
516 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
[all …]
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c104 /* Refclk selection parameters */
211 * @refclk: reference clock index
220 unsigned int refclk; member
392 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
399 if (gtr_phy->refclk == gtr_phy->lane) in xpsgtr_configure_pll()
404 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
624 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) in xpsgtr_phy_init()
676 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); in xpsgtr_phy_exit()
826 unsigned int refclk; in xpsgtr_xlate() local
856 refclk = args->args[3]; in xpsgtr_xlate()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.c161 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
263 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
268 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
273 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
278 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, in dccg314_set_dpstreamclk()
291 /* Set HPO stream encoder to use refclk to avoid case where PHY is in dccg314_init()
304 dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst, in dccg314_init()

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