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/openbmc/linux/drivers/crypto/hisilicon/
H A Dqm.c364 struct hisi_qm *qm; member
380 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
381 void (*qm_db)(struct hisi_qm *qm, u16 qn,
383 int (*debug_init)(struct hisi_qm *qm);
384 void (*hw_error_init)(struct hisi_qm *qm);
385 void (*hw_error_uninit)(struct hisi_qm *qm);
386 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
387 int (*set_msi)(struct hisi_qm *qm, bool set);
451 static void qm_irqs_unregister(struct hisi_qm *qm);
452 static int qm_reset_device(struct hisi_qm *qm);
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H A Ddebugfs.c42 int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
86 /* define the QM's dfx regs region and region length */
122 static void dump_show(struct hisi_qm *qm, void *info, in dump_show() argument
125 struct device *dev = &qm->pdev->dev; in dump_show()
137 static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) in qm_sqc_dump() argument
139 struct device *dev = &qm->pdev->dev; in qm_sqc_dump()
149 if (ret || qp_id >= qm->qp_num) { in qm_sqc_dump()
150 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump()
154 sqc = hisi_qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma); in qm_sqc_dump()
158 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 1); in qm_sqc_dump()
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H A Dqm_common.h79 void *hisi_qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
81 void hisi_qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
83 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);
84 void hisi_qm_set_algqos_init(struct hisi_qm *qm);
H A DMakefile6 hisi_qm-objs = qm.o sgl.o debugfs.o
/openbmc/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c306 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
394 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
398 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
399 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
424 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
439 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument
443 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config()
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H A Dsec.h169 struct hisi_qm *qm; member
188 struct hisi_qm qm; member
231 int sec_register_to_crypto(struct hisi_qm *qm);
232 void sec_unregister_from_crypto(struct hisi_qm *qm);
233 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low);
/openbmc/linux/drivers/crypto/hisilicon/hpre/
H A Dhpre_main.c358 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) in hpre_check_alg_support() argument
362 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; in hpre_check_alg_support()
371 struct hisi_qm *qm = s->private; in hpre_diff_regs_show() local
373 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hpre_diff_regs_show()
458 static void hpre_config_pasid(struct hisi_qm *qm) in hpre_config_pasid() argument
462 if (qm->ver >= QM_HW_V3) in hpre_config_pasid()
465 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
466 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
467 if (qm->use_sva) { in hpre_config_pasid()
474 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
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H A Dhpre.h14 * type used in qm sqc DW6.
71 struct hisi_qm qm; member
104 int hpre_algs_register(struct hisi_qm *qm);
105 void hpre_algs_unregister(struct hisi_qm *qm);
106 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg);
H A Dhpre_crypto.c228 pci_err(qp->qm->pdev, "Can not start qp!\n"); in hpre_get_qp_and_start()
388 ctx->dev = &qp->qm->pdev->dev; in hpre_ctx_set()
390 hpre = container_of(ctx->qp->qm, struct hpre, qm); in hpre_ctx_set()
2100 static int hpre_register_rsa(struct hisi_qm *qm) in hpre_register_rsa() argument
2104 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_register_rsa()
2110 dev_err(&qm->pdev->dev, "failed to register rsa (%d)!\n", ret); in hpre_register_rsa()
2115 static void hpre_unregister_rsa(struct hisi_qm *qm) in hpre_unregister_rsa() argument
2117 if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP)) in hpre_unregister_rsa()
2123 static int hpre_register_dh(struct hisi_qm *qm) in hpre_register_dh() argument
2127 if (!hpre_check_alg_support(qm, HPRE_DRV_DH_MASK_CAP)) in hpre_register_dh()
[all …]
/openbmc/linux/drivers/crypto/hisilicon/zip/
H A Dzip_main.c368 struct hisi_qm *qm = s->private; in hzip_diff_regs_show() local
370 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hzip_diff_regs_show()
461 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) in hisi_zip_alg_support() argument
465 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; in hisi_zip_alg_support()
472 static int hisi_zip_set_high_perf(struct hisi_qm *qm) in hisi_zip_set_high_perf() argument
477 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
484 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
485 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
489 pci_err(qm->pdev, "failed to set perf mode\n"); in hisi_zip_set_high_perf()
494 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) in hisi_zip_open_sva_prefetch() argument
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H A Dzip_crypto.c231 dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n"); in hisi_zip_create_req()
340 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_do_work()
412 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_acomp_cb()
448 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_acompress()
478 struct device *dev = &qp_ctx->qp->qm->pdev->dev; in hisi_zip_adecompress()
506 struct device *dev = &qp->qm->pdev->dev; in hisi_zip_start_qp()
569 hisi_zip = container_of(qps[0]->qm, struct hisi_zip, qm); in hisi_zip_ctx_init()
587 if (hisi_zip->qm.ver < QM_HW_V3) in hisi_zip_ctx_init()
664 dev = &tmp->qp->qm->pdev->dev; in hisi_zip_create_sgl_pool()
677 hisi_acc_free_sgl_pool(&ctx->qp_ctx[HZIP_QPC_COMP].qp->qm->pdev->dev, in hisi_zip_create_sgl_pool()
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H A Dzip.h27 struct hisi_qm qm; member
85 int hisi_zip_register_to_crypto(struct hisi_qm *qm);
86 void hisi_zip_unregister_from_crypto(struct hisi_qm *qm);
87 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);
/openbmc/linux/include/linux/
H A Dhisi_acc_qm.h16 /* qm user domain */
72 /* qm cache */
253 int (*hw_init)(struct hisi_qm *qm);
254 void (*hw_err_enable)(struct hisi_qm *qm);
255 void (*hw_err_disable)(struct hisi_qm *qm);
256 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
257 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
258 void (*open_axi_master_ooo)(struct hisi_qm *qm);
259 void (*close_axi_master_ooo)(struct hisi_qm *qm);
260 void (*open_sva_prefetch)(struct hisi_qm *qm);
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/openbmc/linux/drivers/vfio/pci/hisilicon/
H A Dhisi_acc_vfio_pci.c20 static int qm_wait_dev_not_ready(struct hisi_qm *qm) in qm_wait_dev_not_ready() argument
24 return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE, in qm_wait_dev_not_ready()
33 static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs) in qm_check_reg_state() argument
38 state = readl(qm->io_base + regs); in qm_check_reg_state()
41 state = readl(qm->io_base + regs); in qm_check_reg_state()
48 static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr, in qm_read_regs() argument
57 data[i] = readl(qm->io_base + reg_addr); in qm_read_regs()
64 static int qm_write_regs(struct hisi_qm *qm, u32 reg, in qm_write_regs() argument
73 writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET); in qm_write_regs()
78 static int qm_get_vft(struct hisi_qm *qm, u32 *base) in qm_get_vft() argument
[all …]
H A Dhisi_acc_vfio_pci.h54 /* QM match information */
62 /* QM reserved match information */
65 /* QM RW regs */
79 /* QM reserved 5 regs */
82 /* QM memory init information */
/openbmc/linux/Documentation/ABI/testing/
H A Ddebugfs-hisi-sec13 has a QM. This file can be used to select the QM which below
14 qm refers to.
27 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_regs
30 Description: Dump of QM related debug registers.
34 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/current_q
37 Description: One QM of SEC may contain multiple queues. Select specific
41 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/clear_enable
45 the SEC's QM debug registers.
49 What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/err_irq
53 QM task completion.
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H A Ddebugfs-hisi-zip26 has a QM. Select the QM which below qm refers to.
39 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/regs
42 Description: Dump of QM related debug registers.
46 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
49 Description: One QM may contain multiple queues. Select specific queue to
53 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
56 Description: QM debug registers(regs) read clear control. 1 means enable
62 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/err_irq
66 QM task completion.
69 What: /sys/kernel/debug/hisi_zip/<bdf>/qm/aeq_irq
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H A Ddebugfs-hisi-hpre27 has a QM. Select the QM which below qm refers to.
46 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/regs
49 Description: Dump debug registers from the QM.
53 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q
56 Description: One QM may contain multiple queues. Select specific queue to
60 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/clear_enable
63 Description: QM debug registers(regs) read clear control. 1 means enable
69 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/err_irq
73 QM task completion.
76 What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/aeq_irq
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/openbmc/qemu/target/arm/tcg/
H A Dmve.decode23 %qm 5:1 1:3
41 &1op qd qm size
42 &2op qd qm qn size
45 &2shift qd qm shift size
48 &vcmp qm qn size mask
51 &vmaxv qm rda size
52 &vabav qn qm rda size
53 &vldst_sg qd qm rn size msize os
54 &vldst_sg_imm qd qm a w imm
65 qd=%qd qm=%qm msize=%sg_msize
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H A Dtranslate-mve.c220 TCGv_ptr qd, qm; in DO_VLDST_WIDE_NARROW() local
223 !mve_check_qreg_bank(s, a->qd | a->qm) || in DO_VLDST_WIDE_NARROW()
236 qm = mve_qreg_ptr(a->qm); in DO_VLDST_WIDE_NARROW()
237 fn(tcg_env, qd, qm, addr); in DO_VLDST_WIDE_NARROW()
245 * the offsets in Qm should be scaled by the element size.
265 if (a->qd == a->qm) { in trans_VLDR_S_sg()
285 if (a->qd == a->qm) { in trans_VLDR_U_sg()
314 TCGv_ptr qd, qm; in do_ldst_sg_imm() local
317 !mve_check_qreg_bank(s, a->qd | a->qm) || in do_ldst_sg_imm()
332 qm = mve_qreg_ptr(a->qm); in do_ldst_sg_imm()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c871 "QM: Queue is not empty",
877 "QM: VOQ_0, VOQ credit is not equal to initial credit",
883 "QM: VOQ_1, VOQ credit is not equal to initial credit",
889 "QM: VOQ_4, VOQ credit is not equal to initial credit",
895 "QM: P0 Byte credit is not equal to initial credit",
901 "QM: P1 Byte credit is not equal to initial credit",
1165 "QM: Interrupt status is not 0",
1201 "QM: Credit error register is not 0 (byte or credit overflow/underflow)",
1861 "QM: XQM wrc_fifolvl is not 0",
1867 "QM: UQM wrc_fifolvl is not 0",
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dcoretemp.rst71 i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
154 i7 840QM/820/740/720 100
/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_nav.h55 /* QM module addresses */
71 /* QM configuration parameters */
/openbmc/linux/drivers/media/platform/nxp/imx-jpeg/
H A DKconfig11 This is a video4linux2 driver for the i.MX8 QXP/QM integrated
/openbmc/linux/fs/xfs/
H A Dxfs_stats.c55 { "qm", xfsstats_offset(xs_xstrat_bytes)}, in xfs_stats_format()
128 seq_puts(m, "qm"); in xqmstat_proc_show()

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