1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ef454717SKhoronzhuk, Ivan /* 3ef454717SKhoronzhuk, Ivan * Multicore Navigator definitions 4ef454717SKhoronzhuk, Ivan * 5ef454717SKhoronzhuk, Ivan * (C) Copyright 2012-2014 6ef454717SKhoronzhuk, Ivan * Texas Instruments Incorporated, <www.ti.com> 7ef454717SKhoronzhuk, Ivan */ 8ef454717SKhoronzhuk, Ivan 9ef454717SKhoronzhuk, Ivan #ifndef _KEYSTONE_NAV_H_ 10ef454717SKhoronzhuk, Ivan #define _KEYSTONE_NAV_H_ 11ef454717SKhoronzhuk, Ivan 12ef454717SKhoronzhuk, Ivan #include <asm/arch/hardware.h> 13ef454717SKhoronzhuk, Ivan #include <asm/io.h> 14ef454717SKhoronzhuk, Ivan 15ef454717SKhoronzhuk, Ivan #define QM_OK 0 16ef454717SKhoronzhuk, Ivan #define QM_ERR -1 17ef454717SKhoronzhuk, Ivan #define QM_DESC_TYPE_HOST 0 18ef454717SKhoronzhuk, Ivan #define QM_DESC_PSINFO_IN_DESCR 0 19ef454717SKhoronzhuk, Ivan #define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \ 20ef454717SKhoronzhuk, Ivan (QM_DESC_PSINFO_IN_DESCR << 22) 21ef454717SKhoronzhuk, Ivan 22ef454717SKhoronzhuk, Ivan /* Packet Info */ 23ef454717SKhoronzhuk, Ivan #define QM_DESC_PINFO_EPIB 1 24ef454717SKhoronzhuk, Ivan #define QM_DESC_PINFO_RETURN_OWN 1 25ef454717SKhoronzhuk, Ivan #define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \ 26ef454717SKhoronzhuk, Ivan (QM_DESC_PINFO_RETURN_OWN << 15) 27ef454717SKhoronzhuk, Ivan 28ef454717SKhoronzhuk, Ivan struct qm_cfg_reg { 29ef454717SKhoronzhuk, Ivan u32 revision; 30ef454717SKhoronzhuk, Ivan u32 __pad1; 31ef454717SKhoronzhuk, Ivan u32 divert; 32ef454717SKhoronzhuk, Ivan u32 link_ram_base0; 33ef454717SKhoronzhuk, Ivan u32 link_ram_size0; 34ef454717SKhoronzhuk, Ivan u32 link_ram_base1; 35ef454717SKhoronzhuk, Ivan u32 link_ram_size1; 36ef454717SKhoronzhuk, Ivan u32 link_ram_base2; 37ef454717SKhoronzhuk, Ivan u32 starvation[0]; 38ef454717SKhoronzhuk, Ivan }; 39ef454717SKhoronzhuk, Ivan 40ef454717SKhoronzhuk, Ivan struct descr_mem_setup_reg { 41ef454717SKhoronzhuk, Ivan u32 base_addr; 42ef454717SKhoronzhuk, Ivan u32 start_idx; 43ef454717SKhoronzhuk, Ivan u32 desc_reg_size; 44ef454717SKhoronzhuk, Ivan u32 _res0; 45ef454717SKhoronzhuk, Ivan }; 46ef454717SKhoronzhuk, Ivan 47ef454717SKhoronzhuk, Ivan struct qm_reg_queue { 48ef454717SKhoronzhuk, Ivan u32 entry_count; 49ef454717SKhoronzhuk, Ivan u32 byte_count; 50ef454717SKhoronzhuk, Ivan u32 packet_size; 51ef454717SKhoronzhuk, Ivan u32 ptr_size_thresh; 52ef454717SKhoronzhuk, Ivan }; 53ef454717SKhoronzhuk, Ivan 54ef454717SKhoronzhuk, Ivan struct qm_config { 55ef454717SKhoronzhuk, Ivan /* QM module addresses */ 56ef454717SKhoronzhuk, Ivan u32 stat_cfg; /* status and config */ 57ef454717SKhoronzhuk, Ivan struct qm_reg_queue *queue; /* management region */ 58ef454717SKhoronzhuk, Ivan u32 mngr_vbusm; /* management region (VBUSM) */ 59ef454717SKhoronzhuk, Ivan u32 i_lram; /* internal linking RAM */ 60ef454717SKhoronzhuk, Ivan struct qm_reg_queue *proxy; 61ef454717SKhoronzhuk, Ivan u32 status_ram; 62ef454717SKhoronzhuk, Ivan struct qm_cfg_reg *mngr_cfg; 63ef454717SKhoronzhuk, Ivan /* Queue manager config region */ 64ef454717SKhoronzhuk, Ivan u32 intd_cfg; /* QMSS INTD config region */ 65ef454717SKhoronzhuk, Ivan struct descr_mem_setup_reg *desc_mem; 66ef454717SKhoronzhuk, Ivan /* descritor memory setup region*/ 67ef454717SKhoronzhuk, Ivan u32 region_num; 68ef454717SKhoronzhuk, Ivan u32 pdsp_cmd; /* PDSP1 command interface */ 69ef454717SKhoronzhuk, Ivan u32 pdsp_ctl; /* PDSP1 control registers */ 70ef454717SKhoronzhuk, Ivan u32 pdsp_iram; 71ef454717SKhoronzhuk, Ivan /* QM configuration parameters */ 72ef454717SKhoronzhuk, Ivan 73ef454717SKhoronzhuk, Ivan u32 qpool_num; /* */ 74ef454717SKhoronzhuk, Ivan }; 75ef454717SKhoronzhuk, Ivan 76ef454717SKhoronzhuk, Ivan struct qm_host_desc { 77ef454717SKhoronzhuk, Ivan u32 desc_info; 78ef454717SKhoronzhuk, Ivan u32 tag_info; 79ef454717SKhoronzhuk, Ivan u32 packet_info; 80ef454717SKhoronzhuk, Ivan u32 buff_len; 81ef454717SKhoronzhuk, Ivan u32 buff_ptr; 82ef454717SKhoronzhuk, Ivan u32 next_bdptr; 83ef454717SKhoronzhuk, Ivan u32 orig_buff_len; 84ef454717SKhoronzhuk, Ivan u32 orig_buff_ptr; 85ef454717SKhoronzhuk, Ivan u32 timestamp; 86ef454717SKhoronzhuk, Ivan u32 swinfo[3]; 87ef454717SKhoronzhuk, Ivan u32 ps_data[20]; 88ef454717SKhoronzhuk, Ivan }; 89ef454717SKhoronzhuk, Ivan 90ef454717SKhoronzhuk, Ivan #define HDESC_NUM 256 91ef454717SKhoronzhuk, Ivan 92ef454717SKhoronzhuk, Ivan int qm_init(void); 93ef454717SKhoronzhuk, Ivan void qm_close(void); 94ef454717SKhoronzhuk, Ivan void qm_push(struct qm_host_desc *hd, u32 qnum); 95ef454717SKhoronzhuk, Ivan struct qm_host_desc *qm_pop(u32 qnum); 96ef454717SKhoronzhuk, Ivan 97ef454717SKhoronzhuk, Ivan void qm_buff_push(struct qm_host_desc *hd, u32 qnum, 98ef454717SKhoronzhuk, Ivan void *buff_ptr, u32 buff_len); 99ef454717SKhoronzhuk, Ivan 100ef454717SKhoronzhuk, Ivan struct qm_host_desc *qm_pop_from_free_pool(void); 101ef454717SKhoronzhuk, Ivan void queue_close(u32 qnum); 102ef454717SKhoronzhuk, Ivan 103ef454717SKhoronzhuk, Ivan /* 104ef454717SKhoronzhuk, Ivan * DMA API 105ef454717SKhoronzhuk, Ivan */ 106ef454717SKhoronzhuk, Ivan #define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \ 107ef454717SKhoronzhuk, Ivan psloc, sopoff, qmgr, qnum) \ 108ef454717SKhoronzhuk, Ivan (((einfo & 1) << 30) | \ 109ef454717SKhoronzhuk, Ivan ((psinfo & 1) << 29) | \ 110ef454717SKhoronzhuk, Ivan ((rxerr & 1) << 28) | \ 111ef454717SKhoronzhuk, Ivan ((desc & 3) << 26) | \ 112ef454717SKhoronzhuk, Ivan ((psloc & 1) << 25) | \ 113ef454717SKhoronzhuk, Ivan ((sopoff & 0x1ff) << 16) | \ 114ef454717SKhoronzhuk, Ivan ((qmgr & 3) << 12) | \ 115ef454717SKhoronzhuk, Ivan ((qnum & 0xfff) << 0)) 116ef454717SKhoronzhuk, Ivan 117ef454717SKhoronzhuk, Ivan #define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \ 118ef454717SKhoronzhuk, Ivan (((fd0qm & 3) << 28) | \ 119ef454717SKhoronzhuk, Ivan ((fd0qnum & 0xfff) << 16) | \ 120ef454717SKhoronzhuk, Ivan ((fd1qm & 3) << 12) | \ 121ef454717SKhoronzhuk, Ivan ((fd1qnum & 0xfff) << 0)) 122ef454717SKhoronzhuk, Ivan 123ef454717SKhoronzhuk, Ivan #define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) 124ef454717SKhoronzhuk, Ivan #define CPDMA_CHAN_A_TDOWN (1 << 30) 125ef454717SKhoronzhuk, Ivan #define TDOWN_TIMEOUT_COUNT 100 126ef454717SKhoronzhuk, Ivan 127ef454717SKhoronzhuk, Ivan struct global_ctl_regs { 128ef454717SKhoronzhuk, Ivan u32 revision; 129ef454717SKhoronzhuk, Ivan u32 perf_control; 130ef454717SKhoronzhuk, Ivan u32 emulation_control; 131ef454717SKhoronzhuk, Ivan u32 priority_control; 132ef454717SKhoronzhuk, Ivan u32 qm_base_addr[4]; 133ef454717SKhoronzhuk, Ivan }; 134ef454717SKhoronzhuk, Ivan 135ef454717SKhoronzhuk, Ivan struct tx_chan_regs { 136ef454717SKhoronzhuk, Ivan u32 cfg_a; 137ef454717SKhoronzhuk, Ivan u32 cfg_b; 138ef454717SKhoronzhuk, Ivan u32 res[6]; 139ef454717SKhoronzhuk, Ivan }; 140ef454717SKhoronzhuk, Ivan 141ef454717SKhoronzhuk, Ivan struct rx_chan_regs { 142ef454717SKhoronzhuk, Ivan u32 cfg_a; 143ef454717SKhoronzhuk, Ivan u32 res[7]; 144ef454717SKhoronzhuk, Ivan }; 145ef454717SKhoronzhuk, Ivan 146ef454717SKhoronzhuk, Ivan struct rx_flow_regs { 147ef454717SKhoronzhuk, Ivan u32 control; 148ef454717SKhoronzhuk, Ivan u32 tags; 149ef454717SKhoronzhuk, Ivan u32 tag_sel; 150ef454717SKhoronzhuk, Ivan u32 fdq_sel[2]; 151ef454717SKhoronzhuk, Ivan u32 thresh[3]; 152ef454717SKhoronzhuk, Ivan }; 153ef454717SKhoronzhuk, Ivan 154ef454717SKhoronzhuk, Ivan struct pktdma_cfg { 155ef454717SKhoronzhuk, Ivan struct global_ctl_regs *global; 156ef454717SKhoronzhuk, Ivan struct tx_chan_regs *tx_ch; 157ef454717SKhoronzhuk, Ivan u32 tx_ch_num; 158ef454717SKhoronzhuk, Ivan struct rx_chan_regs *rx_ch; 159ef454717SKhoronzhuk, Ivan u32 rx_ch_num; 160ef454717SKhoronzhuk, Ivan u32 *tx_sched; 161ef454717SKhoronzhuk, Ivan struct rx_flow_regs *rx_flows; 162ef454717SKhoronzhuk, Ivan u32 rx_flow_num; 163ef454717SKhoronzhuk, Ivan 164ef454717SKhoronzhuk, Ivan u32 rx_free_q; 165ef454717SKhoronzhuk, Ivan u32 rx_rcv_q; 166ef454717SKhoronzhuk, Ivan u32 tx_snd_q; 167ef454717SKhoronzhuk, Ivan 168ef454717SKhoronzhuk, Ivan u32 rx_flow; /* flow that is used for RX */ 169ef454717SKhoronzhuk, Ivan }; 170ef454717SKhoronzhuk, Ivan 1719ea9021aSKhoronzhuk, Ivan extern struct pktdma_cfg netcp_pktdma; 1729ea9021aSKhoronzhuk, Ivan 173ef454717SKhoronzhuk, Ivan /* 174ef454717SKhoronzhuk, Ivan * packet dma user allocates memory for rx buffers 175ef454717SKhoronzhuk, Ivan * and describe it in the following structure 176ef454717SKhoronzhuk, Ivan */ 177ef454717SKhoronzhuk, Ivan struct rx_buff_desc { 178ef454717SKhoronzhuk, Ivan u8 *buff_ptr; 179ef454717SKhoronzhuk, Ivan u32 num_buffs; 180ef454717SKhoronzhuk, Ivan u32 buff_len; 181ef454717SKhoronzhuk, Ivan u32 rx_flow; 182ef454717SKhoronzhuk, Ivan }; 183ef454717SKhoronzhuk, Ivan 1849ea9021aSKhoronzhuk, Ivan int ksnav_close(struct pktdma_cfg *pktdma); 1859ea9021aSKhoronzhuk, Ivan int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); 1869ea9021aSKhoronzhuk, Ivan int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); 1879ea9021aSKhoronzhuk, Ivan void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); 1889ea9021aSKhoronzhuk, Ivan void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); 189ef454717SKhoronzhuk, Ivan 190ef454717SKhoronzhuk, Ivan #endif /* _KEYSTONE_NAV_H_ */ 191